JPH0528040A - Quick memory access system - Google Patents

Abstract

PURPOSE:To enable quick memory access with relatively less hardware amount and easy-to-control manner by reducing erroneous penalties caused by erroneous hits on a cache memory. CONSTITUTION:In a computer system performing a quick access using a cache memory 51, a high-speed non-cache memory 54 is directly connected to a CPU bus 41 other than the cache memory 51. Data and codes to be frequently accessed are stored in the non-cache memory 54, and a decision means 32a in a memory controller 32 selects the non-cache memory 54 or the cache memory 51. The normal data and codes are accessed through the cache memory 51 by a CPU 31, the data and codes to be frequently accessed are directly accessed to the non-cache memory 54 by the CPU 31. Thus, the memory access speed can be further increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed memory access system for data and codes for executing programs at high speed in a computer system having a cache memory.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents.

Nikkei Data Pro, "32-bit Microprocessor Overview-Companies, Strategies, Technologies, Market Trends", (Sho 61-12-10) Nikkei McGraw-Hill Co. 244
Conventionally, in a computer system having a central processing unit (CPU), a memory, and the like, an inexpensive and large-capacity low-speed memory, a medium-capacity and medium-speed memory are used to fill the speed difference between the CPU and the memory. It has a memory hierarchical structure such as a memory and an expensive, small-capacity, high-speed memory. Usually, of the three layers of memory, a low-speed and large-capacity memory is called a secondary memory and is composed of a hard disk, and a medium- and medium-speed memory is called a main memory. RA
M), a small-capacity high-speed memory is called a cache memory, and is composed of a high-speed semiconductor memory (for example, static RAM). An example of the configuration of such a computer system is shown in FIG.

FIG. 2 is a block diagram showing the outline of a conventional computer system.

This computer system is provided with a CPU 1 for program controlling the entire system and a memory controller 2 for selecting a plurality of memories. C
A cache memory 21 is connected to PU1 via a CPU bus 11. Further, the cache memory 21 is connected to the system bus 12, and the main memory 22 and the hard disk 23 are connected to the system bus 12.

A cache memory 21 and a main memory 22
And the hard disk 23 is the memory controller 2,
Selection between memories and control such as read / write are performed.
Among them, the cache memory 21 is a memory that is placed between the CPU 1 and the main memory 22 and has a fast access time, as described in the above document. The cache memory 21 copies a part of the contents of the main memory onto the cache memory 21 so that most of the accesses to the main memory 22 can be performed by accessing the cache memory 21. It has the function of improving the program execution performance.

The capacity of the cache memory 21 is extremely smaller than that of the main memory 22. Therefore, the main memory 2
It is necessary to have a rule that determines where on the cache memory 21 the data on 2 is associated. This association method includes, for example, Set Associat
ive method, Fully Associativ
e) method and direct mapping (Direct Mappi)
ng) method etc. Of these, the basic set associative method is a method in which the cache memory 21 and the main memory 22 are divided into block (line) units and the units are associated with each other.

In the computer system of FIG. 2, C
When the PU1 accesses the main memory 22, when the data exists in the cache memory 21 (this is called a cache hit), the contents of the cache memory 21 are directly used to perform a high-speed access to the CPU1. The program execution performance of is improved. On the other hand, if the data to be accessed does not exist in the cache memory 21 (this is called cache miss hit), the corresponding data or code must be brought from the main memory 22 to the cache memory 21 via the system bus 12. .. Furthermore, it is impossible to guarantee a hit rate of 100% due to various memory access modes. Therefore, various methods have been proposed to increase the hit rate of the cache memory.

[0009]

However, in the conventional high speed memory access method, the cache memory 21 is used to fill the speed difference between the CPU 1 and the main memory 22, and the hit rate of the cache memory 21 is increased. Therefore, various methods have been proposed. However, in these various methods, the control becomes complicated and the amount of hardware increases, and it has been difficult to propose a high-speed memory access method which is technically sufficiently satisfactory.

The present invention solves, as a problem of the prior art, a high-speed memory access method that solves the problem that it is difficult to perform an accurate high-speed memory access without complicating control and increasing the amount of hardware. Is provided.

[0011]

In order to solve the above-mentioned problems, the present invention provides a high-speed access memory system of a computer system for performing high-speed access using a cache memory provided between a CPU and a main memory, in which a bus is used. A high-speed non-cache memory connected to the CPU via a CPU and accessible by a non-cache, and which of the cache memory and the non-cache memory is the access target of the CPU is determined according to the processing content. And a determining means.

Then, using this non-cache memory and the judging means, data and codes that are frequently accessed are stored in the non-cache memory, and the non-cache memory specified by the judgment result of the judging means is stored in the non-cache memory. The CPU is directly accessed.

[0013]

According to the present invention, since the high-speed memory access system is configured as described above, processing programs such as CPU register saving, global variable storage, and interrupt requesting a response at high speed and at a fixed time can be executed. It is stored in the non-cache memory in advance. Then, normal data and codes are accessed by the CPU via the cache memory.
Since the data and the code that are frequently accessed are stored in the non-cache memory, the determining means 32a.
The non-cache memory is selected by, and the CPU accesses it.

This makes it possible to perform memory access at a higher speed with a simple control, with little increase in the amount of hardware. Therefore, the above problem can be solved.

[0015]

FIG. 1 is a block diagram of a computer system showing an embodiment of the present invention.

This computer system is provided with a CPU 31 for program-controlling the entire system, and a memory controller 32 for controlling selection between a plurality of memories and read / write. The CPU 31 is connected to the cache memory 51 via the CPU bus 41 as in the conventional case, and the cache memory 51 is connected to the system bus 42.
It is connected to the. A main memory 52 and a hard disk 53 are connected to the system bus 42.

This computer system is different from the conventional one in that the cache memory 5 connected to the CPU bus 41 is used.
1 is a non-cache memory 54 such as a high-speed static RAM that can be accessed by non-cache.
It is connected to the PU bus 41. Further, in the memory controller 32 controlled by the CPU 31, there is provided a judging means 32a for judging which of the cache memory 51 and the non-cache memory 54 is the access target of the CPU 31 according to the processing content. Has been.

Next, a high speed memory access system in the computer system of FIG. 1 will be described.

Normal data and codes are stored in the main memory 52.
Data and codes stored in the non-cache memory 54 are stored in advance in the non-cache memory 54. For example, a register save destination and its save program when an interrupt occurs or an internal register overflow in the CPU, a global variable, and a processing program such as an interrupt that requires a response (real-time processing) at high speed and in a fixed time are stored in a non-cache memory. It is stored in 54.

When the CPU 31 accesses normal data or code, the judging means 3 in the memory controller 32 is used.
2a judges the processing content and selects the cache memory 51. Then, when normal data or code exists in the cache memory 51, the CPU 31 directly accesses the cache memory 51. When the corresponding data or code is not in the cache memory 51, the memory controller 32 causes the main memory 52
Is controlled to transfer the corresponding data or code from the main memory 52 to the cache memory 52 via the system bus 42. The CPU 31 has access to the transferred data or code.

As described above, normal data and codes are accessed via the cache memory 51, but frequently accessed data and codes are stored in the non-cache memory 54 in advance, so the memory controller 32 is used.
The non-cache memory 5 by the determination means 32a in the
4 is selected, and the data and code in the non-cache memory 54 are accessed by the CPU 31 via the CPU bus 41. At this time, the non-cache memory 54 stores C
By mapping in the memory space of the PU 31 and excluding the memory space from the cache area, it is possible to distinguish the access between the cache memory 51 and the non-cache memory 54.

In the high speed memory access system of this embodiment,
It has the following advantages.

(A) Since frequently accessed data and codes are stored in the non-cache memory 54, the miss penalty at the time of a cache miss hit to the cache memory 51 is reduced as in the prior art, and C
The program execution performance of the PU 31 is improved.

(B) Since the CPU 31 can directly access the non-cache memory 54, real-time processing such as interruption can be performed at high speed. Since the response speed, which is important for real-time processing, can be easily estimated, system design becomes simple.

(C) Judging means 3 for judging and selecting the cache memory 51 and the non-cache memory 54
Since 2a can be configured by a decoder or the like having a simple circuit configuration, it is possible to add a relatively small amount of hardware. Moreover, since the cache memory 51 and the non-cache memory 54 are selected, and the CPU 31 directly accesses the non-cache memory 54 when the non-cache memory 54 is selected, the control is simple.

(D) Since the access method to the non-cache memory 54 is independent of the control method (algorithm) of the cache memory, the present embodiment can be applied to various methods such as the set associative method as the control method of the cache memory 51. Examples can be applied.

(E) As one method for realizing the high-speed memory access method, a compiler, which is a translation program for translating a program written in a compiler language that is easy for humans to translate into a machine language, is used to allocate the register time in the CPU 31. There is also a method of shortening the access speed to increase the speed. By adding the non-cache memory 54 to the CPU 31 of such a method as in the present embodiment, the processing time of register allocation by the compiler can be shortened, and thereby the access speed can be further increased.

The present invention is not limited to the above embodiment,
For example, various modifications are possible such as adding a functional block such as DMA (direct memory access) for transferring data between the input / output device and the memory without passing through the CPU 31 to the computer system of FIG.

[0029]

As described above in detail, according to the present invention, a high speed non-cache memory is connected to the CPU via a bus in addition to the cache memory, and frequently accessed data and codes are stored in the non-cache memory. Since the non-cache memory which is stored in the cache memory and selected by the determining means can be directly accessed by the CPU, the miss penalty due to the miss hit to the cache memory is reduced and the program execution performance of the CPU is improved.

Moreover, since frequently-used data and codes are stored in the non-cache memory, the CPU can directly use the data and codes, the control is simple, the increase in the amount of hardware is small, and the memory access is fast. it can. Therefore, the overall processing speed of the computer system is improved, and the reliability of the computer system is further improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration block diagram of a computer system showing an embodiment of the present invention.

FIG. 2 is a schematic block diagram of a conventional computer system.

[Explanation of symbols]

 31 CPU 32 Memory Controller 32a Judgment Unit 41 CPU Bus 51 Cache Memory 52 Main Memory 54 Non-Cache Memory

Claims (1)

Claim: What is claimed is: 1. A high-speed memory access method for a computer system for performing high-speed access using a cache memory provided between a central processing unit and a main memory, wherein the central processing unit is provided via a bus. A high-speed non-cache memory which is connected to the non-cache and which can be accessed by a non-cache; Is used to store frequently accessed data and codes in the non-cache memory, and the central processing unit directly accesses the non-cache memory designated by the determination result of the determination means. High-speed memory access method.