JPH0527989A - Exception processing device for computer system - Google Patents

Abstract

PURPOSE:To enable a correct exception processing corresponding to the kind of access error by obtaining plural exception vectors by accessing various tables corresponding to the cause of exception. CONSTITUTION:In the case of the access error caused by a cause A, a select signal CS 1 is asserted since a latch 1 is not set, and vectors are conventionally read from a memory 4. When a cause holding latch 1 is set and the vectors are read, a select signal CS 2 in another space is asserted. Therefore, the various vectors can be outputted in respect to the access error due to a cause B. When the vectors are read by the select signal CS 2, the cause holding latch 1 is cleared. In this case, since the exception is processed by causes from the biginning, judgement is not missed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exception handling device for a computer system, and more particularly to an exception handling device for a computer system capable of reliably distributing exception handling even when there are a plurality of interrupt factors.

[0002]

2. Description of the Related Art Generally, a microprocessor which has been widely used recently is generally called "Exception" when it encounters various abnormal states (access error, interrupt, division by 0, etc.).
) ”Is designed to do the processing.

When an exception occurs, the corresponding vector is read from the table indicating the address (vector) of the exception handling routine, and control is transferred to that routine. The position of the vector in the table is predetermined for each exception.

Exceptions are divided into several groups according to their priority. For example, the access error belongs to the highest rank and is accepted immediately after the end of the corresponding access.

Also, a bus time-out, a memory fault, etc. can cause an access error. Even if it is the same access error, it is sufficient to retry with a memory fault. When the I / O times out, the I / O
To deal with by disconnecting.

[0006]

However, since there is only one vector storage location (= one vector) for an access error, the factor is S / W based on external information in the processing routine. You have to determine.

If the next access error occurs between the error recognition and the determination, the information is rewritten, and the correct processing cannot be executed. This situation will be described with reference to FIG. In this figure, 1 is a factor holding latch, 2 is an OR gate for passing factors A and B, 3 is a CPU, 4 is a memory as a vector table,
An address decoder 5 generates an address for accessing the memory 4.

When an access error occurs, the presence or absence of the factor B at that time is recorded in the factor holding latch 1. CP
Upon receiving an access error via the OR gate 2, U3 immediately terminates the cycle and then performs a read cycle to obtain a vector of the access error.

At this time, the normal memory select signal CS
1 is asserted and the memory is read. The CPU 3 reads the factor holding latch 1 in the exception handling routine and performs a conditional branch. If the next access error occurs between the time when the control is transferred to the exception processing and the time when the factor holding latch 1 is read, the contents of the factor holding latch 1 are rewritten,
You may make a mistake in your judgment.

Further, if a different exception is assigned to each cause of an access error in order to properly use a plurality of vectors, the priority is lowered and it cannot be accepted in the corresponding cycle, which is a problem.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a computer system having a plurality of factors that cause a particular highest exception (Exception). An object of the present invention is to realize an exception processing device of a computer system capable of reliably separating exception processing.

[0012]

Means for solving the above-mentioned problem is to provide a specific exception in an exception processing device of a computer system which reads out a corresponding vector from a table showing an address of an exception processing routine when an exception processing occurs. It is characterized by comprising a plurality of vector tables provided corresponding to a plurality of factors that occur, and an access means for obtaining a plurality of exception vectors by accessing different tables depending on the cause of an exception. is there.

[0013]

In the present invention, a plurality of vector tables are prepared corresponding to a plurality of factors that cause a specific exception, and a plurality of exception vectors are obtained by accessing different tables according to the factors of the exception. To do so.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram showing a first embodiment of the present invention. In this figure, 1 is a factor holding latch, 2 is an OR gate for passing factors A and B, 3 is a CPU,
Reference numeral 4 is a memory as a vector table, 5 is an address decoder for generating an address for accessing the memory 4, and 6 is a memory (register) as a second vector table provided corresponding to other factors.

When an access error occurs, the presence / absence of the factor B at that time is recorded in the factor holding latch 1. CP
Upon receiving an access error via the OR gate 2, U3 immediately terminates the cycle and then performs a read cycle to obtain a vector of the access error.

In the case of an access error due to factor A,
Latch 1 is not set, so select signal CS
1 is asserted and the vector is read from the memory as usual. When the factor holding latch 1 is set and the vector reading is performed, the select signal C in another space is selected.
S2 is asserted. Therefore, a different vector can be output for an access error due to factor B. When vector reading is performed by the select signal CS2, the factor holding latch 1 is cleared.

In the above case, since the exception processing is divided according to factors from the beginning, there is no erroneous judgment.
Further, as another embodiment, the same effect can be obtained by converting the address itself by several bits instead of asserting another select signal.

With the above configuration, it is possible to perform appropriate exception processing (re-execution / ignore, etc.) according to the type of access error. In other words, if there are multiple factors that cause a particular highest exception, different address spaces can be accessed depending on the factors and multiple exception vectors can be returned without changing the priority of the exception. ..

[0019]

As described in detail in connection with the above embodiments, a plurality of exception vectors are obtained by accessing different tables depending on the cause of the exception, so that the appropriate exception handling depending on the type of access error ( Re-execute / ignore) can be performed. Therefore, if there are multiple factors that cause a particular highest-level exception, different address spaces can be accessed depending on the factors, and multiple exception vectors can be returned without changing the priority of the exception. ..

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an overall configuration of a conventional exception handling device.

[Explanation of symbols]

 1 factor holding latch 2 or gate 3 CPU 4 memory 5 address decoder 6 memory (register)

Claims (1)

Claim: What is claimed is: 1. An exception handling device of a computer system, which reads a corresponding vector from a table showing an address of an exception handling routine when an exception handling occurs, responds to a plurality of factors causing a particular exception. An exception handling device for a computer system, comprising: a plurality of vector tables provided as described above; and access means for obtaining a plurality of exception vectors by accessing different tables depending on the cause of the exception.