JPH05276687A - Exciting current controller of generator for vehicle - Google Patents

Abstract

PURPOSE:To provide an exciting current controller of a generator for a vehicle in which a decrease in a rotating speed of an engine can be suppressed immediately after an electric load is applied while avoiding an increase in load of a battery as much as possible. CONSTITUTION:An exciting current controller 1 controls an exciting current of a generator 2 for a vehicle to be supplied to an electric load 5 and a battery 3. Particularly, exciting current change suppressing means Cr for the controller 1 sets an exciting current change rate of a first period to a relatively small value immediately after a time point when the load is varied, and sets the exciting current change rate of a second period after the first period to a value larger than that of the first period. Thus, an insufficient load current of the first period is supplied from the battery to suppress an abrupt increase in the exciting current of the first period, to prevent an abrupt decrease in the speed of an engine in the first period and to thereafter avoid excess consumption of the battery due to an increase in an exciting current increasing ratio in the second period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exciting current control device for a vehicle generator, and more particularly to a device for gradually changing the exciting current corresponding to a change in electric load.

[0002]

2. Description of the Related Art In a conventional vehicular generator, the amount of generated current is insufficient immediately after a switch is turned on to supply electric power to an electric load. Therefore, electric power is supplied from a battery and the terminal voltage of the battery decreases due to discharge of the battery. Detect
The exciting current of the generator is increased until the terminal voltage reaches a predetermined reference level, thereby increasing the output current of the generator and feeding the electric load. However, according to the above-described power generation control method, there is a problem that the engine speed drops sharply due to a rapid increase in the engine load immediately after the electric load is turned on. Hereinafter, this problem will be described in more detail. When an electric load is turned on at a specified accelerator opening, the terminal voltage of the battery drops due to the power supply to it, the exciting current increases sharply, the engine load increases sharply, and the engine speed drops sharply. The engine speed drops below the equilibrium point (usually called undershoot).

In order to solve such a problem, Japanese Unexamined Patent Publication No.
2-64299 is when the electric load is newly turned on,
Regardless of the amount of decrease in the battery terminal voltage, the constant increase in the duty ratio of the exciting current is used to avoid a sharp drop in the engine speed due to a sharp increase in the exciting current.

[0004]

However, even in the technique of the above-mentioned publication in which the duty ratio of the generator is uniformly increased, as shown in FIG. 9, the impact on the engine is still large immediately after the electric load is applied, and the engine speed is increased. Depression and undershoot occur. Of course, if the above-mentioned constant rate of increase is set to be extremely small, the engine speed will not drop sharply and undershoot will not occur.
However, such suppression of the increase rate takes a long time until the generator completely supplies power to the electric load, and the amount of energy taken out from the battery during that time becomes large, which causes an increase in load on the battery. ..

Further, according to the above-mentioned respective prior arts, there is a problem that the engine rotational speed pulsates in synchronization with an intermittent load, which gives an occupant an unpleasant feeling. In consideration of the decrease and fluctuation of the engine rotational speed. There is also a problem in that the idle speed is set, which is disadvantageous in terms of fuel consumption. The present invention has been made in view of the above problems, and it is an object of the present invention to provide an exciting current control device for a vehicle generator capable of suppressing a decrease in engine speed immediately after an electric load is applied while avoiding an increase in battery load as much as possible. , Its purpose is.

[0006]

An exciting current control device for a vehicle generator according to the present invention makes an output of a vehicle generator that feeds an electric load and a battery correspond to a change in the electric load and at the time of the change. The exciting current of the generator is controlled so as to gradually change from the exciting current value corresponding to the value of the electric load immediately before to the exciting current value corresponding to the value of the electric load after the changing time, from the changing time. In the exciting current control device for the vehicle generator, an exciting current change suppressing unit that sets the exciting current change rate in the first period immediately after the fluctuation point to be smaller than the exciting current change rate in the second period after the first period. It is characterized by having.

[0007]

The exciting current control device controls the exciting current of the vehicular generator that supplies power to the electric load and the battery so that the output current of the generator corresponds to the fluctuation of the electric load. Further, the exciting current change suppressing means of the exciting current control device gradually changes from the changing time from the exciting current value according to the electric load value immediately before the changing time to the exciting current value according to the electric load value after the changing time. Let

Further, the exciting current change suppressing means of this exciting current control device sets the exciting current change rate in the first period immediately after the time point of the electrical load change to a relatively small value, and the exciting current change rate in the second period after the first period is set. The current change rate is set to be larger than that in the first period. In this way, the insufficient load current in the first period is fed from the battery to suppress a rapid increase in the exciting current in the first period, prevent a sharp decrease in the engine speed in the first period, and in the subsequent second period. Excessive consumption of the battery can be avoided by increasing the rate of increase of the exciting current.

[0009]

As described above, in the exciting current control device for a vehicle generator of the present invention, the exciting current change rate in the first period immediately after the change of the electric load is set to the exciting current in the second period after the first period. Since the exciting current change suppressing unit that is set to be smaller than the change rate is provided, the following effects can be obtained.

First, since the increase of the exciting current in the first period immediately after the change of the electric load is small, the drop of the engine speed and the undershoot thereof can be made small. Next, the exciting current increase rate is increased in the second period after the first period, but the engine speed is reduced to some extent in the early part of the second period, so that the engine speed thereafter decreases. Is small, and its undershoot (excessive decrease in rotation speed due to engine inertia) can be further suppressed. Further, the increase of the exciting current increase rate in the second period reduces the burden on the battery.

Further, according to the present invention, since the responsiveness to changes in the electric load is suppressed, the change in the exciting current becomes small with respect to the frequent and periodic changes due to the intermittent electric load, and the change in the intermittent electric load is accordingly reduced. The pulsation of the engine speed can be suppressed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an exciting current control device for a vehicle generator according to the present invention will be described below with reference to FIG. The generator 2 is a three-phase AC generator with a built-in three-phase full-wave rectifier driven by a vehicle engine (not shown), the low-order output end of which is grounded, and the high-order output end is connected to the + terminal of the battery 3. In addition, the electric load 5 can be supplied with electricity by the conduction of the electric load switch 6. An excitation current control device 1 is attached to the generator 2, and the excitation current control device 1 has an input end for detecting the terminal voltage of the battery 3 and an output end connected to one end of the excitation winding 20 of the generator 2. And the other end of the excitation winding 20 is connected to the high-level output end of the generator 2. Further, the excitation current control device 1 has a built-in power supply circuit 19 which is supplied with power from the battery 3 through the switch 4, and the power supply circuit 19 supplies predetermined power supply voltage to each part through a power supply line (not shown).

The structure of the exciting current controller 1 will be described below. The voltage divider Vs appearing at the connection node of the voltage dividing resistors R1 and R2 connected in series between the input terminal of the exciting current control device 1 and the ground line is compared with the reference voltage Vr by the comparator 10, and the comparator 10 Is output to the AND circuit 12. The AND circuit 12 supplies the logical product output of the output of the comparator 10 and the output of the exciting current suppressing circuit section described later to the base of the power transistor 11 whose emitter is grounded, and the collector of the power transistor 11 is the output of the exciting current controller 1. The excitation current supplied to the excitation winding 20 through the end is interrupted.
Here, when the output from the exciting current suppressing circuit section to the AND circuit 12 is at high level (1), the power transistor 11 is controlled to be opened / closed by the comparator 10 as usual, and the divided voltage Vs is the reference voltage Vr. The duty ratio of the power transistor 11 (hereinafter, also simply referred to as duty) is determined so as to be equal to.

Next, the exciting current suppressing circuit section (exciting current change suppressing means in the present invention) Cr will be described. The exciting current suppressing circuit section Cr is composed of a duty storage circuit 13, a duty addition latch circuit 14, a pulse width generation circuit 15, a latch cycle switching circuit 16, a determination circuit 17, and a reference clock circuit 18.

The reference clock circuit 18 includes a duty storage circuit 13, a pulse width generation circuit 15, and a latch cycle switching circuit 1.
6. Input a clock signal having a predetermined period to the determination circuit 17. The duty storage circuit 13 has a function of inputting and storing the duty of the power transistor 11 by detecting the output of the AND circuit 12. Judgment circuit 17
Is a circuit that compares the output of the comparator 10 with the output of the pulse width generation circuit 15 to make a determination.

The latch cycle switching circuit 16 includes a determination circuit 17
Is a circuit that controls the timing of changing the duty of the clock signal for connecting and disconnecting the power transistor 11 based on the output from the. Duty addition latch circuit 14
Latches the duty stored in the duty storage circuit 13 at a predetermined timing, adds a predetermined amount of duty to the latched duty at the latch timing (duty switching timing) instructed by the latch cycle switching circuit 16, and Is a circuit for latching.

The pulse width generation circuit 15 is a circuit for outputting to the AND circuit 12 a pulse signal having an ON time corresponding to the duty (latch duty) latched by the duty addition latch circuit 14 based on the output of the duty addition latch circuit 14. The overall operation will be further described below. Immediately before the electric load 5 is turned on while the generator 2 is normally operating, the pulse width generation circuit 15 outputs the added duty waveform to the AND circuit 12 and calculates the logical product with the output of the comparator 10. As a result, the power transistor 11 is substantially intermittently controlled by the comparator 10. The duty of the AND circuit 12 generated due to the intermittent operation of the comparator 10 is periodically input to and stored in the duty storage circuit 13.

The judgment circuit 17 detects the intermittent low level (0) of the output of the comparator 10 using the output of the pulse width generation circuit 15 as a timing signal during normal operation, and then the electric load 5 is turned on. Then, the output of the comparator 10 is constantly at the high level (1) because Vs is reduced, and the continuous high level (1) of the comparator 10 is detected by the same timing signal as in the normal operation to detect the electrical load. It is determined that 5 has been input, and the determination output is output to the latch cycle switching circuit 16.

The latch cycle switching circuit 16 includes a determination circuit 17
Based on the determination output of (1), a clock signal (latch cycle switching clock) designating a latch cycle described later is output during the continuous high level (1) of the comparator 10 after the electric load is applied. The duty stored in the duty storage circuit 13 is latched in the duty addition latch circuit 14 at a predetermined latch timing. The duty addition latch circuit 14 adds a predetermined duty addition amount α to the latched duty to form an added duty and outputs it to the pulse width generation circuit 15, and the pulse width generation circuit 15 outputs the added duty that has been input. The high level (1) is output to the AND circuit 12 for a corresponding period, and the power transistor 11 is turned on. Immediately before the electric load is applied, the pulse width generation circuit 15 outputs the added duty waveform to the AND circuit 12, and as a result of taking the logical product with the output of the comparator 10, the power transistor 11 is substantially It is intermittently controlled by the comparator 10.

In this embodiment, the determination circuit 17 determines a time point after a predetermined period TD (see FIG. 3) from the time point when the electric load is turned on, and the latch cycle switching circuit 16 cuts off the output of the latch cycle switching clock in this period TD. After that, the latch cycle switching clock is output. This latch cycle switching clock is sent to the duty addition latch circuit 14, and the duty addition latch circuit 14 performs latching and addition of the duty addition amount α at the timing of this latch cycle switching clock. Therefore, the duty increase due to the addition of the duty addition amount α in the duty addition latch circuit 14 is prohibited in the period TD. As a result, during the predetermined period TD after the electric load is applied, the duty is maintained substantially in the state immediately before the electric load is applied, the duty of the exciting current becomes constant, and the engine load becomes constant.

After the period TD, the latch cycle switching circuit 16
Outputs the latch cycle switching clock to the duty addition latch circuit 14, and the duty addition latch circuit 14 latches in synchronization with this clock and adds the duty addition amount α to the latched duty. The duty increased by the duty addition amount α in synchronization with the latch cycle switching clock is output to the pulse width generation circuit 15, and the pulse width generation circuit 15 ANDs the pulse signal of the predetermined cycle having the input duty.
It is output to the circuit 12, and the power transistor 11 is intermittently connected at this duty.

The details of each section will be described below. First, the reference clock circuit 18, the determination circuit 17, and the latch cycle switching circuit 16 will be described in detail with reference to FIG. In FIG. 2, reference numeral 18 denotes a reference clock circuit, which includes a reference oscillator 182 that oscillates at a predetermined frequency, and a predetermined number of cascade-connected counters 183 that outputs a clock 181 formed by dividing a clock output from the reference oscillator 182. Consists of. Further, the reference clock circuit 18 has a built-in AND circuit 184 which outputs a logical product output 185 of the outputs of the counter 183 of a predetermined digit.

In the determination circuit 17, the output of the comparator 10 is input as the input 171, the output of the pulse width generation circuit 15 is input as the input 172, the clock 181 is input as the input 173, and the output 174 is the latch cycle switching circuit. It becomes 16 inputs 161. 175 is an input terminal 171,
A D flip-flop that receives a signal from 172,
176 is a counter, 1771 and 1772 are AND circuits,
Reference numeral 178 is an OR circuit, and 179 is a NOT circuit.

The operation of each part of the determination circuit 17 before and after the application of the electric load 5 will be described with reference to the timing chart of FIG. When the electric load 5 is turned on from the normal control state,
The output of the comparator 10 is always high level (1), and the input terminal 17
1 is always at the high level (1), and the state of the output end of the pulse width generation circuit 15 immediately after that is the NOT circuit 179.
Therefore, the Q output of the D flip-flop 175 becomes high level (1) at the time when it becomes high level (1) (falling edge of CK of 175).

This Q output is input to the AND circuit 1771. Since the Q output of the AND circuit 1771 as a gate is high level (1) and the output of the NOT circuit 179 is high level (1), the clock ( The latch cycle switching clock) 181 is output to the CK input terminal of the lower digit counter 176 through the AND circuit 1771, and the two digit counter 176 counts the clock 181 by 2 bits. If the outputs of both counters 176 are (11), AN
The D circuit 1772 outputs a high level (1) to the output 174 through the OR circuit 178. Also, both counters 176
Output becomes (11), the high level (1) of the AND circuit 1772 becomes a low level (0) in the NOT circuit 179, and the AND circuit 1771 outputs a low level (0) to the counter 176 and stops it. Let On the other hand, the anti-Q output of the D flip-flop 175 is output 174 through the OR circuit 178 at the same time as the reset signal of the counter 176.
It is said that. Therefore, the output 174 of the determination circuit 17 has the waveform shown in FIG. 3, and hereinafter, the period when the output 174 is at the low level (0) is referred to as the period in the Fduty fixed control state (region (II) in FIG. 3), and thereafter. Output of 17
The period of high level (1) of 4 is called the period of the gradual excitation control state (region (III) in FIG. 3), and the period before the output 174 becomes low level (0) is the period of the normal control state (Fig. (Region (I) in 3)).

The latch cycle switching circuit 16 is the NOT circuit 1
64, an AND circuit 165, and an OR circuit 166. The input 161 and the clock 181 are input, and the output 16
3 is output. The latch cycle switching circuit 16 includes the determination circuit 1
The clock 181 is output as the output 163 only when the output 174 of 7 is at the high level (1). That is, F
In the fixed duty control state, the output 163 of the latch cycle switching circuit 16 is clamped to the high level (1).

In this embodiment, the same reference clock is input to the input terminal 173 of the determination circuit 17 and the input terminal 162 of the latch cycle switching circuit 16 to operate them in synchronization, but of course the input terminal 173 and the input terminal 173 are input. A reference clock having a different oscillation cycle may be input to the terminal 162. Next, one embodiment of the duty storage circuit 13, the duty addition latch circuit 14, and the pulse width generation circuit 15 will be described with reference to FIG.

In the duty storage circuit 13, input 1
31 is the output of the AND circuit 12, the input 132 is the output 186 of the reference clock circuit 18, the input 133 is the output 185 of the reference clock circuit 18, and the output 134 of the duty storage circuit 13 is the number of bits (resolution). ), The number of output lines is determined, for example, 5 bits (resolution: 1/2
^In the case of ⁵ ), there are 5 outputs. An AND circuit 135 is a gate for counting the ON time of the power transistor 11, and uses the divided output 186 of the reference clock circuit 18 as the lowest level only during the period when the output of the AND circuit 12 is at high level (1). It sends it to the digit counter 136, and the counter 136 counts it. As a result, the ON time of the power transistor 11 is counted by the counter 136. Here, the number of counters is the output 134 described above.
As in the case of 5 bits, at least 5 stages are required. In the present embodiment, the circuit configuration that counts the ON time within one cycle is used. However, the sum of the ON times for two cycles or four cycles can be counted, and the average value thereof is calculated and output. You may. For example, one or two counters 136 may be added, the number of count bits may be increased by one or two bits, and the upper bits may be output. 137 is NA
This is an ND circuit, and when all the outputs 134 of each counter 136 become high level (1), the output of the AND circuit 135 is clamped to low level (0), and the counter 136 is
Stop the operation of.

The counter 136 is reset by inputting the output 185 of the reference clock circuit 18 to the R terminal as the reset input 133. The output 185 is the logical product of the outputs of the predetermined number of counters 183 so that one pulse is generated in each predetermined cycle (intermittent cycle of the power transistor 11). The predetermined period means AN of the reference clock circuit 18.
It is equal to the cycle of the output 185 of the D circuit 184, that is, the output cycle of the most significant digit counter 183 input to the AND circuit 184.

Next, the duty addition latch circuit 14 will be described. The duty addition latch circuit 14 includes a flip-flop 144 provided by the number of digits of the counter 136 of the duty storage circuit 13, and an addition circuit 145 that adds a predetermined value (duty addition amount α) to the output of the flip-flop 144. CK of each flip-flop 144
Terminal input (hereinafter referred to as latch pulse (LP) input)
141 is a clock 181 and each flip-flop 1
The D terminal input 142 of 44 is individually configured by each digit output of each counter 136 of the duty storage circuit 13. The output of the flip-flop 144 is added with the duty addition amount α by the adder circuit 145, and a predetermined number (the same number as the output number of the duty storage circuit 13) of outputs 143 are output as the added duty. The number of outputs 143 can be changed according to the binary digit number (bit number) of the added duty.

The operation of the duty addition latch circuit 14 will be described. Each flip-flop 144 has an LP input 1
Each data of the output 134 of the duty storage circuit 13 is latched bit by bit in a cycle of 41 (= clock 181).
The output of each flip-flop 144 holds the immediately preceding latch data while the LP input 141 is at high level (1). The adder circuit 145 adds the duty addition amount α to the data latched by each flip-flop 144, that is, the immediately preceding duty, and outputs it as the added duty 143.

An example of the adder circuit 145 will be described with reference to FIG. This adder circuit 145 has 3 bits (resolution 1/2).
³ = 0.125), and the added duty is output in which the duty from 0 to 100% is divided into eight stages. The inputs 1451 to 1453 of the adder circuit 145 are individually configured by the output 142 of the flip-flop 144, and the input 1453 is the most significant digit flip-flop 144.
Of the flip-flop 144 of the next digit is input to the input 1452, and the output of the flip-flop 144 of the next digit is input to the input 1451. The input 1451 is inverted by the NOT circuit 1451 and is output through the least significant digit OR circuit 1458 to the least significant digit output 14
31 and the input 1452 is the half adder 145 on the lower digit side.
5 is added to the input 1451 and the added value which is not carried is output to the intermediate digit output 1 through the OR circuit 1458 of the next digit.
432, and the input 1453 is the half adder 1 on the most significant digit side.
AND circuit 14 of half adder 1455 on the lower digit side at 455
The carry value from 57 is added, and the added value which is not carried is output through the most significant digit OR circuit 1458 as the most significant digit output 1433. The half adder 1455 includes an EXOR circuit 1456 and an AND circuit 1457, as is well known. Further, the AND circuit 1 of the half-sign adder 1455 of the most significant digit
When a carry is output from 457, each OR circuit 145
3-bit output 1431, 1432, 1433 through 8
(111), that is, 100% duty is output. In this way, 3-bit inputs 1451, 145
It is possible to add (001 = duty 12.5%) to 2,1453 as the duty addition amount α.

It should be noted that the most significant digit half adder 1455 AN
The D circuit 1457 becomes high level (1) (the carry signal is generated in the half-adder 1455 of the most significant digit) when the 3-bit inputs 1451, 1452, and 1453 of the adder circuit 145 (111 = duty 100%). In this case, that is, the output of the NOT circuit 1454 and the output of the EXOR circuit 1456 of each half adder 1455 become (000). At this time, the most significant digit half adder 1455 is used.
According to the carry value of, the output of the addition circuit 145 is set to (111) instead of (000).

In the present embodiment, the adder circuit 145 is configured to perform addition after latching, but naturally it may be configured to perform addition before latching (not shown). Further, if the counter 136 of the duty storage circuit 13 is configured to give the duty addition amount α as a preset value, the addition circuit 145 becomes unnecessary. Next, the pulse width generation circuit 15 will be described.

Inputs 151 and 152 thereof are composed of outputs 186 and 186 of the reference clock circuit 18, respectively.
Reference numeral 54 is an output 143 of the duty addition latch circuit 14, and 153 is an output of the pulse width generation circuit 15,
It is sent to the ND circuit 12 and the determination circuit 17. 155 is a preset counter, 156 is an AND circuit, 157
Is a NAND circuit and 158 is a NOT circuit. The counter 155 is individually provided for each bit, and the output 143 of the duty addition latch circuit 14, that is, the added duty is input to the preset terminal of the counter 155.
Is input as a preset value individually as
Reference numeral 55 designates an input 154 and an output 186 of the reference clock circuit 18.
At the timing, the count UP is started with the preset value as an initial value. The NAND circuit 157 has each counter 1
When all the outputs Q of 55 become high level (1), A
The output of the ND circuit 156 is clamped to "0" and the operation of the counter 155 is stopped. Therefore, counter 1
54 starts counting from the binary value corresponding to the preset added duty, and the NAND circuit 157 operates the NOT circuit 158 during this counting period.
Output a low level (0) to the AND circuit 12 through
The power transistor 11 is turned off. Then, if all the outputs Q of each counter 155 become high level (1),
Since counting stops and the outputs of the counter 155 are all clamped to 1, the NAND circuit 157 outputs a high level (1) to the AND circuit 12 through the NOT circuit 158, and the power transistor 11 is turned on. After that, when the AND circuit output 185 outputs a high level (1) from the reference clock circuit 18, the pulse width generation circuit 15
All counters 155 of are reset, all counters 136 of the duty storage circuit 13 are reset,
After that, the above operation is repeated at the cycle of the AND circuit output 185 until the amount of power generation (duty of the power transistor 11) according to the electric load is reached.

That is, the pulse width generation circuit 15 turns off the power transistor 11 from the time when the count value corresponding to the input added duty is preset in the counter 155, and the counter 155 starts counting from the preset value. The power transistor 11 is turned on when the count value of is maximum. Since the preset cycle (the cycle of the signal 185) is constant, the off period of the power transistor 11 is reduced (the duty is gradually increased).

Duties stored in the duty storage circuit 13
When the duty addition amount α is added to the tee to gradually increase the duty of the power transistor 11, the power generation amount of the generator 2 gradually increases, and when the potential of the battery 3 rises to a predetermined level, the comparator 10 Is inverted to cut off the power transistor 11 through the AND circuit 12, the low level (0) of the comparator 10 is input to the determination circuit 17, and the normal excitation current control is resumed. The gradual excitation control state is
The amount of power generated by the generator 2 continues until it reaches a considerable amount according to the electric load, and the duration is the latch period T _LP , the duty immediately before the electric load is applied is D ₁ %, and the final arrival duty is
If the tee is D ₂ % and the duty addition amount is α%, then T _LP
It is calculated as × (D ₂ −D ₁ ) / α.

According to this embodiment, the duty of the generator 2 is fixed for a predetermined period after the electric load 5 is turned on, and then the duty is gradually increased to a stable level. Therefore, for example, the electric load is turned on only for a short time. In the case of a high speed intermittent load, it is possible to reduce the influence of these electric loads on the engine and prevent them from temporarily lowering the engine speed or hunting. it can.

Further, it is possible to suppress the occurrence of undershoot even under continuous load. Furthermore, since it is possible to prevent the engine speed from temporarily lowering, it is possible to lower the idle speed and also improve fuel efficiency. In the above embodiment, the voltage control device 1 includes the comparator 10, the AND circuit 12,
Pulse width generation circuit 15, duty addition latch circuit 1
4, duty storage circuit 13, latch cycle switching circuit 1
Although the configuration including the circuit 6 and the determination circuit 17 is described above, it is a matter of course that some or all of the circuits and the comparator can be provided outside the voltage control device 1.

A modification will be described with reference to FIG. In this mode, at least one counter 183 is added to the reference clock circuit 18 and an output 188 having an oscillation cycle longer than the output 181 is taken out. In addition, A is provided between the NOT circuit 164 and the OR circuit 166 of the latch cycle switching circuit 16.
The ND circuit 165 is added, and the AND circuit 165 is NO.
The logical product of the output of the T circuit 164 and the output 188 is obtained.

The operation of the above circuit will be described below.
7 only when the output 174 is at the low level (0), that is, in the Fduty fixed control state shown in FIG. 3, the latch cycle switching circuit 16 sets the longest cycle 188 as the latch cycle, that is, the duty switching cycle. Output to. Therefore, as shown in FIG. 7, the duty increase rate is reduced in the period TD of the Fduty fixed control state, whereby the reduction of the engine speed in this period can be suppressed, whereby the rapid reduction of the engine speed in this period is achieved. It is possible to prevent a subsequent undershoot resulting from such factors as a decrease in engine speed.

In the above embodiment, the ON duty increase amount + α is constant, but as shown in FIG. 8, the duty increase amount + α is changed to + β, or the latch period is changed from TLPα to TLPβ. You may let me do it. Also, the ON duty (duty) increase amount + α
Can be increased by giving a preset value to the duty storage circuit 13.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of an exciting current control device of the present invention,

FIG. 2 is a circuit diagram showing a part of the exciting current suppressing circuit section of FIG.

3 is a signal waveform diagram of each part of the circuit of FIG.

FIG. 4 is a circuit diagram showing the remaining part of the exciting current suppressing circuit unit of FIG.

5 is a circuit diagram showing an example of an adder circuit of the exciting current suppressing circuit unit of FIG. 4;

6 is a circuit diagram showing another mode of the exciting current suppressing circuit section of FIG.

7 is a timing chart showing the relationship between the duty of the power transistor, the electric load state, and the engine speed in the mode of FIG.

FIG. 8 is a timing chart showing another mode of gradually increasing the duty.

FIG. 9 is a timing chart showing a relationship between duty of a power transistor, an electric load state, and an engine speed according to a conventional technique;

[Explanation of symbols]

1 is an exciting current control device, 2 is a vehicle generator, 3 is a battery, 5 is an electric load, and Cr is an exciting current suppressing circuit section (exciting current change suppressing means).

Claims (1)

[Claims] 1. An output of a vehicular generator that supplies power to an electric load and a battery is made to correspond to a change in the electric load, and from an exciting current value corresponding to a value of the electric load immediately before the change time, to a time after the change time. In order to gradually change the exciting current value according to the value of the electric load from the time of fluctuation,
In the excitation current control device for a vehicle generator that controls the excitation current of the generator, the exciting current change rate of the first period immediately after the change time is more than the exciting current change rate of the second period after the first period. An exciting current control device for a vehicle generator, characterized by comprising exciting current change suppressing means set to a small value.