JPH05274253A - System bus controller - Google Patents

Abstract

(57) [Abstract] [Purpose] CP for write access to DRAM
The wait time of U is reduced and the processing capability of CPU is improved. [Structure] During write access to the DRAM 12, the write data (CPU-DATA) output from the CPU 11 on the system bus S-BUS is held in the latch A 112 in the third clock cycle under the control of the bus controller 111. It The parity generation circuit 14
Since parity data is generated based on the held data (Lathed-DATA), the CPU 11 writes the next data to the system bus S-BUS when the write data output by itself is latched by the latch A 112. Enables output of embedded data (during burst mode) or execution of the next instruction (during normal write).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system bus control circuit for controlling write access performed by a CPU to a DRAM (dynamic random access memory) connected via a system bus.

[0002]

2. Description of the Related Art Generally, in a computer, a main memory is a ROM (Read Only Memory) or a RAM.
A semiconductor memory such as (random access memory) is used. Recently, with the increase in capacity of DRAM, a RAM disk having a plurality of DRAM chips mounted on a board has been used as an auxiliary memory.

Here, in FIG. 6, a CPU (Central Processing Unit) 11 has a DRAM 1 via a system bus S-BUS.
2 shows a circuit block diagram of the system connected to FIG. Generally, when the DRAM 12 has a large capacity and high reliability is required for holding data or is used under bad conditions, a function of detecting an error in data stored in the DRAM 12 is required.

As a method of detecting an error in this stored data, a para-ity check is generally used. In this parity check, the number of bits of "1" included in binary data is even (eve
A data error is detected by detecting whether it is n; even) or odd (odd), and a 1-bit parity bit is added to the n-bit storage data when writing data to the DRAM. Then, the number of bits that are "1" in the (n + 1) -bit data is always even (even parity) or odd (odd parity).
Write +1) bit data to DRAM. And
When the data is read from the DRAM, the (n + 1) -bit data to which the above-mentioned 1-bit parity bit is added is read, and n is read depending on whether the number of "1" bits in the read data is even or odd. It is intended to detect an error in bit storage data.

In the system shown in FIG. 6, the DRAM
A parity generation circuit (hereinafter abbreviated as P-GEN) 14 is provided between the CPU 11 and the DRAM 12 in order to perform the parity check on the data read from the data 12.

By the way, the DRAM 12 by the CPU 11
Write access to the normal write (Norm
al Write) and Burst Write. Normal write is a mode to write data one by one to the DRAM 12 at random, and burst write is C
In this mode, the PU 11 occupies the system bus S-BUS for a certain period of time and continuously writes a plurality of (for example, four) data to the DRAM 12.

[0007] Next, the operation of each mode of the normal write and the burst write which has been conventionally performed is shown in FIG.
Also, description will be made with reference to the timing chart of FIG. The CPU 11 operates in synchronization with the system clock shown in FIG.

When a normal write is performed on the DRAM 12, the CPU 11 outputs a write cycle start signal bar cyclen output to the DRC 15 which controls data write / data read for the DRAM 12 in the latter half of the first clock cycle C1. -Star is asserted (enabled)
(Refer to the same figure (b)).

Next, in the next clock cycle C2, the CPU 11 outputs D on the data bus of the system bus S-BUS.
Write data CPU-DATA for RAM 12 is output. (Refer to the same figure (C)).

The P-GEN 14 is a system bus S-BU.
When the write data CPU-DATA is output to the S data bus and is determined, the parity data (PARITY-DATA) PD for the write data CPU-DAT is supplied to the clock cycle C3 from the latter half of the clock cycle C2 to the next clock cycle C3.
It is generated by taking the time t _p until the first half of the above, and is output to the DRAM 12 (see (d) in the same figure).

The DRC 15 detects the start of the write cycle of the CPU 11 by detecting the assertion of the write cycle start signal Cycle-Star input from the CPU 11, and the parity data PD output from the P-GEN 14 to the DRAM 12 is detected. Column address strobe signal bar C at the start of the fourth clock cycle C4
AS is asserted (hereinafter abbreviated as CAS for convenience) (see (e) in the figure). The time for which the column address / strobe signal bar CAS is determined is DRC15.
Changes due to variations in the output characteristics of the above, and is delayed by a maximum of time td.

Next, after the delay time t _{d of the} bar CAS has elapsed, the DRC 15 asserts a write cycle end signal bar cycle-end to be output to the CPU 11 (see (f) in the same figure).

The CPU 11 is the system bus S-BU.
Write data CPU-DATA output on S to DRC
The delay time td output from the CAS 15 and the subsequent data hold time th of the write data CPU-DATA of the DRAM 12 continue to hold and wait ((c), (d), (d) in the figure). See e)).

Then, the CPU 11 inputs the write cycle end signal barbar cycle-en input from the DRC 15.
The end of the write cycle is detected by detecting the assertion of d (see (f) in the figure).

As described above, the DRAM of the conventional CPU 11
A normal light for 12 is the system clock (system clock
-Clock) 4 clock cycles C1 to C4. Next, a burst write operation of the conventional CPU 11 with respect to the DRAM 12 will be described with reference to the timing chart of FIG.

The CPU 11 starts with the first data (1st
Writing of (CPU-DATA) is performed in clock cycles C1 to C4 in the same manner as the normal writing described above. Then, the subsequent second data (2nd CPU-DATA),
The writing of the third data (3rd CPU-DATA) and the fourth data (4th CPU-DATA) is performed by clock cycles C2 to C4 in the writing of the first data (1st CPU-DATA).

Therefore, the DRAM of the conventional CPU 11
Burst write of 4 word data to 12
13 clock cycles were required. FIG. 9 shows operations of the CPU 11, the P-GEN 14, and the DRC 15 in each of the clock cycles C1 to C4 in the above-described data writing to the DRAM 12 of the CPU 11.

[0018]

As described above, conventionally, the CPU 11 performs the DR via the system bus S-BUS.
When writing data to AM12, CPU11
Had to wait while continuously outputting the write data to the data bus of the system bus S-BUS for 4 clock cycles in the normal write and 13 clock cycles in the burst write.

The CPU 11 frequently performs write access to the work area on the main memory during data processing. Therefore, the length of the data writing time to the DRAM 12, which is the main memory, has a great influence on the processing capacity of the CPU 11, and thus the processing capacity of the entire system.

Therefore, in order to increase the processing capacity of the CPU, it is necessary to reduce the wait time of the CPU 11 when writing (writing access) data to the DRAM used for the main memory or the like.

By the way, as described above, the CPU is a DRAM
The reason for increasing the wait time of the CPU when performing write access is to the fact that the CPU must continue to output write data on the data bus of the system bus until parity data is generated. is doing.

Therefore, even if the CPU does not continuously output the write data onto the data bus of the system bus until the parity data is generated, the write data and the parity data can be correctly written in the DRAM. For example, CPU
It is considered that the wait time at the time of writing data to the DRAM can be shortened, and the processing capacity of the CPU can be improved and the processing capacity of the entire system can be improved.

An object of the present invention is to enable the write data and its parity data to be correctly written in the DRAM without the CPU continuing to output the write data on the data bus of the system bus until the parity data is generated. It is to be.

[0024]

The means of the present invention are as follows. The first latch means 1 (see the block diagram of FIG. 1, the same applies hereinafter) latches write data output by the CPU on the system bus. Parity data generation means 2
Creates parity data of the write data latched by the first latch means 1. The second latch means 3 is
The write data latched by the first latch means 1 and the parity data generated by the parity data generating means 2 are latched, and the latched data are DRA.
It is output to M as write data. The control means 4 is a CPU
The write operation is started in response to a write cycle start instruction from the CPU, and when the write data output from the CPU on the system bus is confirmed, the first latch means 1 is caused to latch the write data and The writing output from the first latch means 1 to the second latch means 3 at the time when the parity data generating means 2 generates the parity data of the write data by notifying the CPU of the end of the data writing. The data and the parity data of the write data output from the parity data generating means 2 are latched. This control means 4 is provided with the DRA, for example.
When the data write to M is performed by burst write, in the data write of the second time and thereafter, the D
After receiving the notification of the end of the data writing to the DRAM from the DRAM control means that controls the writing to the RAM, the CRU is notified of the end of the data writing, and the first and second The latch timing of the latch means 1 and 3 is determined.

[0025]

The operation of the means of the present invention is as follows. CP
When writing data in the DRAM, U first notifies the control means 4 of the start of the write cycle. And then,
The CPU outputs data (write data) to be written in the DRAM to the system bus. When this write data is confirmed on the system bus, the control means 4 causes the first latch means 1 to latch the write data. By this,
The first latch means 1 outputs the write data to the parity data generating means 2 and the second latch means 3. Then, the control means 4 immediately notifies the CPU of the end of data writing. Thus, when the write data output from the CPU on the system bus is confirmed on the system bus, it is immediately latched by the first latch means 2. Therefore, in the case of a normal write for writing 1-word data, the CPU
The write cycle can be terminated and the next instruction can be executed before the write data is written to the DRAM along with its parity data. Then, while the CPU is executing the next instruction, the parity data generation means 2 generates the parity data of the write data, and the second latch means 3 is generated.
Output to. Then, as described above, the parity data is the second
Output to the second latch means 3, the control means 4 outputs to the second latch means 3 the write data of the CPU output from the first latch means 1 and the parity data generating means 2. The parity data of the write data is latched and those data are output to the DRAM. Subsequently, the DRAM control means controls writing to the DRAM, and the write data and the parity data are D
It is written to the address in RAM. And DRA
The M control means immediately notifies the control means 4 of the completion of the data writing to the DRAM after the completion of the writing. As described above, the normal write to the DRAM of the CPU is completed. In the burst write, after the first write data of the CPU is latched by the first latch means 1 as described above, the control means 4 immediately sends CP.
Notify U of the end of data writing. In response to this, the CPU outputs the second write data to the system bus. During this period, the parity data generation means 2 generates the parity data of the first write data. That is, the output of the second write data to the system bus of the CPU and the generation of the parity data of the first write data by the parity data generating means 2 are performed in parallel. Then, as described above, the first write data is written in the DRAM,
When the control means notifies the control means 4 of the end of the data writing to the DRAM, the control means 4 causes the first latch means 1 to latch the second write data and the CPU
Is notified of the end of data writing to the DRAM. As a result, the CPU outputs the third write data to the system bus. Then, thereafter, the same processing as the above-mentioned first write data is performed on the above-mentioned second write data by the parity data generating means 2, the control means 3, the second latch means, and the DRAM control means. Then, the second write data is written in the DRAM. After the data writing is completed, the DRAM control unit causes the control unit 4 to perform the DRA.
Notify the end of data writing to M. Thereafter, similarly, the CPU outputs the third, fourth and fourth signals to the system bus.
.. is written in the DRAM. In this way, in the case of burst write, the second and subsequent DRs
In writing data to the AM, the output of the nth write data to the system bus by the CPU and the generation of the parity data of the (n-1) th write data by the parity generation means 2 are performed in parallel. It happens almost at the same time.
Therefore, even if the CPU does not continue to output the write data on the data bus of the system bus until the parity data is generated, the write data and the parity data can be correctly written in the DRAM.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described below with reference to FIGS. FIG. 2 is a circuit block diagram of a system in which the CPU 11 and the DRAM 12 are connected via the system bus control circuit 100.

In the figure, the same blocks as those shown in FIG. 6 are designated by the same reference numerals. As shown in the figure, a system bus control circuit 100 with a parity generation function is provided between the CPU 11 and the DRAM 12.

The system bus control circuit 100 includes a bus controller 11 and a latch A (L).
ATCH-A) 112, Latch B (LATCH-B) 1
13, and the P-GEN (parity generation circuit) 114
Made of.

The bus controller 111 is the CPU 11
Normal write and burst to DRAM 12 by
The write cycle start signal bar cycle_start is input from the CPU 11 for controlling the write.
Is detected, control of the write cycle is started, and latch A1
12, the latch A enable signal bar Latch A for causing the CPU 11 to latch the write data CPU-DATA output on the data bus of the system bus S-BUS.
_Enable and outputs the write data and P output from the latch A112 to the latch B113.
Output a latch B enable signal bar Latch B_enable for latching the parity data of the write data output from the GEN14. Further, the CPU 11 asserts the CPU cycle end signal bar CPU_cycle_end each time one data transfer is completed, and notifies the CPU 11 that the next write data can be output.

Latch A112 is the bus controller 1
Latch A enable signal bar Latch A_ added from 11
When enable is asserted, the CPU 11 latches the write data (CPU-DATA) output on the data bus of the system bus S-BUS and outputs it to the latch B113.

The P-GEN 14 generates parity data (PARITY-DATA) of the write data (Latched-DATA) output from the latch A 112 and outputs it to the latch B 113.

The latch B113 is the bus controller 1
Latch B enable signal bar Latch B_ added from 11
When enable is asserted, the write data (Latched-DATA) output from the latch A112 and P-
The parity data (PARITY-DATA) of the write data output from the GEN 14 is latched and the latched data is output to the DRAM 12.

Next, a DRC (DRAM Controller) 2
Reference numeral 15 asserts the column address / strobe signal bar CAS which is output to the DRAM 12 at a predetermined timing every time the data (RAM-DATA) stored in the latch B 113 is written to the DRAM 12, and the above data (RAM-DATA ) Is written to the address of the DRAM 12. Next, in the system having the above configuration, D
The operations of normal write and burst write to the RAM 12 will be described.

FIG. 3 is a timing chart for explaining the operation when the CPU 11 normally writes to the DRAM 12. The clock shown in FIG. 9A is a system clock.

In the case of normal light, the CPU 11 first
In the latter half of the first clock cycle C1, the write cycle start signal bar cycle_star is asserted and output to the bus controller 111 and the DRC 215 (see FIG. 7B).

Next, the CPU 11 outputs the write data (CPU-DATA) on the data bus of the system bus S-BUS in the latter half of the next clock cycle C2 (see FIG. 7C). This write data (CPU-DATA)
Is connected to the P-GE via the latch A112 in the through state.
It is output to N14 and the latch B113 (see (f) in the figure).

When the write data (CPU-DATA) is determined on the data bus of the system bus S-BUS, the bus controller 111 asserts the CPU cycle / end signal bar CPU_cycle_end to CP.
It is added to U11 (see (d) in the figure).

Subsequently, the bus controller 111 asserts the latch A enable signal bar Latch A_enable at the start of the next clock cycle C3 (corresponding to the clock cycle C1 in the case of normal write) to latch L1.
12 (see (e) in the figure).

As a result, the latch A112 becomes the CPU
The write data (CPU-DATA) output from 11 is latched (held) and added to the P-GEN 111 and the latch B 113 (see (f) in the figure).

The P-GEN 11 has a clock cycle C3.
CPU11 output from the latch A112 in
Write parity data (PARITY-DATA) of the write data (Latched-DATA) and output the parity data (PARITY-DATA) to the latch B113 (see (g) in the figure).

Subsequently, the bus controller 111 asserts the latch B enable signal bar Latch B_enable at the start of the next clock cycle C4 to latch L113.
Is output (see (h) of the same figure).

As a result, the latch B113 causes the write data (La of the CPU 11) output from the latch A112.
tched-DATA) and its write data (Latched-DATA)
Data) parity data (PARITY-DATA) is held, and these data are written data (RAM DAT).
It is output to the DRAM 12 as A) (see (i) in the figure).

Further, the DRC 215 receives the column address strobe signal bar CA at the start of the clock cycle C4.
The S is output to the DRAM 12. Also, the DRC 215
After the output of the signal bar CAS, the RAM write cycle end signal bar RAM_c indicating that the normal write has ended
Cycle_end is output to the bus controller 111 (see (k) in the figure).

As described above, the write data (CPU-DATA) output from the CPU 111 on the data bus of the system bus S-BUS in the clock cycle C2 is immediately latched by the latch A112 under the control of the bus controller 111, After that, the P-GEN 114 has its latch A1.
Since parity data is created based on the data (Latched-DATA) latched by 12, the CPU 11 can immediately execute the next instruction after the end of the second clock cycle C2.

That is, the normal write seen from the CPU 11 side is completed in two clock cycles of C1 and C2 (conventionally, as described above, C1 to C4 are used.
Clock cycle).

Next, the burst write operation of the CPU 11 will be described with reference to FIGS. In the case of burst write, the CPU 11 first sets the bus controllers 111 and D in the latter half of the first clock cycle C1.
In order to notify the RC 215 of the start of burst write, the write cycle start signal bar cycle_star
Assert t to assert bus controller 111 and DRC
215 (see FIG. 4B).

Subsequently, the CPU 11 writes the first write data (1st) to the DRAM 12 on the data bus of the system bus S-BUS in the latter half of the next clock cycle C2.
CPU-DATA) is output (see (c) in the figure).

Subsequently, the CPU 11 causes the write data 1 to be written.
When stDATA is confirmed on the data bus,
The controller 111 displays the CPU cycle end signal bar CP
The change of U_cycle_end to assert is detected at the start of the next clock cycle C3, and the second write data (2nd CP) is detected in the latter half of the next clock cycle C4.
U-DATA) is output to the data bus of the system bus S-BUS.

Further, at the start of the clock cycle C3, the bus controller 111 asserts the latch A enable signal bar Latch A_enable to set the latch A1.
The first write data (1st C
PU-DATA) Latch (hold) ((e) in the figure,
(See (f)).

The P-GEN 14 causes the latch A 112 to write the first write data (1st-CPU) as described above.
-DATA) is latched, the first write data (1st CPU-DATA) is input from the latch A 112 and the parity data (1st PARITY-DATA) of the write data (1st CPU-DATA) is input. 3 within clock cycle C3, latch B11
3 (see (g) of the same figure).

Next, the bus controller 111 asserts the latch B enable signal bar Latch B-enable to start latch B at the start of the next fourth clock cycle C4.
113 (see (h) in the figure).

As a result, the latch B113 latches (holds) the first write data (1st CPU-DATA) and its parity data (1st PARITY-DATA) and outputs it to the DRAM 12 ((i) in the figure). reference). Therefore, at this point, the DRAM 12
Is the first write data 1st DATA and its parity data (1st PARITY DATA).
Of the first write data (1st R
It is output as AM-DATA).

When the first write data (RAM-DATA) is determined, the DRC 215 outputs the column address / strobe signal bar CAS to the DRAM 12, and the first write data (1st RAM-DATA) is DRA.
The data is written in M (see (j) in the same figure).

Subsequently, the DRC 215 asserts the RAM cycle end signal bar RAM_cycle_end and outputs it to the bus controller 111 ((k) in the figure).
reference).

As described above, the clock cycles C1 to C1.
At C4, the first write data (1stRAM-DATA) is written to the address of the DRAM 12. By the way, as described above, the CPU 11 adds the CP from the bus controller 111 at the start of the clock cycle C3.
The first assertion of the U cycle end signal CPU_cycle_end is detected, and the second write data (2nd CPU-DATA) is output to the data bus of the system bus S-BUS in the latter half of the clock cycle C3 (see FIG. )reference).

In the bus controller 111, as described above, the DRC 215 outputs the RAM cycle end signal bar RAM-cycle-en at the fourth clock cycle C4.
When it detects that d has been asserted, it asserts the CPU cycle end signal bar CPU-cycle-end and outputs C
It is added to PU11 (see (k) and (d) in the same figure).

As a result, the CPU 11 causes the third write data (3rd) in the latter half of the next clock cycle C5.
CPU-DATA) on the data bus of the system bus S-BUS.

The bus controller 111 has a fourth
Clock cycle / end signal bar RAM_cycle
Upon detection of assertion of e_end, at the start of the next fifth clock cycle C5, the latch A enable signal L
Asch_enable is assorted and latch A112
(See (e) of the same figure).

As a result, the latch A112 causes the second write data (2nd CPU-DATA) output by the CPU 11 from the data bus of the system bus S-BUS.
Is latched (held) during the fifth clock cycle C5, and is output to the latch B113 and the P-GEN 14 (see (f) in the figure).

The P-GEN 14 receives the second write data (2nd C) within the period of the fifth clock cycle C5.
PU-DATA) parity data (2nd PARI
TYDATA) is generated and output to the latch B113 (see (g) in the figure).

Subsequently, the bus controller 111 asserts the latch B enable signal bar Latch B_enable at the start of the sixth clock cycle C6 to latch L11.
3 (see (h) of the same figure).

As described above, the parity data (2nd PARITY DATA) of the second write data (2nd CPU-DATA) of the CPU 11 is already P-.
Since it is generated by the GEN 14 in the fifth clock cycle C5 and is output to the DRAM 12, the latch B enable signal bar Latch B_enable asserted at the start of the sixth clock cycle C6 causes the latch B11.
3 is the second write data (2nd
CPU-DATA) and its parity data (2nd
CPU-DATA) are latched together and they are used as the second write data (2nd RAM-DATA) in the DRAM.
12 (see (i) in the figure). Then, the DRC 215 outputs the sixth clock cycle C6.
In the first half, the column address strobe signal CAS is asserted and output to the DRAM 12 (see (j) in the same figure).

As a result, the second write data (2n
d CPU-DATA) and its parity data (2nd
Data composed of PARITY DATA (2nd)
RAM-DATA) is written in the DRAM 12.
The DRC 215 asserts the column address strobe signal bar CAS as described above and then asserts the ram cycle end signal bar RAM_cycle_end to apply it to the bus controller 111.

Thereafter, the same operation as the clock cycles C5 and C6 is repeated twice (clock cycle C
7, C8 and clock cycles C9, C10) are repeated, and the third write data (3rd CPU-
DATA) and its parity data (3rd PAR
ITY-DATA), the fourth write data of the CPU 11 (4th CPU-DATA), and its parity data (4th PARITY-DATA) are written to the DRAM 12 at the eighth clock cycle C8 and the tenth clock cycle 10, respectively. ..

Then, in this case, the fourth write data (4th CPU-) output from the CPU 10 on the data bus of the system bus S-BUS at the eighth clock cycle C8.
DATA) is latched (held) in the latch A 112 by asserting the latch A enable signal bar Latch_enable which the bus controller 111 outputs to the latch A 112 in the next ninth clock cycle C9.
Therefore, the CPU 11 causes the ninth clock cycle C
From 9 it is possible to execute the next instruction.

That is, when viewed from the CPU 11 side, D
The burst write of 4 data to the RAM 12 is completed in 8 clock cycles. In this way, the two latches A112, the latch B113, and the bus for controlling the latch timing of these latches 112, 113 are provided.
System bus control circuit 100 including controller 111
Is provided between the CPU 11 and the DRAM 11,
The wait cycle in which the CPU 11 continues to output and hold the write data to the DRAM 11 on the data bus of the system bus S-BUS is from 4 clock cycles to 2 clock cycles in normal write and from 13 clock cycles to 8 clocks in burst write. Cycles down.

Therefore, the processing capacity of the CPU 11 is further improved as compared with the conventional one, and accordingly, the processing capacity of the entire system is remarkably improved as compared with the conventional one. Incidentally, in the above-mentioned embodiment, although four words are continuously written in the burst write, the row address strobe signal (bar R
By applying a column address strobe signal (bar CAS) as a clock with AS) being asserted, the present invention can be applied to a case where all data of the same row address are continuously written.

[0068]

According to the present invention, the write data and the parity data can be correctly written in the DRAM even if the CPU does not continuously output the write data on the data bus of the system bus until the parity data is generated. Since this is done, the wait time when the CPU writes data in the DRAM is shortened, and it is possible to improve the processing capability of the CPU and thus the processing capability of the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a circuit block diagram of a system to which a system bus control circuit of an embodiment is applied.

FIG. 3 is a timing chart for explaining a normal write operation for the DRAM in the above system.

FIG. 4 shows a burst for DRAM in the above system.
6 is a timing chart illustrating a write operation.

FIG. 5 shows the burst of each block in the system.
It is a figure explaining operation | movement of each clock cycle C1-C9 (C1) in write.

FIG. 6 is a circuit block diagram of a system in which a conventional CPU performs burst write to DRAM.

FIG. 7 is a timing chart for explaining a normal write operation for the DRAM of the CPU in the above conventional system.

FIG. 8 is a timing chart for explaining a burst write operation for the DRAM of the CPU in the above conventional system.

FIG. 9 is a diagram for explaining the operation in each clock cycle in the normal write and burst write of each block in the conventional system.

[Explanation of symbols]

 1 First Latch Means 2 Parity Data Generation Means 3 Second Latch Means 4 Control Means

Claims (2)

[Claims] 1. A first latch means for latching write data output from a CPU on a system bus, and a parity data generating means for generating parity data of the write data latched by the first latch means. , The write data latched by the first latch means and the parity data generated by the parity data generating means are latched, and the latched data are D
Second latch means for outputting to the RAM as write data, and operation upon receiving a write cycle start instruction from the CPU, and when the write data output on the system bus by the CPU is confirmed. When the parity data generation means generates the parity data of the write data, the second latch means is caused to latch the write data and the CPU is notified of the end of the data write. And a control unit that causes the latch unit to latch the write data output from the first latch unit and the parity data of the write data output from the parity data generation unit. Bus controller. 2. When the data writing to the DRAM is performed by a burst write, the control means controls the DRAM control means to perform the write control on the DRAM in the second and subsequent data writing.
To the CRU and to determine the latch timing of the first and second latch means after receiving the notification of the end of the data writing to the CRU. The system bus control device according to claim 1.