JPH05273298A - Semiconductor integrated circuit device and its test method - Google Patents
Semiconductor integrated circuit device and its test methodInfo
- Publication number
- JPH05273298A JPH05273298A JP4066945A JP6694592A JPH05273298A JP H05273298 A JPH05273298 A JP H05273298A JP 4066945 A JP4066945 A JP 4066945A JP 6694592 A JP6694592 A JP 6694592A JP H05273298 A JPH05273298 A JP H05273298A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- test pattern
- current
- semiconductor integrated
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000010998 test method Methods 0.000 title description 5
- 238000012360 testing method Methods 0.000 claims abstract description 34
- 238000001514 detection method Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000007547 defect Effects 0.000 description 3
- 238000011990 functional testing Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置及
びそのテスト方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its testing method.
【0002】[0002]
【従来の技術】半導体製造プロセスにおける微細加工技
術の進歩は、高機能化,大規模化した半導体集積回路デ
バイスの提供を可能にした。しかし、製造されたデバイ
スの良・否或いは所望の性能を有し得るか否かを検査す
るテストに関しては、機能が複雑になった分、その機能
を検査するテストパターンが増大するだけでなく、デバ
イスに適した完全なテストパターンを作成することが困
難になっている。2. Description of the Related Art Advances in microfabrication technology in semiconductor manufacturing processes have made it possible to provide highly functional and large-scale semiconductor integrated circuit devices. However, regarding the test for inspecting whether the manufactured device is good or bad or can have desired performance, not only the test pattern for inspecting the function increases due to the complicated function, It is difficult to create the perfect test pattern for the device.
【0003】半導体集積回路デバイスに従来から採用さ
れている機能テストは、デバイスの入力ピンからデバイ
スを励起するテストパターンを入力し、デバイス応答を
検証する方法が採られている。In the functional test conventionally used for semiconductor integrated circuit devices, a method of inputting a test pattern for exciting the device from an input pin of the device and verifying the device response is adopted.
【0004】[0004]
【発明が解決しようとする課題】上記従来の機能テスト
方法では、出力端子におけるデバイスの応答によって良
・否判別するため、半導体集積回路の内部に存在する故
障を、出力端子にまで伝搬するテストパターンを作成し
なければ不良の検出ができなかった。回路規模がそれほ
ど大きくないデバイスでは、このような条件を満たすテ
ストパターンを作成するのはさほど困難ではなかった。
しかし近年のように大規模化した半導体集積回路では機
能を検査するテストパターンもそれに伴って増大し、故
障検出率95%以上のテストパターンを作成するには膨
大な開発工数がかかるという問題があった。In the above-mentioned conventional functional test method, since the pass / fail judgment is made by the response of the device at the output terminal, a test pattern for propagating a fault existing in the semiconductor integrated circuit to the output terminal. The defect could not be detected without creating. It was not so difficult to create a test pattern satisfying such a condition in a device with a circuit scale not so large.
However, in a semiconductor integrated circuit which has become large in scale as in recent years, the number of test patterns for inspecting the function also increases, and there is a problem that enormous development man-hours are required to create a test pattern with a fault coverage of 95% or more. It was
【0005】本発明は上記従来の大規模集積回路デバイ
スのテスト方法の問題点に鑑みてなされたもので、デバ
イスの故障を検出するためのプロセスがテストパターン
に及ぼす負担を軽減した半導体集積回路及びそのテスト
方法を提供する。The present invention has been made in view of the problems of the above-described conventional testing method for large-scale integrated circuit devices, and a semiconductor integrated circuit and a semiconductor integrated circuit in which a process for detecting a device failure reduces the load on a test pattern. Provide the test method.
【0006】[0006]
【課題を解決するための手段】本発明は上記目的を達成
するために、CMOSからなる半導体集積回路装置にお
いて、電源端子の電流を検出する電流検出回路を内蔵
し、外部基準電圧を入力する基準電圧端子と、該基準電
圧端子から入力された基準電圧が一方の端子に供給さ
れ、他方の端子に上記電流検出回路の出力を供給した比
較器とを備えて構成する。In order to achieve the above object, the present invention provides a semiconductor integrated circuit device comprising a CMOS, which has a built-in current detection circuit for detecting a current at a power supply terminal and which receives an external reference voltage as a reference. It comprises a voltage terminal and a comparator in which the reference voltage input from the reference voltage terminal is supplied to one terminal and the output of the current detection circuit is supplied to the other terminal.
【0007】また本発明は、CMOS半導体集積回路装
置にテストパターンを印加し、テストパターンの待機状
態で電源端子に流れる電流を検出し、この検出電流を予
め入力された基準電圧に基づく電流と比較して行うテス
ト方法である。Further, the present invention applies a test pattern to a CMOS semiconductor integrated circuit device, detects a current flowing through a power supply terminal in a standby state of the test pattern, and compares the detected current with a current based on a reference voltage input in advance. It is a test method to be performed.
【0008】[0008]
【作用】CMOS構造を持つデバイスにおいて、デバイ
ス内部の故障(スタック故障,オープン故障,ショート
故障)が内在する場合、テストパターンを加え内部状態
を設定すると、電源端子に異常な電流が流れる。従って
テストパターンを走らせながら、半導体集積回路の電源
端子に設けた電流検出回路で電流を検出し、これを外部
から供給される基準電圧として出力端子に比較結果を出
力することにより、この結果で半導体集積回路の良・否
を判定することができる。In a device having a CMOS structure, if a device internal fault (stack fault, open fault, short fault) is inherent, if a test pattern is added to set the internal state, an abnormal current will flow to the power supply terminal. Therefore, while running the test pattern, the current detection circuit provided in the power supply terminal of the semiconductor integrated circuit detects the current and outputs the comparison result to the output terminal as the reference voltage supplied from the outside. It is possible to judge whether the integrated circuit is good or bad.
【0009】[0009]
【実施例】本発明の一実施例を、集積回路を構成するC
MOSインバータを挙げて説明する。CMOSインバー
タは、図1,図2,図3,図4に示すようにPチャネル
MOSトランジスタPchとNチャネルMOSトランジ
スタNchを含んで構成されている。上記PチャネルM
OSPchのソース側は電源Vccに、NチャネルMO
SNchのソース側はグランドに接続されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described as C constituting an integrated circuit.
A MOS inverter will be described as an example. The CMOS inverter is configured to include a P-channel MOS transistor Pch and an N-channel MOS transistor Nch as shown in FIGS. 1, 2, 3, and 4. P channel M
The source side of the OSPch is the power supply Vcc and the N channel MO
The source side of SNch is connected to the ground.
【0010】上記図に示すいずれのCMOSインバータ
も、図中の番号で示すいずれかの点で故障を生じてお
り、図1は0縮退故障(0になりっ放しの故障),図2
は1縮退故障(1になりっ放しの故障),図3はオープ
ン故障,及び図4はショート故障の場合を示す。Each of the CMOS inverters shown in the above figures has a failure at any of the points indicated by the numbers in the figure, and FIG. 1 shows a stuck-at 0 failure (fail at 0), and FIG.
Shows a case of 1 stuck-at fault (a fault that is left as it is 1), FIG. 3 shows an open fault, and FIG. 4 shows a short-circuit fault.
【0011】CMOSインバータに“高”レベルの入力
信号が印加されると、トランジスタPchはオフし、ト
ランジスタNchはオンになる。このとき図1のよう
に、入力線路上の点(1),(4),(5)のいずれ
か、或いは電源線路上の点(3)に0縮退故障が存在す
れば、たとえ集積回路デバイスを構成するその他の回路
が良であっても電流路が形成されて電流が流れる。また
図2に示すようにCMOSインバータの点(12),
(13),(16),(17)のいずれかに1縮退故障
が存在すれば、同様に電流路が形成されて電源端子に電
流が流れる。When a "high" level input signal is applied to the CMOS inverter, the transistor Pch turns off and the transistor Nch turns on. At this time, as shown in FIG. 1, if a 0 stuck-at fault exists at any of points (1), (4), and (5) on the input line or at point (3) on the power line, even if the integrated circuit device is A current path is formed and a current flows even if the other circuits constituting the above are good. In addition, as shown in FIG. 2, points (12) of the CMOS inverter,
If a stuck-at-1 fault exists in any of (13), (16), and (17), a current path is similarly formed and a current flows through the power supply terminal.
【0012】上記CMOSインバータの入力信号が
“低”レベルの場合には、トランジスタの導通関係は反
転し、トランジスタPchはオンし、トランジスタNc
hはオフになる。このとき図1の点(2),(6),
(7)のいずれかに0縮退故障が存在すれば、たとえ集
積回路デバイスを構成するその他の回路が良であっても
電流路が形成されて電流が流れる。同様に図2に示すよ
うにCMOSインバータの点(11),(14),(1
5)のいずれかに1縮退故障が存在すれば、同様に電流
路が形成されて電源端子に電流が流れる。更に図3のオ
ープン故障及び図4のショート故障が存在する場合にも
電源端子に電流が流れる。When the input signal of the CMOS inverter is at "low" level, the conduction relation of the transistor is inverted, the transistor Pch is turned on, and the transistor Nc is turned on.
h is turned off. At this time, points (2), (6), and
If a stuck-at-0 fault exists in any of (7), a current path is formed and current flows even if the other circuits constituting the integrated circuit device are good. Similarly, as shown in FIG. 2, points (11), (14), (1
If a stuck-at-1 fault exists in any of 5), a current path is similarly formed and a current flows to the power supply terminal. Further, even when the open failure of FIG. 3 and the short failure of FIG. 4 exist, current flows through the power supply terminal.
【0013】電源端子に電流が流れることを利用して、
テストパターンを印加しながら電源端子に電流検出回路
を接続し、各テストパターンごとの電流測定の結果を観
測することで、CMOSに内存する故障を検出すること
ができる。Utilizing the fact that a current flows through the power supply terminal,
A failure existing in the CMOS can be detected by connecting a current detection circuit to the power supply terminal while applying the test pattern and observing the result of the current measurement for each test pattern.
【0014】図5は上記故障検出の原理に基づいたテス
ト方法を実施するための電流検出回路で、被テスト用半
導体集積回路デバイスと一体的に半導体基板に内蔵させ
て形成されている。被テスト集積回路48に加えて、電
流検出のために第1演算増幅器41及び第2演算増幅器
42が設けられ、第1演算増幅器41の一方の入力端は
抵抗44を介して電源端子51に接続されて電源Vcc
が印加され、他方の入力端は抵抗46を介して被測定デ
バイス48に接続されている。また上記両抵抗44,4
6の他端間には抵抗値Rsの電流検出抵抗43が接続さ
れている。抵抗45は第1演算増幅器41の帰還抵抗で
あり、抵抗47は入力端に接続された接地抵抗である。
上記第1演算増幅器41の出力信号は第2演算増幅器4
2の一方の入力端に供給され、第2演算増幅器42の他
方の入力端には基準電圧端子49からテスト工程時に基
準電圧Vrefが供給される。FIG. 5 shows a current detection circuit for carrying out a test method based on the principle of failure detection, which is formed integrally with a semiconductor integrated circuit device under test on a semiconductor substrate. In addition to the integrated circuit under test 48, a first operational amplifier 41 and a second operational amplifier 42 are provided for current detection, and one input end of the first operational amplifier 41 is connected to a power supply terminal 51 via a resistor 44. Powered by Vcc
Is applied, and the other input end is connected to the device under test 48 via the resistor 46. Also, both resistors 44 and 4
A current detection resistor 43 having a resistance value Rs is connected between the other ends of the resistors 6. The resistor 45 is a feedback resistor of the first operational amplifier 41, and the resistor 47 is a grounding resistor connected to the input end.
The output signal of the first operational amplifier 41 is the second operational amplifier 4
2 is supplied to one input terminal of the second operational amplifier 42, and the other input terminal of the second operational amplifier 42 is supplied with the reference voltage Vref from the reference voltage terminal 49 during the test process.
【0015】上記構成からなる電流検出回路内蔵の集積
回路デバイスにおいて、電源電圧Vccを印加してデバ
イス48にテストパターンを入力すると、デバイスに故
障が生じている場合には、上述の原理に基づいて電源電
流が流れる。そのため電流検出抵抗43の両端には流れ
る電流iによって電圧降下(Rs×i)が生じる。この
電流に相当する電圧を第1演算増幅器41で検出し、図
6に示すような検出信号O1が出力される。この検出信
号は基準電圧Vrefが入力された第2演算増幅器42
に入力されて両者の比較がなされ、テスト結果の出力と
して信号O2が形成され、この信号レベルから良・否が
判定される。テスト工程では、上記第2演算増幅器42
で基準電圧Vrefと検出信号O1を比較する際は、ス
トローブをたてて検出する。このようにテストパターン
を走らせながら集積回路デバイスの良・否を判定する。In an integrated circuit device having a current detection circuit having the above-mentioned structure, when a power source voltage Vcc is applied and a test pattern is input to the device 48, if a failure occurs in the device, it is based on the above-mentioned principle. Power supply current flows. Therefore, a voltage drop (Rs × i) is caused by the current i flowing across the current detection resistor 43. The voltage corresponding to this current is detected by the first operational amplifier 41, and the detection signal O1 as shown in FIG. 6 is output. The detection signal is the second operational amplifier 42 to which the reference voltage Vref is input.
The signal O2 is formed as an output of the test result, and the pass / fail is determined from this signal level. In the test process, the second operational amplifier 42
When comparing the reference voltage Vref with the detection signal O1, the strobe is detected. In this way, the quality of the integrated circuit device is judged while running the test pattern.
【0016】上記実施例はインバータの例を挙げて説明
したが、CMOSスタティック論理回路であれば同様に
電流検出回路を内蔵させて構成することにより、テスト
することができる。Although the above embodiment has been described by taking the example of the inverter, a CMOS static logic circuit can be tested by similarly including a current detection circuit therein.
【0017】[0017]
【発明の効果】従来のテスト方法では内在する故障を出
力端子に伝搬させなければ不良を検出できなかったが、
本発明を用いれば簡単な電流検出回路を追加すること
で、集積回路内に故障があれば電源端子で不良検出する
ことができ、テストパターンも短くてすみ、デバイス開
発コストの低減に大いに貢献する。According to the conventional test method, the defect cannot be detected unless the inherent failure is propagated to the output terminal.
By using the present invention, by adding a simple current detection circuit, if there is a failure in the integrated circuit, it is possible to detect a defect at the power supply terminal, the test pattern can be short, and it greatly contributes to the reduction of device development cost. ..
【図1】 本発明の一実施例を説明するための0縮退故
障モデル。FIG. 1 is a zero stuck-at fault model for explaining an embodiment of the present invention.
【図2】 本発明の一実施例を説明するための1縮退故
障モデル。FIG. 2 is a one stuck-at fault model for explaining an embodiment of the present invention.
【図3】 本発明の一実施例を説明するためのオープン
故障モデル。FIG. 3 is an open failure model for explaining an embodiment of the present invention.
【図4】 本発明の一実施例を説明するためのショート
故障モデル。FIG. 4 is a short-circuit failure model for explaining an embodiment of the present invention.
【図5】 本発明による一実施例の電流検出回路。FIG. 5 is a current detection circuit according to an embodiment of the present invention.
【図6】 図5の回路動作を説明するための信号波形
図。FIG. 6 is a signal waveform diagram for explaining the circuit operation of FIG.
(1)〜(7) 0縮退故障 (11)〜(17) 1縮退故障 21〜28 オーブン故障 31〜36 ショート故障 41,42 オペアンプ 43 電流検出抵抗Rs 44〜47 抵抗 48 被測定デバイス 49 基準電圧Vref 50 比較結果出力端子 51 電源端子 (1) to (7) 0 stuck-at failure (11) to (17) 1 stuck-at failure 21-28 oven failure 31-36 short-circuit failure 41,42 operational amplifier 43 current detection resistance Rs 44-47 resistance 48 measured device 49 reference voltage Vref 50 Comparison result output terminal 51 Power supply terminal
Claims (2)
おいて、電源端子の電流を検出する電流検出回路を内蔵
し、外部基準電圧を入力する基準電圧端子と、該基準電
圧端子から入力された基準電圧が一方の端子に供給さ
れ、他方の端子に上記電流検出回路の出力を供給した比
較器とを備えてなることを特徴とする半導体集積回路装
置。1. A semiconductor integrated circuit device comprising a CMOS, comprising a current detection circuit for detecting a current of a power supply terminal, a reference voltage terminal for inputting an external reference voltage, and a reference voltage input from the reference voltage terminal. A semiconductor integrated circuit device comprising: a comparator supplied to one terminal and the other terminal supplied with the output of the current detection circuit.
ンを印加し、テストパターンの待機状態で電源端子に流
れる電流を検出し、この検出電流を予め入力された基準
電圧に基づく電流と比較して行うことを特徴とする半導
体集積回路装置のテスト方法。2. A test pattern is applied to a CMOS semiconductor integrated device, a current flowing through a power supply terminal is detected in a standby state of the test pattern, and the detected current is compared with a current based on a reference voltage input in advance. A method for testing a semiconductor integrated circuit device, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4066945A JPH05273298A (en) | 1992-03-25 | 1992-03-25 | Semiconductor integrated circuit device and its test method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4066945A JPH05273298A (en) | 1992-03-25 | 1992-03-25 | Semiconductor integrated circuit device and its test method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05273298A true JPH05273298A (en) | 1993-10-22 |
Family
ID=13330663
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4066945A Pending JPH05273298A (en) | 1992-03-25 | 1992-03-25 | Semiconductor integrated circuit device and its test method |
Country Status (1)
Country | Link |
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JP (1) | JPH05273298A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5760599A (en) * | 1995-08-14 | 1998-06-02 | Sharp Kabushiki Kaisha | Method and apparatus for testing semiconductor integrated circuits |
US5949798A (en) * | 1996-02-06 | 1999-09-07 | Nec Corporation | Integrated circuit fault testing system based on power spectrum analysis of power supply current |
JP2005140759A (en) * | 2003-11-10 | 2005-06-02 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit and failure detection method for semiconductor integrated circuit |
-
1992
- 1992-03-25 JP JP4066945A patent/JPH05273298A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5760599A (en) * | 1995-08-14 | 1998-06-02 | Sharp Kabushiki Kaisha | Method and apparatus for testing semiconductor integrated circuits |
US5949798A (en) * | 1996-02-06 | 1999-09-07 | Nec Corporation | Integrated circuit fault testing system based on power spectrum analysis of power supply current |
JP2005140759A (en) * | 2003-11-10 | 2005-06-02 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit and failure detection method for semiconductor integrated circuit |
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