JPH05268579A - Television system converter - Google Patents

Abstract

PURPOSE:To avoid the effect of deviation in a horizontal synchronization of an input video signal onto a pattern and to avoid improper operation of write and read to/from a memory. CONSTITUTION:Two memories 23A, 23B are operated alternately in the write/ read state to convert the number of lines and the number of fields. Horizontal synchronization on the read side is synchronized with the horizontal synchronization on the write side in the vicinity of the vertical synchronization location on the read side in the system conversion and the non-system conversion. A picture frame of a video signal written in the memories 23A, 23B is changed in response to a deviation in the horizontal synchronization of the input video signal and the deviation in the horizontal synchronization on the write side in the system conversion. Since the effect of the deviation in the horizontal synchronization of the input video signal is propagated to the read side during the vertical blanking period of the read side, no skew appears on an output pattern. Furthermore, since the picture frame is changed according to the deviation, the overlapping of the write/read operation of the memories 23A, 23B is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television system converter.

[0002]

2. Description of the Related Art Currently, the television (TV) system adopted in the world is mainly composed of the following three types because of the structure of a composite video signal.
It can be divided into methods. System name Scan line / number of frames Color subcarrier Modulation system NTSC 525/60 3.58 MHz Quadrature two-phase modulation PAL 625/50 4.43 MHz Quadrature two-phase modulation However, V axis phase inversion for each scan line SECAM Same as above 4.25 MHz 4.206 MHz FM Modulation Furthermore, the NTSC and PAL each have a combination of scanning line / frame number and color modulation method, and are as follows. Method name Scan line / number of frames Color subcarrier V-axis phase inversion for each scan line 4.43NTSC 525/60 4.43MHz None M-PAL 525/60 3.58MHz Yes N-PAL 625/50 3.58MHz Yes , NTSC, M-PAL, N-PAL 3.58
Each MHz is slightly different.

From these, the requirements necessary for mutual conversion between television systems are summarized in the following two. (1) Conversion of scanning line / number of frames (line / field) 525
/ 60,625 / 50 (2) Conversion of color modulation system Carrier frequency (fsc) Quadrature two-phase modulation, FM modulation Presence / absence of V-axis phase inversion (2) is suitable for each system as demodulator and modulator of color signal It can be easily done by using the one. However, (1) generally requires an image memory because there is a time lag between the signals before and after conversion.

There is also a system in which the application is limited to viewing on a television receiver and only the conversion processing of (2) is used for system conversion.

It is expected that the vertical synchronizing circuit of the 625/50 system TV has a large allowable amount and can sufficiently cope with the TV signal of the 525/60 system, but some readjustment of the vertical synchronization is necessary. Therefore, it is unavoidable that the figure is flattened by being flattened up and down.

[0006] As mentioned above, only TV viewing is possible.
Although viewing with a 525/60 system TV signal is possible, it is impossible to record / reproduce it on a 625/50 system VTR or the like because the VTR has a small allowance for the difference in vertical synchronization. However, in terms of cost, it can be realized at low cost because only the color signal is remodulated.

If the conversion of (1) is also performed, it is necessary to first convert the number of lines. 525/60 →
In case of 625/50 conversion, 100 per field
It is an increase of lines, and it is necessary to increase the ratio of 1 line to 5 lines (illustrated in FIG. 41A). Conversely, 625/50 →
In the case of the 525/60 system conversion, the number of lines is reduced by 100 lines per field, and it is necessary to reduce the number of lines every 6 lines (shown in FIG. 9B). The increase / decrease in the number of lines
It can be realized simply by overlapping or thinning the same line.

From a strict calculation, the number of converted lines becomes ± 5 lines deficient or shortage due to simple duplication every 5 lines or thinning out every 6 lines, but this is to be absorbed in the vertical blanking period. ..

As is clear from FIG. 41, the image memory for one line or more is required for converting the number of lines. In the figure, it seems that one line is enough, but in order to convert all one field, an image memory for one field or more is required as shown below.

FIG. 42 shows field number conversion.
Referring to the conversion part of the m + 4 → m + 4 ′ field in FIG. A, the last line of the m + 4 field moves to the m + 4 ′ field (arrow P1), which coincides with the timing of the last line of the m + 5 field. Therefore, m +
It is necessary to delay the last line of 4 fields by 1 field.

On the other hand, looking at the conversion portion of the n → n ′ field in FIG. 6B, the last line of the n field is n−
This coincides with the timing of the last line of the 1'field (arrow P2), and a delay of 1 field is required.
The same thing occurs in the conversion part of the n + 5 → n + 5 ″ field (arrow P3).

Strictly speaking, the above line coincidence is
Since it does not match perfectly with a slight line difference, it is completely 1.
A field delay amount is not necessary, but one field is used here for simplification.

A one-field delay is now usually implemented by digitizing the signal and using the digital memory as an image memory.

Horizontal resolution is 320 lines, luminance (Y) S / N
The memory capacity of one field required for system conversion of a standard TV signal of 46 dB for color and C / S of 36 dB or higher is as follows. However, in consideration of the conversion of (2) described above, the C system already has color difference signals RY = V, B.
Assuming demodulation to the state of -Y = U, two systems are required.

Here, the following setting values are considered for the sampling frequencies and gradations of the Y and C systems.

Y system Sampling frequency: 8 MHz Gradation: 8 bits C system Sampling frequency: 3 MHz Gradation: 6 bits Considering mutual conversion between 525/60 system and 625/50 system, 1 field is based on 625/50 system (In the case of FIG. 42B).

From the above, the memory capacity of one field is obtained by the following equation. {8 × 8 × 10 ⁶ + (6 × 3 × 10 ⁶ × 2)} ÷ 50 = 1.8 × 10 ⁶ = 1.8 Mbits If the resolution and gradation set above are required to be improved, The memory capacity will be larger.

Further, looking at the state of line number conversion in more detail, since the TV signal is interlaced in both the 525/60 system and the 625/50 system, a simple field as shown in FIG. 41 is used. The conversion of the number of lines per unit may impair the image quality in the vertical direction.

FIG. 43 shows in detail the position of each line when the images are displayed in the same image size when the system conversion from the 525/60 system to the 625/50 system is performed. The solid line is the line position of the odd field and the dotted line. Indicates the line position of the even field, and since they are interlaced, both
They are arranged alternately.

FIG. 6A shows a state of conversion when a field memory is used, and represents the same type of field (odd → odd or even → even). There are some parts such as the z ″ and a ″ lines where the vertical positional relationship is reversed, and there are also parts where the positions are shifted downward by almost one line like the a ′ to a ″ lines.

FIG. 9B shows a state of conversion when a field memory is used, and shows between different fields (odd → even or even → odd). Again,
Up and down reversals are made in the f'-e "to f" lines, and the positions are greatly shifted downward in the f'-f "lines.

Incidentally, as is apparent from FIG. 42, since one field duplication (n + 5 ″ in FIG. B) and thinning (m + 5 in FIG. A) occur during conversion, conversion between same-type fields and conversion between different types of fields The cyclical change with is inevitable.

In each field, a->c-> e is interlaced, but since it is continuously visible from a to k in the eyes, vertical line inversion as shown in FIGS. 43A and 43B and significant line position. The shift is recognized as vertical graphic distortion.

On the other hand, in FIG. 6C, since the conversion field is formed from two fields (one frame),
There is no reversal of the upper and lower lines, and the positional deviation is suppressed to a maximum of 0.5 lines, and the figure distortion in the vertical direction is greatly improved.

Most of the conventional TV system converters are for broadcasting and for business use, and since they do not like image quality deterioration, they also have a large memory capacity per field and the above-mentioned FIG. 43C.
Since the number of lines is converted in each frame, a memory for one frame is required. Actually, in order to further improve the image quality, the one having a memory of several frames is mainstream.

Further, as is apparent from FIG. 42, the TV format converter must simultaneously perform writing (writing) and reading (reading) to this memory for the convenience of immediately converting and outputting an input signal. Moreover, since each data position sequentially changes with time, the above field memory (or frame memory) must have two asynchronous write / read ports. As a memory that meets this condition, a video memory (V-RAM) developed for such image processing is used, or a large number of general-purpose memories are driven by serial / parallel conversion to apparently perform asynchronous operation. I had no choice but to do it.

The advantages and disadvantages of each conversion are summarized as follows. (A) Line / field conversion + color modulation system conversion Merit: It becomes a complete TV system conversion that can be recorded on a VTR or the like.

Disadvantages: Asynchronous write / read is possible, and a large-capacity memory capable of guaranteeing image quality is required, which is expensive and complicated. (B) Conversion of color modulation method only Merit: It is simple and inexpensive because it only has a chroma remodulation circuit.

Disadvantages: Half of which depends on the circuit of the TV receiver, so recording on a VTR or the like is not possible. Also,
It is necessary to re-establish the vertical synchronization of the TV. Furthermore, the screen is flattened up and down.

[0030]

As described above, the VTR
To convert (a) so that recording to
There is a disadvantage that a large-capacity expensive dedicated video memory or a large amount of general-purpose memory is required.

Therefore, according to the present invention, the television system conversion device for line / field conversion is constructed inexpensively without using a large capacity memory, and the output screen is displayed even if a large deviation occurs in the horizontal synchronization of the input video signal. It is possible to avoid the influence on.

[0032]

According to the present invention, there are provided first and second memories having a storage capacity of 1/2 horizontal period in the horizontal direction and a storage capacity of 1 vertical period in the vertical direction. It is premised on a television conversion device that converts the number of lines and the number of fields by writing and reading data in the first half of the horizontal period to the first memory and writing and reading data in the second half of the horizontal period to the second memory. To do.

When the system conversion is not performed, the horizontal synchronization and the vertical synchronization on the read side of the memory are synchronized with the horizontal synchronization and the vertical synchronization on the write side, respectively, and the system conversion is performed near the vertical synchronization position on the write side of the memory. In this case, the horizontal sync on the read side is synchronized with the horizontal sync on the write side near the vertical sync position on the read side without synchronizing the vertical sync on the read side with the vertical sync on the write side.

When the system conversion is performed, the phase difference between the horizontal sync of the input video signal and the horizontal sync on the writing side is detected, and the image of the video signal written in the first and second memories is detected according to the phase difference. The frame is changed.

Further, the detection of the phase difference is detected every predetermined period, and when the substantially same phase difference is repeated twice or more, the image frame is changed according to the phase difference.

[0036]

The number of lines and the number of fields are converted by alternately controlling the first and second memories to be in the write state and the read state for every 1/2 horizontal period, so that an inexpensive general-purpose video RAM is used instead of an expensive video RAM. It can be configured by using only two memories (storage capacity for 0.5 field).

Further, when a large phase shift occurs in the horizontal synchronization of the input video signal, the influence is transmitted to the reading side during the vertical blanking period on the reading side, so that it is preferable that the skew appears on the output screen. It can be avoided.

Further, since the image frames of the video signals to be written in the first and second memories are changed according to the phase shift between the horizontal sync of the input video signal and the horizontal sync on the writing side, even if the phase shift becomes large, Alternate operations of writing and reading of the first and second memories will not fail.
In this case, by detecting the phase shift every predetermined period, it is possible to prevent the image quality from being deteriorated without frequently changing the image frame.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

In the figure, the luminance signal Y is supplied to the input terminal 1Y. The luminance signal Y is supplied to the adder 3 via the resistor 2. The wobbling clock WOB output from the write timing generator 4 is supplied to the adder 3 via the resistor 5. Then, the luminance signal Y added with the wobbling clock WOB output from the adder 3 is supplied to the switch circuit 6.

The carrier color signal C ^* is supplied to the input terminal 1C. This color signal C ^* is supplied to the color demodulator 7. The red color difference signal RY (V signal) and the blue color difference signal BY (U signal) output from the color demodulator 7 are supplied to the switch circuit 6.

The luminance signal Y supplied to the input terminal 1Y is also supplied to the AFC circuit 8 including a sync separation circuit and the like. A horizontal synchronizing pulse PH (frequency fh) is supplied from the AFC circuit 8 to the timing generator 4 as a synchronizing reference signal, and a clock, a latch pulse, a switching control signal and the like are formed based on the synchronizing signal PH.

The switching control signals SW1 and SW2 are supplied from the timing generator 4 to the switch circuit 6, and the luminance signal Y is supplied.
And the V and U signals are combined. The combined signal output from the switch circuit 6 is supplied to the A / D converter 9. A /
The D converter 9 receives the clock CLK from the timing generator 4.
1 (frequency is 1100 fh) is supplied and the synthesized signal is 1
The sample is converted into a 6-bit digital signal. In this case, conversion is performed after removing the sync signal in order to secure the S / N.

FIG. 3 shows a part of the switch circuit 6 and the A / D converter 9.

In the figure, 6A and 6B are changeover switches which constitute the switch circuit 6. The V signal is supplied to the fixed terminal on the v side of the changeover switch 6A, and the U signal is supplied to the fixed terminal on the u side. The changeover switch 6A is changed over on the basis of the changeover control signal SW1 and is connected to the v side and the u side by alternating one horizontal period. As a result, the changeover switch 6A alternately outputs the color signal C which is the V signal and the U signal every horizontal period.

Color signal C output from changeover switch 6A
(FIG. 4B) is supplied to the fixed terminal on the c side of the changeover switch 6B, and the luminance signal Y (A in FIG. 4) is supplied to the fixed terminal on the y side.

The change-over switch 6B is changed over based on the change-over control signal SW2 (FIG. 9C). in this case,
connected to the y side for a period of 18 / 1100fh, and c
The connection with the side for 2/1100 fh is performed alternately. That is, the changeover switch 6B outputs a combined signal in which the color signal C is inserted to the luminance signal Y at a cycle of 1 / 55fh for a period of 2 / 1100fh (D in the same figure).

The output signal of the changeover switch 6B is supplied to the A / D converter 9. In this A / D converter 9, 1/11
It is converted into a digital signal by the clock CLK1 (E in the figure) having a cycle of 00fh (F in the figure).

Returning to FIG. 1, the output signal of the A / D converter 9 (FIG. 5A) is supplied to the latch circuit 10. A latch pulse P1 is supplied from the timing generator 4 to the latch circuit 10 at the timing of each sample data of the luminance signal Y (B in the same figure), and the luminance signal Y is latched (C in the same figure).

The luminance signal Y latched and output by the latch circuit 10 is supplied to the digital low pass filter 11. The clock CLK1 is supplied to the low-pass filter 11 from the timing generator 4 and low-pass processing is performed. By this low-pass processing, the 7-bit luminance signal Y'is output from the low-pass filter 11 (D in the same figure).

The luminance signal Y'output from the low pass filter 11 is supplied to the latch circuit 12. A latch pulse P2 having a frequency of 275 fh is supplied from the timing generator 4 to the latch circuit 12 (E in the figure). Here, the latch pulse P2 is inverted in phase every horizontal period. Therefore, the data rate from the latch circuit 12 is 275 fh.
The line offset sub-sampled luminance signal Y ′ is output (F in the figure).

The output signal of the A / D converter 9 (see FIG. 5)
A) is a parallel / serial converter (P / S converter) 13
Is supplied to. The P / S converter 13 is supplied with the latch pulse P3 from the timing generator 4 at the timing of the sample data of the color signal C having a cycle of 1/55 fh (G in the figure), and the color signal C is latched (the same). (Figure H). The P / S converter 13 further includes 275 fh from the timing generator 4.
The clock CLK2 having the frequency is supplied (I in the figure), and each bit data of the latched sample data is sequentially output (J in the figure). At the time of this conversion, the lower 1 bit (C0) of the color signal C is truncated.

The parallel data (7 bits) luminance signal Y '(FIG. 6A) and P /
Color signal C of serial data output from the S converter 13
(B in the figure) is supplied to the switch circuit 14 as 8-bit parallel data. In this case, the 1-bit color signal C is positioned on the lower bit side of the luminance signal Y '.

The switch circuit 14 includes a timing generator 4
Then, the switching control signal SW3 and the information data INF are supplied, and the information data INF is added to the head of the data in each horizontal period.

The output signal of the switch circuit 14 is supplied to the switch circuit 15. The switching control signal SW4 is supplied from the timing generator 4 to the switch circuit 15 (C in the same figure). The switch circuit 15 alternately outputs the upper 4-bit data and the lower 4-bit data of the 8-bit parallel data at intervals of 1/550 fh (D in the same figure).

As shown in FIG. 6D, the information data I
NF is composed of 4-bit data. Here, OXE indicates whether the field is an odd number or an even number, UXV indicates whether the color signal C of the line is a U signal or a V signal, and AXB indicates that the luminance signal Y ′ of the line is a line offset sub signal. It indicates whether it is the A pattern or the B pattern of sampling. In addition, LDEC indicates that the next line will be decimated.

FIG. 7 shows the configuration of the luminance signal system from the input terminal 1Y to the low pass filter 11.

In the figure, the luminance signal Y supplied to the input terminal 1Y is supplied to the adder 3 via the resistor 2.

In the timing generator 4, the clock CL
K1 (1100 fh) is phase-inverted by the inverter 4A and then frequency-divided by the frequency divider 4B. The output signal of the frequency divider 4B is supplied as a wobbling clock WOB to the adder 3 via the resistor 5. In this case, the addition ratio of the luminance signal Y and the wobbling clock WOB in the adder 3 is determined by the resistance values of the resistors 2 and 5,
The amplitude (peak-to-peak value) of the wobbling clock WOB supplied to the adder 3 is set to be an odd multiple of 1/2 step width of the 6-bit quantization step, which is 1 in this example.

The added signal of the luminance signal Y from the adder 3 and the wobbling clock WOB is supplied to the A / D converter 9 and converted into 6-bit digital data Xn. In this case, as described above, the A / D converter 9 has the clock C.
LK1 (1100fh) is supplied as a conversion clock (sampling clock).

When the wobbling clock WOB is formed as described above, the phase of the clock CLK1 is inverted by the inverter 4A, so that the changing point (rising edge and falling edge) of the wobbling clock WOB does not coincide with the sampling point. Is being done.

The 6-bit digital data Xn output from the A / D converter 9 is supplied to the digital adder 11A constituting the low-pass filter 11 and the data terminal D of the D flip-flop 11B. D
The clock CLK1 (110
0fh) is supplied. From the D flip-flop 11B, one clock period (1/1
Digital data Xn-1 delayed by 100 fh) is obtained, and this digital data Xn-1 is supplied to the adder 11A.

In the adder 11A, the digital data Xn and Xn-1 are added together to generate 7-bit digital data Yn.
Is output, and this digital data Yn is used as the output Y'of the low-pass filter 11.

In this case, the adder 11A and the D flip-flop 11B form a low-pass filter whose cutoff frequency is substantially half the frequency of the clock CLK1. Therefore, the wobbling clock WOB added by the adder 3 is automatically removed by the low-pass filter 11 and does not appear in the digital data Yn.

Here, how the digital data Yn is formed will be described.

FIG. 8 shows a quantization state in a normal A / D converter. As is clear from this figure, in a normal A / D converter, the number of bits is from 6 bits (broken line) to 7 bits.
As the number of bits (one-dot chain line) increases, the input luminance signal Y (solid line) approaches, and good results can be obtained. This is because the 7-bit quantization step (Ln and Mn) is finer than the 6-bit quantization step (Ln).

In this example, the luminance signal Y is added by the adder 3.
The wobbling clock WOB is added to (the broken line is shown in FIG. 9A), and the signal (Y + WO) is supplied to the A / D converter 9.
B) is repeatedly shifted with a half step width of the 6-bit quantization step (shown by the solid line in the figure). Therefore, the digital data Xn output from the A / D converter 9 is arranged as shown by the point "." In the figure.

In the D flip-flop 11B, the digital data Xn is delayed by one clock of the clock CLK1. Therefore, the digital data Xn-1 is arranged as shown by a point ".largecircle." In FIG. 9B. Therefore, the 7-bit digital data Yn output from the adder 11A
Are arranged as shown by the points "x" in FIG.

After all, 7-bit digital data Yn
Gives the same result as the quantization by the 7-bit A / D converter (see the alternate long and short dash line in FIG. 8).

Returning to FIG. 1, the 4-bit digital data DW output from the switch circuit 15 is supplied to the movable terminal of the changeover switch 21 as a write signal to the memory. The fixed terminals on the a side and the b side of the changeover switch 21 are connected to the fixed terminals on the a side and the b side of the changeover switch 22, respectively.

The connection points of the fixed terminals on the a side of the changeover switches 21 and 22 are connected to the memory 23A, and the connection points of the fixed terminals on the b side of the changeover switches 21 and 22 are connected to the memory 23.
Connected to B.

Further, the horizontal write start signal WHS is written from the AFC circuit 8 to the memory write timing generator 24.
And a write vertical start signal WVS
Is supplied. In the timing generator 24, the write address signal WAD is generated based on the start signals WHS and WVS.
And the address signal WAD is generated by the switch circuit 2
5 is supplied to the memory 23A or 23B.

Further, from the AFC circuit 8, the synchronization generator 26
Is supplied with the signal HMDP output at the intermediate position of each horizontal period. Then, the synchronization generator 26 outputs the read horizontal start signal RH to the memory read timing generator 27.
S is supplied and read vertical start signal RV
S is supplied. The timing generator 27 uses the read address signal RA based on the start signals RHS and RVS.
D is formed, and this address signal RAD is supplied to the memory 23B or 23A via the switch circuit 25.

A changeover control signal SW5 is supplied from the timing generator 24 to the changeover switches 21 and 22. The changeover switch 21 is connected to the a side in the first half period of each horizontal period, and is connected to the b side in the latter half period. On the other hand, the changeover switch 22 is connected to the b side in the first half period of each horizontal period,
In the subsequent half period, it is connected to the a side.

The switching control signal SW5 is also supplied from the timing generator 24 to the switch circuit 25. As a result, the write address signal WAD is supplied to the memory 23A and the memory 23B is supplied in the first half of each horizontal period.
The read address signal RAD is supplied to. On the other hand, in the latter half of each horizontal period, the write address signal WAD is supplied to the memory 23B and the read address signal RAD is supplied to the memory 23A.

The memories 23A and 23B have a storage capacity of 1/2 horizontal period in the horizontal direction and a storage capacity of 1 vertical period in the vertical direction. Memory 2
The first half data is written in 3A in the first half period of each horizontal period, and the first half data is read from the memory 23A in the second half period of each horizontal period. The latter half data is written in the memory 23B in the latter half period of each horizontal period, and the latter half data is read from the memory 23B in the first half period of each horizontal period.

Here, the conversion of the number of lines and the number of fields is realized by controlling the write address signal WAD and the read address signal RAD to the memories 23A and 23B.

That is, the NTSC system (525/60
41A and 42A) when converting from (system) to the PAL system (625/50 system), thinning is performed at a ratio of 1 field to 6 fields during reading, and at a ratio of 1 line to 5 lines in each field. Same line is 2
Read once.

On the contrary, when converting from the PAL system to the NTSC system (see FIGS. 41B and 42B), 6 is written at the time of writing.
The lines are thinned out at a rate of 1 line, and the same field is repeatedly read at a rate of 1 field to 5 fields during reading. , The memory 23A,
The storage capacity of 23B is 262 or 2 of 525/60 series.
63 lines are basically used. When capturing a 625/50 series 312 or 313 line, it is compressed and expanded in the vertical direction.

Most of the horizontal and vertical blanking periods not directly related to the screen are not stored in the memories 23A and 23B. As a result, the storage capacity of the memories 23A and 23B is 84% of the effective screen for all screens.

From the above, the memory capacity required in this example is as follows, and the memories 23A, 23
As B, for example, a general-purpose 256K-bit DRAM can be used.

{(7 × 275) + (5 × 55)} × 263 × 0.84 = 486 Kbits By the way, the cycle time of a general-purpose 256 Kbit DRAM is as follows. It takes 200 nsec or more to complete the writing or reading. This cycle time is longer than the data cycle (1/550 fh) of the write data DW output from the switch circuit 15, and writing / reading in real time becomes impossible.

Therefore, in this example, when writing and reading data, a write cycle and read cycle method called page mode is adopted.

That is, in the normal write mode, FIG.
As indicated by 0A, since both the row address strobe and the column address strobe are designated, the cycle time required from writing these to writing the data DW is 200 nsec.

On the other hand, in the write mode by the page mode, as shown in FIG. 9B, the row address strobe and the column address strobe are designated only for the first cell of each horizontal line, and for the subsequent cells. Need only specify the column address stove, so 2
The cycle time for the cells after the th is 100 nsec.

In FIG. 10, RAS bar is a row address strobe pulse, CAS bar is a column address strobe pulse, WAD is a write address signal, and
DW is write data.

The same applies to the read mode. FIG. 11A shows the timing in the normal read mode, and FIG. 11B shows the timing relationship in the page mode.
In FIG. 11, RAS is a row address strobe pulse, CAS is a column address strobe pulse, RAD is a read address signal, and DR is read data.

According to the page mode, the cycle time is the data cycle of the write data DW (1 / 550f
Since it is shorter than h), the general-purpose DRAM described above can be used.

Returning to FIG. 1 and FIG. 2, the read data DR output from the changeover switch 22 is the demultiplexer 3
1 is supplied. The horizontal synchronization pulse PH ′ is supplied from the synchronization generator 26 to the read timing generator 32. The demultiplexer 31 is supplied with the switching control signal SW6, the latch pulses P4 to P6 and the control signal CNP from the timing generator 32. From the demultiplexer 31,
The information data INF, the luminance signal Y ', and the color signal C separated from the output signal of the changeover switch 22 are output.

FIG. 12 is a diagram showing a specific configuration of the demultiplexer 31. In the figure, the read data DR (FIG. 13A) output from the changeover switch 22 is supplied to the movable terminal of the changeover switch 31A. Changeover switch 31
The switching control signal SW6 is supplied to A, and is connected to the a side in correspondence with the period of the information data INF added at the beginning of each horizontal period, and is connected to the b side in the other periods. Information data INF is obtained at the fixed terminal on the a side of the changeover switch 31A.

The signal obtained at the fixed terminal on the b side of the changeover switch 31A is the data terminal D of the latch circuits 31B and 31C.
Is supplied to. The latch pulse P4 is supplied to the latch circuit 31B at the timing of the 4-bit data Y6 'to Y3' (FIG. 13B), and the 4-bit data Y6 'to Y3' is output from the latch circuit 31B at the data rate of 275fh. (Fig. C). A latch pulse P5 is supplied to the latch circuit 31C at the timing of 4-bit data Y2 'to Y0' and C (any of C5 to C1) (D in the figure), and 4-bit data Y2 'from the latch circuit 31C. ~ Y0 ', C (C
5 to C1) is output at a data rate of 275 fh (E in the same figure).

The 4-bit data Y6 'to Y3' output from the latch circuit 31B and the 3-bit data Y2 'to Y0' output from the latch circuit 31C are the latch circuit 31.
It is supplied to the data terminal D of D. 1-bit data C output from the latch circuit 31C (any one of C5 to C1)
Is supplied to the data terminal D of the latch circuit 31E.

The latch circuits 31D and 31E have 275f.
A latch pulse P6 having a frequency of h is supplied (F in the same figure). As a result, 275 fh from the latch circuit 31D
The 7-bit luminance signal Y'is output at the data rate of (7) (G in the figure), and the 5-bit color signal C (data rate of 55 fh) is output from the latch circuit 31E as serial data (H in the figure).

The luminance signal Y'output from the latch circuit 31D is output via the phase adjuster 31F. The control signal CNP is supplied to the phase adjuster 31F based on the data AXB included in the information data INF, and the phase adjustment of the sample data of the luminance signal Y ′ in each horizontal period is performed. As a result, the data of each line of the luminance signal Y'is output while maintaining the phase relationship of the line offset.

Returning to FIG. 2, the information data INF output from the demultiplexer 31 is supplied to the synchronization generator 26 and the timing generator 32.

The luminance signal Y'output from the demultiplexer 31 is supplied to the filter circuit 33 and the fixed terminal on the side a of the changeover switch 34. The changeover switch 34 is supplied with the changeover control signal SW7 from the timing generator 32. The output signal of the changeover switch 34 is 1
It is supplied to the delay circuit 35 having a delay time of the horizontal period. The output signal of the delay circuit 35 is supplied to the filter circuit 33 and the fixed terminal on the b side of the changeover switch 34. The filter circuit 33 includes a timing generator 32.
The switching control signal SW8 is supplied.

FIG. 14 shows a specific structure of the filter circuit 33, the changeover switch 34 and the delay circuit 35, which is a processing circuit for the line offset sub-sampled luminance signal Y '.

Here, the signal of the line sampled at a certain phase is the line signal of the A pattern, and the signal of the line sampled at its inverted phase is the line signal of the B pattern. These patterns are identified by the data AXB included in the information data INF as described above.

In the figure, the input signal Sin (luminance signal Y ') is supplied to a high-pass filter 33A which constitutes the filter circuit 33, and the high-frequency component SH of the signal Sin extracted by this high-pass filter 33A is subtracted by a subtractor 33B and It is supplied to the fixed terminal on the side a of the changeover switch 33C.

Further, the input signal Sin is supplied to the subtractor 33B via the delay circuit 33D for time adjustment. The delay time of the delay circuit 33D is set to be equal to the delay amount in the high pass filter 33A.

In the subtractor 33B, the high frequency component SH extracted by the high pass filter 33A is subtracted from the video signal Sin output from the delay circuit 33D, and the low frequency component SL of the signal Sin is subtracted.
Is output.

Further, the input signal Sin is supplied to the fixed terminal on the a side of the changeover switch 34, the output signal of this changeover switch 34 is supplied to the delay circuit 35, and the output signal of the delay circuit 35 is on the b side of the changeover switch 34. Supplied to the fixed terminal of. The changeover switch 34 is changed over by the changeover control signal SW7.
Based on. That is, the changeover switch 34
Is a line signal of A pattern or B pattern is continuously supplied as the input signal Sin for two or more lines,
Each horizontal period from the first line of the continuous lines to the line immediately before the last line is connected to the b side, and the other horizontal periods are connected to the a side.

Here, the line signal of the A pattern or the B pattern continues for two or more lines in some cases by increasing the number of lines by double reading in the line number conversion or by decreasing the number of lines by thinning. In this example, when the signals of the 625/50 system are loaded into the memories 23A and 23B, vertical compression / expansion processing is performed due to the storage capacity. Even with this compression / expansion processing, signals of the same pattern continue for two lines or more. Sometimes.

Whether or not the same pattern continues for two or more lines is determined by the data AXB included in the information data INF separated by the demultiplexer 31.

The signal Sin 'of one horizontal period before output from the delay circuit 35 is supplied to the high pass filter 33E, and the high frequency component S extracted by the high pass filter 33E.
H'is supplied to the fixed terminal on the b side of the changeover switch 33C. The high frequency component SH2 selected and output by the changeover switch 33C is supplied to the adder 33F.

The changeover switch 33C is set to 1 based on the changeover control signal SW8 supplied from the timing generator 32.
It is alternately switched to the a side and the b side by changing the / 2 sampling cycle. In this case, the high pass filter 33
It is connected to the a side in correspondence with the sampling timing of the high frequency component SH output from A. The sampling timing of the high frequency component SH is determined by the data AXB included in the information data INF separated by the demultiplexer 31.

The low frequency component SL of the signal Sin output from the subtractor 33B is supplied to the adder 33G and the fixed terminal on the side a of the changeover switch 33H.

The high frequency component SH 'of the signal Sin' output from the high pass filter 33E is supplied to the subtractor 33I,
The signal Sin 'output from the delay circuit 35 is supplied to the subtractor 33I via the delay circuit 33J for time adjustment. The delay time of the delay circuit 33J is equal to the high pass filter 3
It is set to be equal to the delay amount in 3E.

In the subtractor 33I, the high frequency component SH 'output from the high pass filter 33E is subtracted from the signal Sin' output from the delay circuit 33J. The low frequency component SL 'of the signal Sin' is output from the subtractor 33I, and this low frequency component SL 'is supplied to the adder 33G.

In the adder 33G, the video signals Sin and Si
The low frequency components SL and SL 'of n'are added and averaged, and the output signal (SL + SL') / 2 is supplied to the fixed terminal on the b side of the changeover switch 33H.

The low frequency component selected by the changeover switch 33H is supplied to the adder 33F and is added to the high frequency component SH 'selected by the changeover switch 33C. And adder 3
The output signal of 3F is the output signal Sout of the filter circuit 33.
(Y ″).

In the above structure, first the changeover switch 3
A case where 3H is connected to the a side will be described. Signal S
When the line signals of the A pattern and the B pattern are alternately supplied as in (see FIG. 15), it becomes as follows.

When the signal Sin is an n-1 line signal, the signal Sin 'output from the delay circuit 35 is an n-2 line signal. From the changeover switch 33C, n-1
A high-frequency component SH2 in which the high-frequency component SH of the line signal and the high-frequency component SH 'of the signal of the n-2 line are alternately selected with a 1/2 sampling period is output. The signal Sout on the output line becomes an addition signal of the high frequency component SH2 and the low frequency component SL of the signal on the n-1 line (see FIG. 16A). When the signal Sin is an n-line signal, the signal Sin 'output from the delay circuit 35 is an n-1 line signal. From the change-over switch 33C, the high frequency component S of the n-line signal is output.
A high-frequency component SH2 is output in which H and the high-frequency component SH 'of the signal of the n-1 line are alternately selected at a 1/2 sampling period. The signal Sout on the output line becomes an addition signal of the high-frequency component SH2 and the low-frequency component SL of the n-line signal (see FIG. 16B).

As described above, the high frequency component SH2 included in the signal Sout is sampled at a sampling cycle of substantially 1/2, and the high frequency range is improved.

When the line signals of the same pattern are continuously supplied as the signal Sin (see FIG. 17), the following occurs.

For example, as shown in FIG. 17, when the n-1 line and the n line continuously form a B pattern line signal, the line signals of the same pattern continue in the n-1 line and the n line. Therefore, the changeover switch 34 is connected to the b side during the horizontal period in which the signal of the n-1 line is supplied. Therefore, during the two horizontal periods in which the signals of the n−1 line and the n line are supplied, the delay circuit 35 outputs n−
The signals of two lines are continuously output.

Therefore, as the signal Sin, n-2 to n +
When signals of two lines are supplied (see FIG. 17), the delay circuit 35 outputs signals of lines n−3 to n−1 as signals Sin ′ (see FIG. 18), and signals Sin and The patterns of the Sin 'line signals are different from each other.

Therefore, the sampling timings of the high frequency components SH and SH 'output from the high pass filters 33A and 33E are always alternating, and the changeover switch 33
From C, the high frequency component SH2 sampled at substantially 1/2 sampling period is obtained.

When the signal Sin is the signal of the n-1 line (B pattern), the signal Si output from the delay circuit 35.
n'becomes a signal (A pattern) on the n-2 line. From the changeover switch 33C, the high frequency component SH2 of the signal of the n-1 line and the high frequency component SH 'of the signal of the n-2 line are alternately selected at a 1/2 sampling period.
Is output. The signal Sout on the output line is a signal obtained by adding the high frequency component SH2 and the low frequency component SL of the signal on the n-1 line (see FIG. 19A).

Signal Sin is an n-line signal (B pattern)
Also, the signal Sin ′ output from the delay circuit 35
Is a signal (A pattern) of the n-2 line. From the change-over switch 33C, the high frequency components SH and n
The high frequency component SH2, which is alternately selected with the high frequency component SH 'of the -2 line signal at a 1/2 sampling period, is output. The signal Sout on the output line is the high frequency component SH2.
And the low-frequency component SL of the signal of the n line is added (see FIG. 19B).

Thus, even when the line signals having the same pattern are continuously supplied as the signal Sin, the changeover switch 33C outputs the high frequency component SH2 sampled at a substantially 1/2 sampling period. , The improved signal Sout in the high frequency range can be obtained.

Next, the case where the changeover switch 33H is connected to the b side will be described. The high frequency component is the same as the case where the changeover switch 33H is connected to the side a, and the description thereof will be omitted.

Regarding the low frequency component, the low frequency components SL and SL 'of the signals Sin and Sin' are arithmetically averaged by the adder 33G, and the arithmetically averaged low frequency component (SL + SL ') / 2.
Is supplied to the adder 33F through the b side of the changeover switch 33H.

Therefore, the signal Sout output from the adder 33F is the sum of the low frequency component (SL + SL ') / 2 and the high frequency component SH2.

When the signal Sin is the n-1 line signal, the signal Sin 'output from the delay circuit 35 is the n-2 line signal. From the changeover switch 33C, n-1
A high frequency component SH2 in which the high frequency component SH of the line signal and the high frequency component SH 'of the n-2 line are alternately selected in a 1/2 sampling cycle is output. Also, the adder 33F
Outputs a low-frequency component (SL + SL ') / 2 obtained by adding and averaging the low-frequency component SL of the n-1 line signal and the low-frequency component SL' of the n-2 line signal. Output signal Sout
Is a signal obtained by adding the high frequency component SH2 and the low frequency component (SL + SL ') / 2 (see FIG. 20A).

When the signal Sin is an n-line signal, the signal Sin 'output from the delay circuit 35 is an n-2 line signal. From the change-over switch 33C, the high frequency component SH of the n-line signal and the high frequency component SH 'of the n-2 line are 1
The high frequency component SH2, which is alternately selected in the / 2 sampling cycle, is output. From the adder 33F, the low-frequency component SL of the n-line signal and the low-frequency component SL 'of the n-2 line signal are added and averaged to obtain the low-frequency component (SL + SL').
/ 2 is output. The output signal Sout is the high frequency component SH.
2 and the low frequency component (SL + SL ') / 2 are added (see FIG. 20B).

Thus, the high frequency component of the output signal Sout is SH
Since it is 2, the high frequency band is improved, and the low frequency band component is (SL + SL ') / 2, and the signal is averaged in the vertical direction to improve the jaggedness.

Note that the averaging of signals in the vertical direction generally deteriorates the resolution in the vertical direction. Therefore, in the example of FIG. 14, the changeover switch 33 is used only when the number of lines increases due to the double reading, and the crease becomes a problem.
It is effective to connect H to the b side.

Returning to FIG. 2, the luminance signal Y ″ of the 8-bit parallel data output from the filter circuit 33 is supplied to the fixed terminal on the side a of the changeover switch 36. 37 indicates signals of the pedestal level and the synchronization level. The signal generator 37 is supplied with the timing signal ST1 for generating the respective signals from the synchronization generator 26. The output signal of the signal generator 37 is the changeover switch 36.
Is supplied to the fixed terminal on the side b.

The changeover switch 36 is supplied with a changeover control signal SW9 from the synchronization generator 26. The changeover switch 36 is connected to the b side during the period of the sync signal and the pedestal signal, and is connected to the a side during the other periods. Therefore, the changeover switch 36 outputs the added luminance signal such as the synchronizing signal.

The luminance signal output from the change-over switch 36 is converted into an analog signal by the D / A converter 38, then band-limited by the low-pass filter 39 and supplied to the adder 40.

The color signal C of 1-bit serial data separated by the demultiplexer 31 is supplied to the serial / parallel converter (S / P converter) 41. The S / P converter 41 is supplied with the clock CLK3 synchronized with each bit data of the color signal C from the timing generator 32, and also with the latch pulse P7 at the timing of every 5 bits (C5 to C1).

The color signal C converted into 5-bit parallel data by the S / P converter 41 is supplied to the fixed terminals on the side a of the changeover switches 42 and 43, and at the same time, the changeover switch 44.
Is supplied to the fixed terminal on the side b.

The output signal of the changeover switch 42 is supplied to the delay circuit 45 having a delay time of one horizontal period, and the output signal of the delay circuit 45 is supplied to the fixed terminal on the b side of the changeover switch 42. The changeover switch 42 is supplied with the changeover control signal SW10 from the timing generator 32.

As described above, the color signal C before conversion of the number of lines by writing / reading to / from the memories 23A and 23B is a line-sequential signal which becomes the V signal and the U signal every horizontal period, but the number of lines is converted. The color signal C after being processed becomes a line in which two lines of the same color are periodically continuous by thinning or double reading.

The changeover switch 42 has a changeover control signal SW10.
The first line of two consecutive lines is switched to the b side, and the other periods are connected to the a side. The switching control signal SW10 is formed, for example, based on the data LDEC included in the information data INF separated by the demultiplexer 31 when lines are thinned out at the time of writing, and when the same line is read twice at the time of reading. , Based on that information.

The output signal of the delay circuit 45 is the changeover switch 4
3 is supplied to the fixed terminal on the b side and also to the fixed terminal on the a side of the changeover switch 44. Changeover switch 4
The switching control signal S from the timing generator 32 is supplied to the switches 3 and 44.
W11 is supplied. The changeover switches 43 and 44 are S /
One horizontal period in which the color signal C from the P converter 41 is the U signal is connected to the a side, and conversely, one horizontal period in which the color signal C is the V signal is connected to the b side. The switching control signal SW11 is formed based on the data UXV included in the information data INF separated by the demultiplexer 31.

Here, a case will be described in which the same line is read twice at a ratio of one line to five lines and the number of lines is increased. At this time, as shown in FIG. 21A, the line of the same color is periodically output from the S / P converter 41.
A line-continuous color signal C is output.

At this time, the switching control signals SW10 and SW1
1 is formed as shown in FIGS. Therefore, the output signal of the delay circuit 45 becomes as shown in D of the same figure, and the synchronized U signal and V signal are respectively obtained from the changeover switches 43 and 44 (shown in E and F of the same figure).

Although not described, the number of lines is reduced by thinning out one line with respect to six lines.
Even when the S / P converter 41 outputs a color signal C in which two lines of the same color are cyclically continuous, the changeover switches 43 and 44 similarly similarly synchronize the synchronized U signal and V signal, respectively. The signal is obtained.

The U signal output from the changeover switch 43 is supplied to the fixed terminal on the a side of the changeover switch 46. 47
Is a signal generator for generating burst level and blanking level signals. The signal generator 47 is supplied with the timing signal ST2 for generating the respective signals from the synchronization generator 26. The output signal of the signal generator 47 is supplied to the fixed terminal on the b side of the changeover switch 46.

Further, V output from the changeover switch 44
The signal is supplied to the fixed terminal on the a side of the changeover switch 48. 49 is a signal generator for generating burst level and blanking level signals. The signal generator 49 is supplied with the timing signal ST2 for generating the respective signals from the synchronization generator 26. The output signal of the signal generator 49 is supplied to the fixed terminal on the b side of the changeover switch 48.

The changeover switches 46 and 48 include the synchronization generator 2
The switching control signal SW12 is supplied from the switch 6. The changeover switches 46 and 48 are connected to the b side during the burst period and the blanking period, and are connected to the a side during the other periods. Therefore, the changeover switches 46 and 48 output the U and V signals to which the burst level signal and the like have been added.

U output from changeover switches 46 and 48
The signal and the V signal are supplied to the color modulator 50. Color modulator 5
At 0, the color subcarrier of 4.43 MHz is used when converting from the NTSC system to the PAL system, while the color subcarrier of 3.58 MHz is used when converting from the PAL system to the NTSC system.

The carrier color signal of 6-bit parallel data output from the color modulator 50 is converted into an analog signal by the D / A converter 51, and then supplied to the adder 40 via the bandpass filter 52. .. Then, the adder 40 adds the luminance signal and the carrier color signal, and the format-converted video signal SV is derived at the output terminal 53.

In this example, the memories 23A and 23B are alternately controlled to be in the write state and the read state for every 1/2 horizontal period to convert the number of lines and the number of fields. Therefore, a general-purpose 256K-bit DRAM can be used as each of the memories 23A and 23B, and a method conversion device that also performs line / field conversion can be inexpensively configured.

In this example, the line offset subsampling process is performed on the luminance signal Y'on the writing side and the changeover switch 34, on the reading side in order to reduce the data rate and save the capacity of the memories 23A and 23B.
The delay circuit 35 and the filter circuit 33 are used to alternately select the high frequency components of the signal of the current line and the signal one line before with a 1/2 sampling period to improve the high frequency. Even when the line signals of the same pattern continue due to the repeated reading, the first and second patterns are alternately selected, and the high frequency band can be improved satisfactorily.

Further, in the present example, the memories 23A, 2
In order to save the capacity of 3B, the U signal and the V signal are line-sequentially written and read, and they are synchronized by using the changeover switches 42 to 44 and the delay circuit 45 on the read side. Even when the line signals of the same color are continuous by thinning or double reading, the synchronization can be favorably performed.

Next, referring to FIGS. 22 and 23, the synchronous system on the write side and the read side of the memories 23A and 23B will be described in detail. The writing side synchronization system is A
In the FC circuit 8, the synchronization system on the read side is configured in the synchronization generator 26 (see FIGS. 1 and 2).

In FIG. 22, the composite synchronizing signal CSYNC supplied to the input terminal 61 is supplied to the falling edge detector 63 via the buffer 62. Edge detector 6
The synchronization pulse CSYNCP output from the circuit 3 is supplied to the input side of the connection switch 64.

The synchronization pulse CSYNCP obtained at the output side of the connection switch 64 is supplied to the input side of the OR gate 65. The output signal of the OR gate 65 is supplied to the load terminal LO of the 10-bit binary up counter (write side horizontal counter) 66. The load data of the counter 66 is “1 DAH”. Here, “H” indicates that it is a hexadecimal number, and the same applies below.

1 is applied to the clock terminal CK of the counter 66.
A system clock CLK having a frequency of 100 fh is supplied. 1 obtained at the Q9 to Q0 terminals of the counter 66
0-bit count data is 11-bit decoder 67
Is supplied to the data terminal D of.

The synchronizing pulse CSYNCP obtained at the output side of the connection switch 64 is supplied to the input side of the OR gate 68. The output signal of the OR gate 68 is the inverter 6
It is supplied to the data terminal D of the D flip-flop 70 via 9. The signal S1 obtained at the Q terminal of the flip-flop 70 is supplied to the input side of the OR gate 68, and
The 10-bit count data of the counter 66 is supplied to the data terminal D of the decoder 67 in parallel.

From the decoder 67, the signal S1 is "1",
The count data is "3FF regardless of whether it is" 0 ".
When the signal S1 becomes "H", the signal S2 which becomes "1" is outputted, when the signal S1 becomes "1" and the count data becomes "34FH", the write horizontal start signal WHS which becomes "1" is outputted, and further the signal S1 becomes When "0", the count data is "3
The signal HMDP which becomes "1" when it becomes "FFH" is output. Here, "1" and "0" indicate logic levels, and the same applies to the following.

The signal S output from the decoder 67
2 is supplied to the input side of the OR gates 65 and 72 via the connection switch 71. The synchronization pulse CSYNCP obtained at the output side of the connection switch 64 is supplied to the flip-flop 73, and is made to have a pulse width (“1” period) of two clocks of the system clock CLK (frequency of 1100 fh). It is supplied to the connection switch 71 as an on / off control signal. The connection switch 71 is turned off during the pulse width period of 2 clocks and turned on during the other periods.

The synchronizing pulse CSYNCP obtained at the output side of the connection switch 64 is supplied to the input side of the OR gate 72 via the connection switch 74. The connection switch 74 has a signal S1 obtained at the Q terminal of the flip-flop 70.
Is supplied as an on / off control signal. Connection switch 7
4 is turned off when the signal S1 is "0" and is "1".
Is turned on. The output signal of the OR gate 72 is supplied to the enable input terminal EN of the flip-flop 70. The flip-flop 70 transmits the data of the input D terminal to the output terminal in synchronization with the system clock CLK only while the enable input terminal is "1".

The composite synchronizing signal CSYNC supplied to the input terminal 61 is also supplied to the integrator 75. Integrator 75
Is output to the rising edge detector 77 via the buffer 76. A vertical synchronizing pulse VP is output from the edge detector 77 when the integrated output exceeds the threshold value Vth, and this synchronizing pulse VP is a load terminal L of a 4-bit binary up counter (writing side vertical counter) 78.
Supplied to O. The load data of the counter 78 is “3
H ”. A signal obtained at the Q8 terminal of the counter 66 is supplied to the enable input terminal EN of the counter 78 via the falling edge detector 79. Counter 78
Counts up with the system clock CLK only when the enable input terminal EN is "1". Since the output of the edge detector 79 is only within one clock, the count is incremented by one each time an edge pulse from the Q8 terminal arrives.

4 obtained at terminals Q3 to Q0 of counter 78
The bit count data is supplied to the data terminal D of the 4-bit decoder 80. The decoder 80 outputs a signal S3 that becomes "1" when the count data becomes "AH" and "BH", and the count data becomes "D".
When it becomes "H", the signal S4 which becomes "1" is output.

The signal S3 output from the decoder 80 is supplied to the connection switch 64 as an on / off control signal.
The connection switch 64 is turned on when the signal S3 is "1", and turned off during other periods. That is, in the connection switch 64, the count data of the counter 78 is “A
It becomes "H" and "BH", and is turned on only for about 1 horizontal period in the period in which there is no serration pulse or equivalent pulse in the vertical synchronization period.

The signal S4 output from the decoder 80 is supplied to the input side of the AND gate 81. AND gate 8
The output signal of the OR gate 72 is also supplied to 1. The output signal of the AND gate 81 is the write vertical start signal WV.
It is output as S.

In FIG. 23, the signal HMDP output from the decoder 67 is supplied to the input side of the OR gate 82. The output signal of the OR gate 82 is supplied to the load terminal LO of the 10-bit binary up counter (readout side horizontal counter) 83. The load data of the counter 83 is set to "1 DAH". The system clock CLK is supplied to the clock terminal CK of the counter 83.

1 obtained at the Q9 to Q0 terminals of the counter 83
When the 0-bit count data is "3FFH",
The carry signal of "1" is output from the CO terminal of the counter 83. The carry signal is supplied to the input side of the OR gate 82 and the input side of the OR gate 88.

The signal HMDP is supplied to the input side of the OR gate 85. The output signal of the OR gate 85 is supplied to the data terminal D1 of the D flip-flop 87 via the inverter 86. The signal S5 obtained at the Q1 terminal of the flip-flop 87 is supplied to the input side of the OR gate 85 and is also supplied to the data terminal D of the decoder 84 in parallel with the count data of the counter 83. Decoder 84
From, the signal S5 is "1" and the count data is "369".
When it becomes "H", the read horizontal start signal RHS which becomes "1" is output.

The signal HMDP is supplied to the input side of the OR gate 88 via the connection switch 89. A signal S5 obtained at the Q1 terminal of the flip-flop 87 is supplied to the connection switch 89 as an on / off control signal. The connection switch 89 is turned off when the signal S5 is "0" and turned on when the signal S5 is "1".

The output signal of the OR gate 88 is connected to the enable input terminal EN of the flip-flop 87 and the 10-bit binary up counter (reading vertical counter) 90.
Is supplied to the input side of the OR gate 92 via the connection switch 91. The output signal of the OR gate 92 is supplied to the load terminal LO of the counter 90.

To the select terminal SEL of the counter 90,
The read control signal R525 is supplied from the input terminal 95. The read control signal R525 is 525/60 system (N
It is set to "1" when outputting the TSC system) and set to "0" when outputting the 625/50 system (PAL system). The load data of the counter 90 is "1F3H" when the read control signal R525 is "1", and "18FH" when it is "0".

1 obtained at the Q9 to Q0 terminals of the counter 90
When the 0-bit count data is "3FFH",
A carry signal is output to the CO terminal of the counter 90,
This carry signal is supplied to the data terminal D2 of the flip-flop 87. The signal obtained at the Q2 terminal of the flip-flop 87 is supplied to the input side of the OR gate 92 via the rising edge detector 94.

The count data of the counter 90 is supplied to the data terminal D of the 10-bit decoder 93. The decoder 93 outputs a signal S6 which is "1" when the count data is "3E6H" and "3E7H", and a read vertical start signal RVS which is "1" when the count data is "3FFH". To be done.

The signal S6 output from the decoder 93 is supplied to the connection switch 91 as an on / off control signal.
The connection switch 91 is turned on when the signal S6 is "1" and turned off when the signal S6 is "0".

Control of the flip-flops 70 and 87 and the binary up counters 78 and 90 is enabled by the input terminal E.
The reason why N is used is to operate them in synchronization with the system clock CLK completely. By doing so, it becomes almost unnecessary to consider the influence of the propagation delay time of elements such as gates. This is a basic LSI design technique.

In the above configuration, the operation of the horizontal synchronizing system will be described first.

A composite sync signal CSY as shown in FIG. 24B.
Consider a case where NC is supplied to the input terminal 61 and the edge detector 63 outputs the synchronization pulse CSYNCP as shown in FIG. Then, the connection switch 64 is turned on when the synchronization pulse CSYNCP is t1 based on a signal S3 output from the decoder 80, as will be described later.
It shall be controlled to be turned off at the time point of 2. FIG. 9A shows the system clock CLK.

The synchronization pulse CSYNCP at the time of t1 is supplied to the load terminal LO of the counter 66 via the connection switch 64 and the OR gate 65 (FIG. D), and the counter 66 is loaded with the data of “1 DAH” (FIG. E).

Further, the synchronization pulse CSYNC at time t1
P is supplied to the OR gate 68 via the connection switch 64, the signal "0" is supplied to the data terminal D of the flip-flop 70 (H in the figure), and the synchronization pulse C
Since SYNCP is supplied to the enable input terminal EN of the flip-flop 70 through the connection switches 64 and 74 and the OR gate 72 (I in the same figure), the flip-flop 70 is loaded at the time when the data of “1 DAH” is loaded into the counter 66. The signal S1 obtained at the Q terminal of is "0" (J in the same figure).

The counter 66 is sequentially incremented by the system clock CLK (E in the figure). The count data of the counter 66 after being counted 550 is “3FF
When it becomes "H", the output signal S2 of the decoder 67 becomes "1" (G in the figure). Since this signal S2 is supplied to the load terminal LO of the counter 66 via the OR gate 65, the data of "1 DAH" is loaded in the counter 66 (E in the figure).

Since this signal S2 is supplied to the enable input terminal EN of the flip-flop 70 via the OR gate 72 (I in the same figure), the counter 66 outputs "1DA".
When the data of "H" is loaded, the signal S1 obtained at the Q terminal of the flip-flop 70 becomes "1" (J in the same figure).

In the same way, the counter 66 similarly outputs "1DAH" to "3F" in the first half and the second half of each horizontal period.
The counting operation up to "FH" is repeated (E in the figure), and at the same time, the signal S obtained at the Q terminal of the flip-flop 70 is obtained.
1 becomes "0" in the first half of each horizontal period and becomes "1" in the latter half thereof (J in the same figure).

Accordingly, the signal S is output from the decoder 67.
When 1 is “1” and the count data of the counter 66 is “34F
The write horizontal start signal WHS is output each time it becomes "H", and the signal HMDP is output each time the signal S1 is "0" and the count data of the counter 66 is "3FFH" (M in the figure). This signal HMDP has a shift of 1/2 horizontal period from the horizontal synchronization of the composite synchronization signal CSYNC.

The connection switch 64 is turned on in one horizontal period in which the count data of the counter 78 is "AH" and "BH", and only the synchronization pulse CSYNCP output from the edge detector 63 during that period is connected switch 64 and. Load terminal L of counter 66 via OR gate 65
It is supplied to O and the data of "1 DAH" is loaded into the counter 66. This establishes synchronization with the horizontal synchronization of the composite synchronization signal CSYNC.

As described above, except when the data of "1 DAH" is loaded into the counter 66 based on the synchronization pulse CSYNCP, the counter 66 is set to "1 DAH" based on the signal S2 output from the decoder 67 as described above. The data is loaded and the counter 66 is in the state of self reset.

Even if not mentioned above, the generator of the system clock CLK having the frequency of 1100 fh is constructed as shown in FIG. The composite synchronizing signal CSYNC and the signal S2 are compared by the phase comparator 201, and the comparison error signal is VCO2.
02 as a control signal. As a result, even in the self-reset state, the frequency itself of the system clock CLK is controlled, and the synchronization with the horizontal synchronization of the composite synchronization signal CSYNC is maintained.

As described above, the connection switch 64 is turned on, and the synchronization pulse CSY is used for load control of the counter 66 and the like.
When the NCP is used, the output signal of the flip-flop 73 becomes "1" (Fig. 24F), and the connection switch 71
Is turned off, the signal S output from the decoder 67 is output.
The use of 2 is blocked.

The synchronizing pulse CSYNCP cannot be supplied to the OR gate 72 in the period in which the signal S1 obtained at the Q terminal of the flip-flop 70 is "0", that is, in the first half of the horizontal period. Since the connection switch 74 is turned off during this period, the influence of noise is prevented.

The signal obtained at the Q8 terminal of the counter 66 is as shown in FIG. 24K, and a signal which becomes "1" when the count data of the counter 66 becomes "295H" is obtained from the edge detector 79. It is supplied to the enable input terminal EN of the counter 78 (L in the figure).

The signal H output from the decoder 67
The MDP (M in the figure) is a counter 8 via an OR gate 82.
3 is supplied to the load terminal LO (N in the figure) and the counter 8
The data of "1 DAH" is loaded into 3 (O in the figure).

Further, the signal HMDP is supplied to the OR gate 85 and the signal "0" is supplied to the data terminal D1 of the flip-flop 87 (Q in the same figure), and this signal HMDP also connects the connection switch 89 and the OR gate 88. Since it is supplied to the enable input terminal EN of the flip-flop 87 (R in the figure) via the counter 83, “1DA
At the time when the "H" data is loaded, the signal S5 obtained at the Q1 terminal of the flip-flop 87 becomes "0" (S in the figure).

The counter 83 is sequentially incremented by the system clock CLK (O in the figure). 550 are counted and the count data of the counter 83 is “3FF
When it becomes “H”, a carry signal is output to its CO terminal (P in the same figure), and this carry signal is supplied to the load terminal LO of the counter 83 via the OR gate 82 (N in the same figure) and “1 DAH Data is loaded.

The carry signal output from the counter 83 is transferred to the flip-flop 87 via the OR gate 88.
Since the signal is supplied to the enable input terminal EN (R in the figure), the signal S5 obtained at the Q1 terminal becomes "1" (S in the figure).

Thereafter, similarly, the counter 83 outputs the signal H
The counting operation from "1 DAH" to "3 FFH" is repeated in the first half and the second half of each cycle (one horizontal period) of the MDP (O in the figure), and Q1 of the flip-flop 87 is also used.
The signal S5 obtained at the terminal becomes "0" in the first half of each cycle and becomes "1" in the latter half thereof (S in the same figure).

As a result, the signal S is output from the decoder 84.
5 is “1” and the count data of the counter 83 is “369
The read horizontal start signal RHS is output every time when it becomes “H”.

The signal HMDP cannot be supplied to the OR gate 88 in the period in which the signal S5 obtained at the Q1 terminal of the flip-flop 87 is "0", that is, in the first half of each cycle of the signal HMDP. Connection switch 89 during this period
Is turned off, the influence of noise is prevented.

Next, the operation of the vertical synchronization system (odd field) will be described.

When the composite synchronizing signal CSYNC is supplied to the input terminal 61 as shown in FIG. 25A, the output signal of the integrator 75 becomes as shown in FIG. When the level of the integrated output exceeds the threshold value Vth, the edge detector 77 outputs the vertical synchronizing pulse VP, and the counter 78 has a load terminal LO.
(C in the same figure).

The counter 7 is activated at the timing of the synchronization pulse VP.
The data of "3H" is loaded into 8 (E in the figure). The output signal of the edge detector 79 is supplied to the enable input terminal EN of the counter 78 (D in the figure), and the counter 78 is sequentially incremented (E in the figure).

The count data of the counter 78 is "AH".
And "BH", the signal S3 output from the decoder 80 becomes "1" (F in the figure), the connection switch 64 is turned on as described above, and the synchronization pulse CSYNC is generated.
P is taken in, and the counting operation of the counter 66 is synchronized with the horizontal synchronization of the composite synchronization signal CSYNC (G in the same figure).

When the count data of the counter 78 becomes "DH", the signal S4 output from the decoder 80 becomes "1" (J in the same figure), and the output signal of the OR gate 72 corresponding to this period (see the same figure). I) is AND gate 81
Is output as the write vertical start signal WVS (K in the same figure). When the counter 78 counts up to "FH", the counter 78 stops itself and waits for the next load.

As described above, the counting operation of the counter 83 is performed in synchronization with the signal HMDP (H in the figure) output from the decoder 67 (L in the figure), and the output signal of the OR gate 88 is as shown in M in the figure. become.

The counter 90 is sequentially incremented by the output signal of the OR gate 88. When the count data of the counter 90 is "3E6H" and "3E7H", the output signal S6 of the decoder 93 becomes "1" (N in the same figure), and the connection switch 91 is turned on during this period to output the output signal of the OR gate 88. It is supplied to the load terminal LO of the counter 90 via the connection switch 91 and the OR gate 92. Then, the initial data is loaded into the counter 90. Initial data read is 525/60 series (NT
It is set to "1F3H" when it is the SC system) and "18FH" when it is the 625/50 system (PAL system) (O in the same figure).

The count data of the counter 90 is "3FF
When it becomes "H", a carry signal is output to its CO terminal (P in the same figure), and this carry signal is applied to the flip-flop 8
7 to the data terminal D2. Therefore, the output signal of the edge detector 94 becomes as shown in Q in the same figure, and this is the load terminal LO of the counter 90 via the OR gate 92.
And the initial data is loaded into the counter 90.

As a result, the counter 90 repeats the counting operation from the initial data to "3FFH".
In this case, the count data becomes “3FFH”
When the reading is the 525/60 system, it is the 525th count since the initial data was loaded, while when the reading is the 625/50 system, it is the 625th count after the initial data was loaded. The read vertical start signal RVS is output from the decoder 93 every time the count data of the counter 90 becomes "3FFH" (R in the same figure).

The operation of the vertical synchronizing system in the even field is performed by the count data of the counter 78 and the composite synchronizing signal CS.
The relationship with YNC horizontal synchronization is only shifted by 1/2 horizontal period, and other relationships are the same as in the case of the odd field described above. The signals corresponding to FIGS. 25A to 25G are shown in FIGS.

Incidentally, in order to simplify the explanation, FIG.
In FIG. 26A, N is set as the composite synchronization signal CSYNC.
The TSC system is shown. In the PAL system, the number of serration pulses and equivalent pulses is different, but the operation is similar.

By the way, in the example of FIGS. 1 and 2 described above, the phase difference between the writing and reading of the memories 23A and 23B is set to 1/2 horizontal period (actually, in order to secure the first access time in the page mode, In order to keep the deviation for several clocks), the following is required.

(A) The horizontal synchronizing cycle of the input video signal is constant.

(B) The write address signal and the read address signal must be synchronized (it is not necessary to keep constant, it is important to keep the phase difference constant), and the same clock is used.

Regarding (a), the horizontal synchronizing signal of the video signal output from the video signal generator, tuner, LD player, etc. is accurate. Also, for consumer VTRs,
The deviation of the horizontal sync signal depends only on the jitter performance of the VTR only for self-recording and reproduction, and in many cases, 0.1 μs (10
0 ns). With this level, the memory 23
On A and 23B, the fluctuation is only about 1 data, and there is a slight margin in the memory capacity and in the horizontal direction, so that even if it shifts, it does not hinder the operation.

However, when a tape recorded by another VTR is reproduced by another VTR, the horizontal sync signal is deviated every vertical period due to the accuracy of the mounting angle of the head chip on the rotary head of the VTR. Occurs.

That is, the tape on which the horizontal synchronizing signal is recorded exactly every horizontal period (1H) is reproduced by the heads HA and HB attached at the angular intervals of exactly 180 ° as shown in FIG. In this case, 1H is maintained as the horizontal synchronization period at the switching points of the heads HA and HB (FIG. 29A).

However, as shown in FIG. 28, the head HA
When reproducing with a head HC that is not attached at an angular interval of 180 ° with this head HA, the head H
The horizontal synchronization cycle at the switching points of A and HC is 1H '(≠ 1H) (Fig. 29B).

If this amount of deviation exceeds the horizontal margin of the memories 23A and 23B, the write and read operations will overlap in the same memory, resulting in a failure of the operation.

As for (b), when a large deviation occurs in the horizontal synchronization cycle at the head switching point as described above, the AFC operation for generating a clock synchronized with the input video signal, that is, the clock Distortion (skew) occurs in the frequency.

FIG. 30 schematically shows the manner of system conversion. The vertical synchronizing position of the output screen with respect to the input screen is on a cylinder rotating at a field ratio of 50:60. It can be seen that when the clock is shared between the input and output, the clock skew is immediately transmitted to the output side, and the skew originally at the lower end of the input screen moves across the screen as the output screen cylinder rotates.

FIGS. 31 and 32 are block diagrams of a synchronization system in which the output screen is not skewed even if the horizontal synchronization cycle of the input video signal is largely deviated. In these figures, the parts corresponding to FIG. 22 and FIG.
The same reference numerals are given and detailed description thereof is omitted.

In this example, the signal HMDP output from the decoder 67 is supplied to the input side of the OR gate 82 via the connection switch 101.

From the decoder 80, signals S3 and S
In addition to 4, the signal S7 is "1" when the count data of the counter 78 is "BH" and "CH", and the signal S1 is "1" when the count data is "EH". S8 is output. From the decoder 84, “1” when the count data of the counter 83 becomes “300H” in addition to the read horizontal start signal RHS.
Then, the signal S9 is output.

The signal S7 output from the decoder 80 is D
It is supplied to the data terminal D of the flip-flop 102.
The signal S9 output from the decoder 84 is supplied to the enable input terminal EN of the flip-flop 102, and the signal S10 obtained at its Q terminal is a of the changeover switch 103.
Side fixed terminal. The enable input terminal EN of the flip-flop 102 is provided to operate in synchronization with the system clock CLK, like the flip-flops 70 and 87 so far. The fixed terminal on the b side of the changeover switch 103 is supplied with the signal S6 output from the decoder 93.

The output signal S11 of the changeover switch 103 is supplied to the connection switch 101 as an on / off control signal. The connection switch 101 is turned on when the signal S11 is "1" and turned off when the signal S11 is "0".

Also, the signal S output from the decoder 80
8 is supplied as an on / off control signal to the connection switch 91 via the connection switch 104. Connection switch 91
Is turned on when the signal S8 is "1" and is "0".
Is turned off.

The write control signal W525 is supplied to the input terminal 105. Write control signal W525
Is “1” when the writing side is the 525/60 system and is “0” when the writing side is the 625/50 system. The write control signal W525 is supplied to the exclusive OR gate (EX or gate) 106 together with the read control signal R525 supplied to the input terminal 95.

The output signal S12 of the EX OR gate 106 is supplied to the changeover switch 103 as a changeover control signal.
The changeover switch 103 is connected to the b side when the signal S12 is "1", and is a when the signal S12 is "0".
Connected to the side.

Also, the output signal S of the EX OR gate 106
12 is supplied to the connection switch 104 as an on / off control signal. The signal S12 of the connection switch 104 is "1".
When it is, it is turned off, and when it is "0", it is turned on.

This example is constructed as described above, and the others are constructed in the same manner as the examples of FIGS. 22 and 23.

First, a case will be described in which the write side and read side systems are the same, and system conversion is not performed.

At this time, the output signal S12 of the EX OR gate 106 becomes "0", and the changeover switch 103 is connected to the a side. In the flip-flop 102, the decoder 8
The output signal S7 of 0 is latched by the output signal S9 of the decoder 84. Then, the Q of the flip-flop 102
A signal S whose terminal is synchronized with the horizontal synchronization on the reading side
10 is output, and this is supplied to the connection switch 101 via the a side of the changeover switch 103.

Therefore, the vertical counter 78 on the writing side
When the count data of is "BH" and "CH",
The signal HMDP is taken into the synchronous system on the read side via the connection switch 101. Then, the operation of the horizontal synchronizing system on the read side is controlled based on this signal HMDP.
The operation of this horizontal synchronization system is similar to the example of FIGS. 22 and 23 (see FIG. 24). As a result, the horizontal counter 66 on the write side and the horizontal counter 83 on the read side are halved.
It will be locked with the phase difference in the horizontal period.

Further, the output signal S of the EX OR gate 106
Since 12 becomes "0", the connection switch 104 is turned on, and the output signal S8 of the decoder 80 changes the connection switch 10
4 to the connection switch 91. for that reason,
The count data of the vertical counter 78 on the writing side is “E
When it becomes “H”, the connection switch 91 is turned on, the output signal of the OR gate 88 is supplied to the load terminal LO of the counter 90 via the connection switch 91 and the OR gate 92, and the counter 90 is loaded with the initial data. As a result, the vertical synchronization positions on the writing side and the reading side are made to substantially coincide with each other.

When the system conversion is not performed in this way,
Even if a phase shift occurs in the composite sync signal CSYNC input to the input terminal 61, the horizontal counter 83 on the read side is reset during the vertical blanking period on the read side, and no skew appears on the screen. ..

Next, a case will be described in which the write side and read side systems are different and system conversion is performed.

At this time, the output signal S12 of the EX OR gate 106 becomes "1", the connection switch 104 is turned off, and the connection switch 91 is always turned off.

The horizontal counter 83 on the reading side is sequentially incremented by the system clock CLK (see FIG. 3).
3J), "1DAH" to "3FFH", the counting operation is repeated. When the count data of the counter 83 becomes “3FFH”, the carry signal (K in the figure) obtained at the CO terminal is supplied to the enable input terminal EN of the vertical counter 90 on the reading side via the OR gate 88, and the counter 90 is sequentially incremented. (L in the figure).

The count data of the counter 90 is "3FF
When it becomes "H", the carry signal (M in the figure) obtained at the CO terminal of the counter 90 is supplied to the data terminal D2 of the flip-flop 87, and the signal (N in the figure) output from the edge detector 94 is supplied to the OR gate 92. Through the counter 90
Is supplied to the load terminal LO. As a result, the counter 90 is in the self-reset state and the initial data to "3F
The counting operation of "FH" is repeated. In this case, the counting operation of the counter 90 is asynchronous with respect to the vertical synchronization on the writing side.

Further, the output signal S of the EX OR gate 106
Since 12 is "1", the changeover switch 103 is connected to the b side, and the output signal S6 of the decoder 93 is supplied to the connection switch 101 via the b side of the changeover switch 103. When the count data of the counter 90 becomes "3E6H" and "3E7H", the signal S6 becomes "1" (I in the same figure) and the connection switch 101 is turned on. Therefore, the signal HMDP (H in the figure) in this period is taken into the synchronous system on the read side via the connection switch 101, and the horizontal counter 83 on the read side is loaded with the data "1DAH" (J in the figure). As a result, after the reading side enters the vertical blanking period, the horizontal synchronization on the reading side is synchronized with the horizontal synchronization on the writing side.

33A to G show the same signals as in FIGS. 25A to 25G. The same applies to the operation of even fields.

Even if the horizontal counter 66 on the write side is reset due to the phase shift of the composite synchronizing signal CSYNC supplied to the input terminal 61 in this way, the horizontal counter 83 on the read side is not immediately reset, and the horizontal counter 83 on the read side is read. Reset takes place during the vertical blanking period on the side. Therefore, the skew due to the reset does not appear on the output screen.

By the way, in the synchronous system configured as shown in FIGS. 31 and 32, when the system on the writing side and the system on the reading side are different as described above and system conversion is performed, vertical synchronization on the reading side is set on the writing side. By synchronizing the horizontal sync on the read side with the horizontal sync on the write side in the vicinity of the vertical sync on the read side without synchronizing on the vertical sync, skew due to the phase shift of the composite sync signal CSYNC does not appear on the output screen. ing.

In this case, since the horizontal sync on the read side is not synchronized with the horizontal sync on the write side until near the vertical sync on the read side, when the phase shift of the composite sync signal CSYNC becomes large, the write and read on the same memory are performed. The operations overlap with each other, and the alternating operation of writing and reading of the memories 23A and 23B fails. Composite sync signal C
The phase shift of SYNC becomes large when the dubbing is repeated many times in the VTR having the shifted heads (HB and HC in FIG. 28).

34 to 36 show the composite sync signal CSYN.
Even if the phase shift of C becomes large, the memories 23A, 23B
FIG. 6 is a block diagram of a synchronous system in which an alternating operation of writing and reading is favorably performed. In these figures, parts corresponding to those in FIGS. 31 and 32 are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 34, decoder 67 outputs signals HMDPM, HMDPP and WHDP in addition to write horizontal start signal WHS and signal HMDP. In addition, the decoder 67 has a select signal SSE.
L is supplied. As will be described later, the select signal SSEL is set to "1" when the image frame is set to 80% and wide, and is set to "0" when the image frame is set to 70% and narrow.
It is said that.

Signals WHS, HMDPM, HMDP, HM
DPP and WHDP are output at the following timings according to the state of the select signal SSEL. Here, 11-bit data supplied to the data terminal D of the decoder 67 is WHCNT.

The signal WHS is output when the data WHCNT becomes "289H" and "61FH" when the select signal SSEL is "1", and the select signal SS is output.
When EL is “0”, the data WHCNT is “2C1.
It is output when it becomes "H" and "61FH".

The signal HMDPM is the select signal SSEL.
When is “1”, the data WHCNT is “3B2H”
When the selection signal SSEL is "0", it is output when the data WHCNT is "37AH".

The signal HMDP is the data WHC regardless of whether the select signal SSEL is "1" or "0".
It is output when NT becomes "3FFH".

The signal HMDPP is the select signal SSEL.
When is “1”, the data WHCNT is “624H”
When the selection signal SSEL is "0", it is output when the data WHCNT is "65CH".

The signal WHDP is the data WHC regardless of whether the select signal SSEL is "1" or "0".
It is output when NT becomes "1 DAH".

From the decoder 80, the signals S3 and S
In addition to 4, S7 and S8, the signal S13 is output. The signal S13 is set to "1" when the count data of the counter 78 becomes "DH". Signal S13 is AND gate 11
1 and the output signal of the OR gate 72 is also supplied to the AND gate 111. The signal SYV is output from the AND gate 111.

Further, as shown in FIG. 36, the select signal SSEL is supplied to the decoder 84. Here, 11-bit data supplied to the data terminal D of the decoder 84 is RHCNT. The read horizontal start signal RHS output from the decoder 84 is the select signal SSEL.
When the value is "1", the data RHCNT is "289H".
And when the select signal SSEL is "0", the data RHCNT is "2".
It is output when it becomes "C1H" and "61FH".

The signal HMDPR is supplied to the input side of the connection switch 101. This signal HMDPR and the above-mentioned select signal SSEL are formed by the block shown in FIG.

In the figure, 11-bit data WHCNT similar to that supplied to the data terminal D of the decoder 67.
Is supplied to the data terminal D of the decoder 112. The output terminals Q0 to Q7 of the decoder 112 are respectively supplied with the signal WHD.
Eight timing pulses TP1 to TP8 indicating time points -t4 to t4 before and after the center of P are output.

Here, when one horizontal period is 100%, time points -t4, -t3, -t2, -t1, t1, t2, t.
3 and t4 are −26.5%, −16.5%, −9.5%, −2.5 with respect to the timing of the signal WHDP, respectively.
%, 2.5%, 9.5%, 16.5%, and 26.5% are set (see FIG. 37).

The timing pulses TP1 to TP8 are supplied to the phase shift detection circuit 113. Terminal I of the detection circuit 113
The signal S14 obtained at the output side of the connection switch 64 (FIG. 34) is supplied to N. In the detection circuit 113, the terminal I
The timing of the synchronization pulse CSYNCP supplied to N is the time points -t4, -t3, -t2, -t1, t1,
Range divided by t2, t3, t4 -L3, -L2, -L
Which of 1, L0, L1, L2 and L3 (see FIG. 37) belongs is detected.

Also, the write vertical start signal WVS output from the AND gate 81 (FIG. 34) is the counter 1
It is supplied to 14 enable input terminals EN. A carry signal is output to the CO terminal of the counter 114 every 64 counts. This carry signal is the connection switch 11
5 is supplied to the enable input terminal EN of the detection circuit 113. When the carry signal is supplied, the detection circuit 113 outputs data indicating the detected range as described above in synchronization with the system clock CLK.

The connection switch 115 has an AND gate 1
The signal SYV output from 11 (FIG. 34) is supplied as an on / off control signal. The connection switch 115 receives the signal S
It is turned on when YV is "1".

When the terminal of the detection circuit 113 is turned on, E
Signal S1 output from X-OR gate 106 (FIG. 36)
2 is supplied. Both signals R525 and W525 are "1"
Or when it is “0” and the signal S12 is “0”,
That is, when the system conversion is not performed, the detection circuit 113 outputs data indicating the range S0 regardless of the range detected as described above.

The data indicating the detection range output from the detection circuit 113 is the data terminal D of the D flip-flop 117.
Is supplied to. The carry signal obtained at the CO terminal of the counter 114 is supplied to the enable input terminal EN of the flip-flop 117 via the connection switch 115. When the carry signal is supplied, the data indicating the detection range supplied to the data terminal D is latched in synchronization with the system clock CLK.

The data S15 obtained at the output terminal Q of the flip-flop 117 is supplied to the data terminal D of the D flip-flop 118. The carry signal obtained at the CO terminal of the counter 114 is supplied to the enable input terminal EN of the flip-flop 118 via the connection switch 115. When the carry signal is supplied, the data S15 indicating the detection range supplied to the data terminal D is latched in synchronization with the system clock CLK.

The data S15 and S16 obtained at the output terminals Q of the flip-flops 117 and 118 are supplied to the terminals A and B of the coincidence detection circuit 119, respectively. Detection circuit 1
An AND gate 11 is connected to the enable input terminal EN of 19.
The signal SYV output from 1 (FIG. 34) is supplied through the delay circuit 120 having a delay time of 3 clocks. When the signal SYV supplied to the enable input terminal EN becomes “1”, the detection circuit 119 detects whether or not the data S15 and S16 match in synchronization with the system clock CLK. Then, when they match, the data is output.

Data DP output from the detection circuit 119
Is supplied to the decoder 121. The decoder 121 has
Signal HMDP output from decoder 67 (FIG. 34)
M, HMDP and HMDPP are supplied. Decoder 12
In 1, the signal HMDPM, depending on the range indicated by the data DP,
Either HMDP or HMDPP is selected and signal HM
The signal HMDPR is output as DPR, and is supplied to the input side of the connection switch 101 (FIG. 36) as described above.

That is, the signal HMDPM is selected when the data DP indicates one of the ranges -L2 and -L1, and the signal HMDP is selected when the data DP indicates the range L0. When the range is indicated, the signal HMDPP is selected (see FIG. 37).

In the decoder 121, the select signal SSEL is formed according to the range indicated by the data DP. That is, when the data DP indicates any range of -L2, L2, it is set to "0", and when the data DP indicates any range of -L1, L0, L1, it is set to "1". The select signal SSEL thus formed is supplied to the decoders 67 and 84 as described above.

When the data DP indicates one of the ranges -L3 and L3, the decoder 121 outputs the signal WDIS. This controls the memory write timing generator 24 to control the memories 23A and 23B.
Is stopped and the still image is output.

The present example is constructed as described above, and the others are constructed in the same manner as the examples of FIGS. 31 and 32.

The operation of forming signal HMDPR and select signal SSEL in the block shown in FIG. 35 will be described. A case where the write control signal W525 and the read control signal R525 have different states and the output signal S12 of the EX OR gate 106 becomes "1", that is, the system conversion is described.

First, the case where the internal counter is delayed with respect to the input composite synchronizing signal CSYNC will be described with reference to the timing chart of FIG.

38A shows a composite synchronizing signal CSYNC supplied to the terminal 61, FIG. 38B shows a signal S3 output from the decoder 80, FIG. 38C shows a signal supplied to the load terminal LO of the counter 66, and FIG. The output of the counter 66, the output E of the flip-flop 70 in the same figure E, the output of the OR gate 72 in the same figure F, the falling edge of the Q8 output of the counter 66 in the same figure H, the output of the counter 78 in the same figure I are shown. And is the same as described in the other embodiments described above.

The signal WHDP is output from the decoder 67 when the output of the counter 66 becomes "1DAH" and the output S1 of the flip-flop 70 becomes "0" (FIG. 38G). The signal WHDP corresponds to the horizontal synchronizing position of the internal counter.

In the phase shift detection circuit 113, the decoder 1
Based on the timing pulses TP1 to TP8 from 12, the range -L3 to L centered on the signal WHDP as described above.
3 is set (J in the same figure). The output of the counter 78 is "A
Output signal S of the decoder 80 when it becomes "H" and "BH"
3 becomes "1", the connection switch 64 is turned on, and the synchronization pulse CSYNCP is supplied to the terminal IN of the phase shift detection circuit 113. As a result, the synchronization pulse CSYNC
Range corresponding to -n (-L3, -L2, -L1, L0)
Is detected (K in the same figure).

In this state, when the output of the counter 78 becomes "CH", the output signal S of the AND gate 111
YV becomes "1" (L in the figure), and the connection switch 115
Turns on. At this time, when the count value of the counter 114 is “3FH” and the signal “1” is output as the carry signal to the terminal CO, the detection circuit 113 is detected.
Since the signal of "1" is supplied to the enable input terminal EN of, the detection circuit 113 outputs the data indicating the range -n detected as described above (M in the figure).

In this state, when the output of the counter 78 becomes "DH", the AND gate 81 outputs the signal WVS.
Is output (N in the figure), and the count data of the counter 114 is incremented from "3FH" to "0H" (O in the figure).

The signal SYV becomes "1" one vertical period (1V later) from this state, but the terminal CO of the counter 114 is
Since the "0" signal is output to the detection circuit 113,
Output does not change. Further, since the signal WVS is output, the counter 114 is incremented. The same operation is repeated until 63V is reached.

After 64V, since the signal SYV becomes "1" and the signal "1" is output to the terminal CO of the counter 114 (P in the same figure), "1" is output to the enable input terminal EN of the flip-flop 117. The signal "1" is supplied, and the data output to the detection circuit 113 is latched (Q in the figure). Further, since a signal of "1" is supplied to the enable input terminal EN of the detection circuit 113 with a delay of one clock, the detection circuit 113 outputs data indicating the range -n detected after 64V (the same). (Figure M). Further, the count data of the counter 114 is incremented from "3FH" to "0H" (O in the figure).

Then, after 128V, the same operation as after 64V is performed, a signal of "1" is supplied to the enable input terminal EN of the flip-flop 118, and the output data of the flip-flop 117 is latched ( R), a signal of "1" is supplied to the enable input terminal EN of the flip-flop 117, and the output data of the detection circuit 113 is latched. Then, after the signal SYV becomes "1", a signal of "1" is supplied to the enable input terminal EN of the detection circuit 119 with a delay of 3 clocks, and the output data S15, S of the flip-flops 117, 118 are output.
16 matches are detected. That is, it is detected whether or not the data indicating the range −n detected by being separated by 64 V match. When they match, the data DP is output from the detection circuit 119 (S in the figure).

When the data DP is output in this way, the decoder 121 outputs H as described above according to the data DP.
MDPR is selected and the select signal SSEL is determined. FIG. T shows an example in which HMDPM is selected as the HMDPR.

Next, a case where the internal counter is advanced with respect to the input composite synchronizing signal CSYNC will be described with reference to the timing chart of FIG.

39A to 39J show signals corresponding to A to J in FIG.

The output of the counter 78 is "AH" and "B".
When it becomes "H", the output signal S3 of the decoder 80 becomes "1", the connection switch 64 is turned on, and the synchronization pulse CS
YNCP is supplied to the terminal IN of the phase shift detection circuit 113. As a result, the range + n (L0, L1, L2, L3) corresponding to the synchronization pulse CSYNC is detected (K in the same figure).

In this state, when the output of the counter 78 becomes "CH", the output signal S of the AND gate 111
YV becomes "1" (L in the figure), and the connection switch 115
Turns on. At this time, when the count value of the counter 114 is “3FH” and the signal “1” is output as the carry signal to the terminal CO, the detection circuit 113 is detected.
Since the signal of "1" is supplied to the enable input terminal EN of, the detection circuit 113 outputs the data indicating the range + n detected as described above (M in the figure).

In this state, when the output of the counter 78 becomes "DH", the AND gate 81 outputs the signal WVS.
Is output (N in the figure), and the count data of the counter 114 is incremented from "3FH" to "0H" (O in the figure).

Since the subsequent operation is similar to that of the timing chart of FIG. 38 described above, its explanation is omitted.

If the write control signal W525 and the read control signal R525 are in the same state and the output signal S12 of the EX OR gate 106 is "0", that is, if the system conversion is not performed, the output of the detection circuit 113 is L0.
Output data DP of the detection circuit 119 also becomes data indicating the range of L0. Therefore, the decoder 121 selects the HMDP as the HMDPR, and the select signal SSEL is set to "1".

Since the operation of generating signals WHS, WVS, RHS, RVS in the blocks shown in FIGS. 34 and 36 is similar to that of the blocks shown in FIGS. 31 and 32 described above, description thereof will be omitted. ..

Next, the timing of writing and reading of the memories 23A and 23B when the signal HMDPR is selected and the select signal SSEL is formed as described above will be described with reference to FIG. MEMA, ME
MB indicates the memories 23A and 23B, respectively.

First, writing to the memories 23A and 23B will be described.

FIG. 40A shows the composite synchronizing signal CSYNC, FIG. 40B shows the output of the counter 66, and FIG. 40C shows the flip-flop 7.
The output S1 of 0 is shown.

Select signal SSEL is "1" (wide)
When the write horizontal start signal WHS is output from the decoder 67 at the timings of "289H" and "61FH" (D in the figure), the write to the memory 23A is "289H" as shown in the E of the figure. The writing to the memory 23B is started at the timing of "61FH", and the image frame 8 is written in the memories 23A and 23B.
A video signal corresponding to 0% is written.

On the other hand, when the select signal SSEL is "0" (narrow) and the write horizontal start signal WHS is output from the decoder 67 at the timings of "2C1H" and "61FH" (D in the same figure), As shown in FIG. F, the writing to the memory 23A is started at the timing of "2C1H", and the writing to the memory 23B is "61F".
The video signal corresponding to the image frame 70% is written in the memories 23A and 23B at the timing of "H".

Next, reading from the memories 23A and 23B will be described. FIG. 40G shows the signal HMDPR supplied to the connection switch 101.

When the signal HMDPM is selected as the signal HMDPR and the select signal SSEL is "0" (narrow), the counter 83 is reset to "1 DAH" at the timing "37 AH" on the write side (H in the figure). ). FIG. 1I shows the output S5 of the flip-flop 87 at that time. At this time, the read horizontal start signal RHS output from the decoder 84 is output at the timing of "2C1H" and "61FH" (J in the same figure).
As shown in K of FIG.
The reading from the memory 23B is started at the timing of "C1H", and the reading from the memory 23B is started at the timing of "61FH" (K in the figure), and the video signal corresponding to the image frame 70% is read from the memories 23A and 23B.

Also, the signal HMDP is used as the signal HMDP.
When M is selected and the select signal SSEL is "1" (wide), the counter 83 is reset to "1DAH" at the timing of "3B2H" on the writing side (L in the figure). At this time, the read horizontal start signal RHS output from the decoder 84 is output at the timing of "289H" and "61FH" (M in the figure), and as shown in N in the figure, the read from the memory 23A is "289".
The reading from the memory 23B is started at the timing of "61", and the reading from the memory 2B is started at the timing of "61FH".
A video signal corresponding to 80% of the image frame is read from 3A and 23B.

The signal HMDP is used as the signal HMDP.
Is selected and the select signal SSEL is “1” (wide)
If it is, the counter 83 is reset to "1DAH" at the timing of "3FFH" on the writing side (O in the figure). At this time, the read horizontal start signal RHS output from the decoder 84 is "289H" and "61F".
It is output at the timing of "H" (P in the same figure), and as shown in Q of the same, reading from the memory 23A is started at the timing of "289H", and reading from the memory 23B is started at the timing of "61FH". Memory 23A,
A video signal corresponding to 80% of the image frame is read from 23B.

The signal HMDP is used as the signal HMDP.
When P is selected and the select signal SSEL is "1" (wide), the counter 83 is reset to "1DAH" at the timing of "624H" on the writing side (R in the figure). At this time, the read horizontal start signal RHS output from the decoder 84 is output at the timing of "289H" and "61FH" (S in the same figure), and the read from the memory 23A is "289" as shown in T in the same figure.
The reading from the memory 23B is started at the timing of "61", and the reading from the memory 2B is started at the timing of "61FH".
A video signal corresponding to 80% of the image frame is read from 3A and 23B.

The signal HMDP is used as the signal HMDP.
When P is selected and the select signal SSEL is "0" (narrow), the counter 83 is reset to "1DAH" at the timing of "65CH" on the write side (U in the figure). At this time, the read horizontal start signal RHS output from the decoder 84 is output at the timings of "2C1H" and "61FH" (V in the same figure), and the read from the memory 23A is "2C1H" as shown in W in the same figure.
The reading from the memory 23B is started at the timing of "61", and the reading from the memory 2B is started at the timing of "61FH".
A video signal corresponding to 70% of the image frame is read from 3A and 23B.

When the signal WDIS is output from the decoder 121 (FIG. 35), the memory 2 is used as described above.
Writing to 3A and 23B is stopped, but reading is repeated in the state immediately before that. Therefore, the output state of the still image is 80% or 70%.

As described above, in the examples of FIGS. 34 to 36, the picture frame 80% (wide) or the picture frame 70% (narrow) of the memories 23A and 23B is dealt with in response to the phase shift of the internal counter with respect to the composite synchronizing signal CSYNC. Are written and read.

As shown in FIG. 40, in both the image frame 80% operation and the image frame 70% operation, during the period from the writing start time of the memory 23B to the writing end time of the memory 23A, the reading start time of the memory 23A From the end of reading of the memory 23B is included. In addition, in both of the operation of the image frame 80% and the image frame 70%, the memory 23B starts from the end of writing in the memory 23B.
During the period until the writing of A is started, reading from the memory 23A is switched to the memory 23B.

Therefore, even if there is a phase shift in the internal counter with respect to the composite synchronizing signal CSYNC, the memory 23
The alternating operation of writing and reading of A and 23B will not fail.

Further, in FIGS. 34 to 36, 64V
The phase shift of the internal counter with respect to the composite synchronization signal CSYNC is detected for each period of, and the signal HMDPR and the select signal SSEL are changed when the same phase shift is detected twice, and writing to the memories 23A and 23B,
The reading state does not change frequently, and the deterioration of image quality can be prevented.

Although not described in the above embodiment,
For example, when the image frame is 70%, the outside of the image frame becomes an unsightly noise screen, and therefore muting may be considered.

[0298]

According to the present invention, the number of lines and the number of fields are converted by alternately controlling the first and second memories to be in the write state and the read state every 1/2 horizontal period. , A low-priced general-purpose memory (storage capacity for 0.5 fields) can be used instead of an expensive video RAM for each memory,
A method conversion device that also performs field conversion can be constructed at low cost.

Further, when the horizontal synchronization of the input video signal is deviated, the influence is transmitted to the reading side during the vertical blanking period of the reading side regardless of the presence or absence of the system conversion. Can be well avoided.

Further, since the image frames of the video signals to be written in the first and second memories are changed according to the phase shift between the horizontal sync of the input video signal and the horizontal sync on the writing side, even if the phase shift becomes large, Alternate operations of writing and reading of the first and second memories will not fail.
In this case, by detecting the phase shift every predetermined period, it is possible to prevent the image quality from being deteriorated without changing the image frame frequently.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment.

FIG. 2 is a block diagram showing a configuration of an example.

FIG. 3 is a connection diagram showing a configuration of an A / D conversion processing unit.

FIG. 4 is a diagram for explaining the operation of the example of FIG.

FIG. 5 is a diagram for explaining the operation of the embodiment.

FIG. 6 is a diagram for explaining the operation of the embodiment.

FIG. 7 is a connection diagram illustrating a configuration of a luminance signal quantization processing unit.

FIG. 8 is a diagram for explaining quantization in a normal A / D converter.

FIG. 9 is a diagram for explaining quantization in the example of FIG. 7.

FIG. 10 is a diagram illustrating a memory write cycle in a normal mode and a page mode.

FIG. 11 is a diagram for explaining a memory read cycle in a normal mode and a page mode.

FIG. 12 is a connection diagram showing a configuration of a demultiplexer.

FIG. 13 is a diagram for explaining the operation of the demultiplexer.

FIG. 14 is a connection diagram showing a configuration of a sub-sampling data processing circuit.

FIG. 15 is a diagram showing sub-sampling data.

16 is a diagram for explaining the signal processing of the example of FIG.

FIG. 17 is a diagram showing sub-sampling data (double reading).

FIG. 18 is a diagram showing data of main parts of the processing circuit of the example of FIG. 14;

FIG. 19 is a diagram for explaining the signal processing of the example in FIG.

20 is a diagram for explaining the signal processing of the example of FIG.

FIG. 21 is a diagram for explaining color signal synchronization processing.

FIG. 22 is a block diagram showing a synchronous system on a writing side and a reading side.

FIG. 23 is a block diagram showing a synchronous system on a writing side and a reading side.

FIG. 24 is a diagram for explaining the operation of the horizontal synchronization system of the examples of FIGS. 22 and 23.

FIG. 25 is a diagram for explaining the operation (odd field) of the vertical synchronization system in the examples of FIGS. 22 and 23.

FIG. 26 is a diagram for explaining an operation (even field) of the vertical synchronization system in the examples of FIGS. 22 and 23.

FIG. 27 is a block diagram showing a configuration of a system clock generator.

FIG. 28 is a diagram showing an overview of a rotary head device.

FIG. 29 is a diagram for explaining a phase shift of horizontal synchronization.

[Fig. 30] Fig. 30 is a schematic diagram showing a manner of system conversion.

FIG. 31 is a block diagram showing a synchronous system on a writing side and a reading side.

FIG. 32 is a block diagram showing a synchronous system on a writing side and a reading side.

FIG. 33 is a diagram for explaining the operation (odd field) of the vertical synchronization system shown in FIGS. 31 and 32.

FIG. 34 is a block diagram showing a synchronous system on a writing side and a reading side.

FIG. 35 is a block diagram showing a synchronous system on a writing side and a reading side.

FIG. 36 is a block diagram showing a synchronous system on a writing side and a reading side.

FIG. 37 is a diagram showing the relationship between the amount of phase shift and the signals SSEL and HNDPR.

FIG. 38 is a diagram for explaining an operation of discriminating a synchronization deviation (when the internal counter is delayed with respect to the input CSYNC).

FIG. 39 is a diagram for explaining an operation of discriminating a synchronization shift (when the internal counter is advanced with respect to the input CSYNC).

FIG. 40 is a memory write in FIGS. 34 to 36;
It is a figure for demonstrating read-out timing.

FIG. 41 is a diagram for explaining line number conversion in system conversion.

[Fig. 42] Fig. 42 is a diagram for describing field number conversion in system conversion.

[Fig. 43] Fig. 43 is a diagram for describing line number conversion in system conversion.

[Explanation of symbols]

1Y, 1C Input terminal 2,5 Resistor 3,40 Adder 4 Write timing generator 6,14,15,25 Switch circuit 7 Color demodulator 8 AFC circuit 9 A / D converter 10,12 Latch circuit 11 Digital low pass Filter 13 P / S converter 21, 22, 34, 36, 42 to 44, 46, 48 Changeover switch 23A, 23B Memory 24 Memory write timing generator 26 Synchronization generator 27 Memory read timing generator 31 Demultiplexer 32 Read timing Generator 33 Filter circuit 35,45 Delay circuit 37,47,49 Signal generator 38,51 D / A converter 39 Low pass filter 41 S / P converter 50 Color modulator 52 Band pass filter 53 Output terminal

Claims (2)

[Claims] 1. A first memory and a second memory having a storage capacity of 1/2 horizontal period in the horizontal direction and a storage capacity of 1 vertical period in the vertical direction are provided, and the first memory is provided in the first memory. In the television conversion device for converting the number of lines and the number of lines by writing and reading the data in the first half of the horizontal period and writing and reading the data in the latter half of the horizontal period in the second memory, when the system conversion is not performed, In the vicinity of the vertical sync position on the write side of the memory, the horizontal sync and vertical sync on the read side of the memory are synchronized with the horizontal sync and vertical sync on the write side, respectively, to convert the system. Without synchronizing the vertical synchronization with the vertical synchronization on the writing side, the reading may be performed near the vertical synchronization position on the reading side. When synchronizing the horizontal sync on the write side with the horizontal sync on the write side, and when performing the system conversion, the phase difference between the horizontal sync on the input video signal and the horizontal sync on the write side is detected, and the phase difference is detected. A television system conversion device, characterized in that the image frame of the video signal to be written in the first and second memories is changed. 2. The detection of the phase difference is detected every predetermined period, and when the substantially same phase difference continues twice or more, the image frame is changed according to the phase difference. The described television system conversion device.