JPH05268568A - Band compression processing unit - Google Patents

Abstract

PURPOSE:To easily obtain an excellent reproduced picture at the high speed reproduction by controlling a generated code quantity of a refresh block so that a prescribed maximum code quantity is not exceeded. CONSTITUTION:The arrangement on a track of a refresh block and a non- refresh block is differentiated. Then, e.g. 24 refresh blocks are recorded to one sector. Since one track consists of 10 sectors, 240 refresh blocks are inserted to one track and it is coincident with the number of refresh blocks in one frame of a video signal. A refresh block control circuit 40 generates a code location signal of the refresh block and gives the signal to a code replacement circuit 39, the code replacement circuit 39 rearranges the refresh blocks and the non-refresh blocks based on the inputted video code and the code location signal. An output of the code replacement circuit 39 is fed to an index insertion circuit 41 and its output is fed to heads A, B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting a video signal or the like into a digital signal and performing band compression by combining intra-frame coding processing and inter-frame coding processing.
The present invention relates to a device which can easily obtain a good reproduced image when the output signal is recorded on, for example, a tape by a helical scan method and transmitted to a recording / reproducing device for reproducing the recorded signal.

[0002]

2. Description of the Related Art As is well known, when digitally transmitting a video signal, band compression is performed by combining a transmission method using a variable length coding method or a combination of intraframe coding processing and interframe coding processing. Transmission methods are being studied. Among them, a technique for performing band compression by combining intraframe coding processing and interframe coding processing and transmitting the data is disclosed in, for example, the document IEEE Trans.on Broadcasting.
Vol.36 NO.4 DEC 1990 Woo Paik: “Digit
It is a band compression technology as shown in "al compatible HD-TV Broadcast system", and its characteristic part is explained below.

In FIG. 24, the video signal input to the input terminal 11 is supplied to the subtraction circuit 12 and the motion evaluation circuit 13, respectively. The subtraction circuit 12 performs a subtraction process, which will be described later, and the output thereof is input to a DCT (discrete cosine transform) circuit 14. The DCT circuit 14 takes in 8 pixels in the horizontal direction and 8 pixels in the vertical direction as a unit block (8 × 8 pixels = 64 pixels), and outputs a coefficient obtained by converting the pixel array from the time axis domain to the frequency domain. Then, each coefficient is quantized by the quantization circuit 15. In this case, the quantization circuit 15 has 10 or 32 types of quantization tables, and each coefficient is quantized based on the selected quantization table. The quantization circuit 15
In the above, the reason why the quantization table is provided is that the amount of information generated and the amount of information transmitted are kept within a certain range.

The coefficient data output from the quantizing circuit 15 is zigzag-scanned from the low frequency band to the high frequency band for each unit block, and is extracted.
It is inputted to 6 and variable-length coded with the number (run length) following the zero coefficient and the non-zero coefficient as one set. The encoder is a variable length encoder having a different code length depending on the frequency of occurrence of Huffman code or the like. The variable-length coded data is input to a FIFO (first-in-first-out) circuit 17 and read out at a prescribed speed, and then, via an output terminal 18, a multiplexer at the next stage (not shown). [Control signals, voice data, sync data (SYN
C), multiplex NMP etc. described later] is supplied to the transmission path. Since the output of the variable length coding circuit 16 has a variable rate and the rate of the transmission path is a fixed rate, the FIFO circuit 17 serves as a buffer that absorbs the difference between the generated code amount and the transmitted code amount. ..

The output of the quantization circuit 15 is input to the inverse quantization circuit 19 and inversely quantized. Further, the output of the inverse quantization circuit 19 is input to the inverse DCT circuit 20 and returned to the original signal. This signal is input to the frame delay circuit 22 via the adder circuit 21. The output of the frame delay circuit 22 is supplied to the motion compensation circuit 23 and the motion evaluation circuit 13, respectively. Motion evaluation circuit 13
Is the input signal from the input terminal 11 and the frame delay circuit 2
The output signal of 2 is compared to detect the overall motion of the image, and the phase position of the signal output from the motion compensation circuit 23 is controlled. In the case of a still image, the original image and the image one frame before are compensated so as to match. The output of the motion compensation circuit 23 can be supplied to the subtraction circuit 12 via the switch 24, and can also be fed back from the addition circuit 21 to the frame delay circuit 22 via the switch 25.

Next, the basic operation of the above system will be described. The basic operation of this system includes intraframe coding processing and interframe coding processing. The intra-frame coding process is performed as follows. When this process is performed, both switches 24 and 25 are off. The video signal of the input terminal 11 is converted from the time domain to the frequency domain by the DCT circuit 14 and quantized by the quantization circuit 15. The quantized signal is subjected to variable length coding processing and then output to the transmission line via the FIFO circuit 17. The quantized signal is supplied to the inverse quantization circuit 19
The signal is returned to the original signal by the inverse DCT circuit 20, and delayed by the frame delay circuit 22. Therefore, in the intra-frame coding process, it is equivalent to that the information of the input video signal is variable length coded as it is. This intra-frame processing is performed in a proper cycle in units of predetermined blocks and scene changes of the input video signal. The periodic in-frame processing will be described later.

Next, the interframe coding process will be described. When the inter-frame coding process is executed, both the switches 24 and 25 are turned on. Therefore, a signal corresponding to the difference between the input video signal and the video signal one frame before is obtained from the subtraction circuit 12. This difference signal is
It is input to the DCT circuit 14, converted from the time domain to the frequency domain, and then quantized by the quantization circuit 15. Further, since the differential signal and the video signal are added by the adding circuit 21 and input to the frame delay circuit 22,
A predicted video signal that predicts the input video signal from which the differential signal was created is created and input.

FIG. 25 shows a line signal in a state in which a video signal of a high-definition television signal is subjected to the intraframe processing and the interframe processing as described above and sent out on the transmission path. This signal is a signal of a transmission line, and is shown in a state in which a control signal, a voice signal, a synchronization signal (SYNC), a system control signal, NMP and the like are multiplexed. FIG. 25A shows signals on the first line, and FIG. 25B shows signals on the second and subsequent lines. If this video signal has undergone intra-frame processing, a normal video signal can be obtained by inverse conversion. However, in the case of a video signal that has been subjected to interframe coding processing, the difference signal is only reproduced even if this signal is inversely converted. Therefore, a normal video signal can be reproduced by adding the video signal (or predicted video signal) reproduced one frame before to this difference signal.

According to the above system, all the information in the signal processed in the frame is variable-length coded, and the signal processed in the inter-frame after the next frame transmits the difference information. It means that compression is realized.

Next, the definition of the set of pixels processed by the band compression system will be described. That is, a block: an area of 64 pixels composed of 8 pixels in the horizontal direction and 8 pixels in the vertical direction. Super block: An area consisting of 4 blocks in the horizontal direction and 2 blocks in the vertical direction of the luminance signal. This area includes one block as the color signals U and V.
The image motion vector obtained from the motion evaluation circuit 13 is included in units of super blocks. Macroblock: 11 superblocks in the horizontal direction. Also, when the code is transmitted, the DCT coefficient of the block is converted into a code determined by the number of consecutive zero coefficients and the amplitude of the non-zero coefficient, and these are transmitted as a set to transmit the code of the block. The end of block signal is added at the end. Then, the motion vector of the motion correction performed in units of super blocks is added and transmitted in units of macro blocks.

With respect to the transmission signal shown in FIG.
Further explanations will be given on particularly relevant matters. First
The line synchronization (SYNC) signal indicates a frame synchronization signal in the decoder, and one timing synchronization signal is used for one frame to generate all timing signals of the decoder. The NMP signal on the first line indicates the number of video data from the end of this signal to the beginning of the macroblock of the next frame. This is because the code is configured by adaptively switching between the intra-frame coding process and the inter-frame coding process, so that the code amount of one frame differs for each frame, and the code position differs. This is because of Therefore, the position of the code corresponding to one frame is indicated by the NMP signal.

Further, as a countermeasure when the user changes the channel, periodical intraframe processing is performed. That is, in this band compression system, as described above, 11 super blocks in the horizontal direction are referred to as macro blocks, and 44 super blocks exist in the horizontal direction of one screen. That is, in one frame, there are a total of 240 macroblocks of 4 macroblocks in the horizontal direction and 60 macroblocks in the vertical direction. Then, in this band compression system, FIGS.
As shown in FIGS. 27A to 27C, refresh is performed for each column of four super blocks in units of four macro blocks, and all the super blocks are refreshed every 11 frame periods. That is, as shown in FIG. 27 (d), the refreshed super block is accumulated for 11 frames, so that the intra-frame processing is performed in all areas.
Therefore, for example, during normal reproduction of a VTR (video tape recorder) or the like, the above-described intraframe processing is performed at an 11-frame cycle, so that the reproduced image can be viewed without any problem.

Head data is inserted at the beginning of the macroblock. This head data contains
The motion vector, field / frame determination, PCM / DPCM determination, quantization level, etc. of each super block are inserted together.

By the way, the band compression system described above is
It is used as an encoder for band compression of television signals, and the decoder is used on the receiving side. Now, consider recording the above transmission signal in a VTR.
A general VTR is a system in which a video signal of one field is converted into a fixed length code, a certain amount of information is generated, and recorded on X (X is a positive integer) tracks.

On the other hand, when the transmission signal obtained by the band compression system is used as it is for recording / reproducing on the VTR, the variable length code is used as it is for the code subjected to the intra-frame processing and the inter-frame processing. Since the position where the code processed in the frame is recorded is not fixed, a block that is not refreshed may occur during high speed reproduction.

More specifically, FIG. 28 shows a track pattern when the variable-length coded signal as described above is helically recorded on the magnetic tape 26. In track patterns T ₁ through T _11, a portion indicated by a thick line indicates the switching position of the frame F ₁ to F _11. The switching positions of the frames F _{1 to} F ₁₁ are not aligned because the record data is created by the variable length code. In the magnetic tape 26, when normally reproduced by a VTR, all track patterns T _{1 to} T ₁₁ are sequentially scanned by the magnetic head. Therefore, by passing the reproduction output to the decoder, no problem occurs. It is possible to reproduce various video signals. That is, during normal reproduction, it is possible to reproduce all of the intra-frame processed code and the inter-frame processed code recorded on the magnetic tape 26, so that an image can be constructed using all the codes.

However, in the VTR, there are cases in which only a limited number of tracks are reproduced, as in the double speed reproduction mode in special reproduction. At this time, the magnetic head jumps the track and picks up the recording signal. In this case, there is no problem if the tracks of the signal subjected to the intra-frame coding process are reproduced one after another, but if the tracks subjected to the inter-frame coding process are reproduced, only the image by the differential signal is obtained.

FIG. 29 shows the trace loci X _{1 to} X ₁₁ of the magnetic head when the double speed reproduction is performed. Figure 2
In 9, since the signal in the frame F ₁ to F ₂₄ are respectively processed frame coding is recorded is distributed, the position of the frame in the processing portion to be reproduced in the screen has become unstable. The intra-frame processed signals that can be reproduced at the double speed reproduction are shown in FIGS. 30 (a) to 30 (h) and FIGS. 31 (a) to 31 (c). And these 1
When one frame is accumulated, as shown in FIG. 31 (d),
There is no code for which intra-frame processing is performed periodically, that is, there is a portion where a refreshed super block does not exist, and a portion that cannot compose a reproduced image occurs.

[0019]

As described above, the helical scan type recording / reproducing apparatus having the conventional band compression system has a problem that high-speed reproduction such as double-speed reproduction becomes difficult.

Therefore, the present invention has been made in view of the above circumstances, and an object thereof is to provide an extremely good band compression processing device which can easily obtain a good reproduced image at high speed reproduction.

[0021]

The band compression processing apparatus according to the present invention has a number (a is a positive integer) for one screen image signal.
Image area is formed, and the video signal is subjected to intra-frame coding processing using intra-frame coding processing using information within the frame and inter-frame coding processing using difference information between frames. And an inter-frame coding process after the intra-frame coding process and adaptively repeats the signal processing method according to the motion evaluation of the input video signal. Refresh encoding processing means for periodically performing intraframe encoding processing on a signal of b image areas of a areas for each frame, with a frame (f is an integer of f ≧ 2) as a cycle;
A circuit for calculating the generated code amount of the refresh block, which has been subjected to the refresh encoding process, and a means for controlling the generated code amount of the refresh block so as not to exceed a predetermined maximum code amount in a predetermined number of refresh blocks. It was prepared.

Further, the band compression processing apparatus according to the present invention forms a (a is a positive integer) image area in one screen of the video signal, and uses the information in the frame for this video signal. To generate an intra-frame processed signal that has been subjected to intra-frame coding processing and an inter-frame processed signal that has been subjected to inter-frame coding processing using the difference information between frames, and Band compression means that performs coding processing and adaptively repeats this signal processing method according to the motion evaluation of the input video signal, and f frames (f is f ≧ 2).
A circuit for calculating the generated code amount of the refresh coding processing, and a refresh coding processing means for periodically performing the intraframe coding processing on the signals of the a number of a A circuit for setting the quantization level of the refresh coding process and the total code amount of the non-refresh coding process and the refresh coding process without the refresh coding process are calculated from the output signal of the coding code generation calculation circuit. A code amount calculation circuit and a circuit for setting the quantization level of the non-refresh coding process by the output signal of the code amount calculation circuit are provided.

[0023]

According to the above construction, since the signal subjected to the intra-frame coding processing can be accurately obtained at the time of high speed reproduction, a good reproduced image can be obtained.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In this embodiment, the intraframe coding processing is performed on 2640 areas per screen in 11 frames, so the number of areas in one screen is a = 2640, and the intraframe coding processing period f is 11 frames. Further, here, an example in which the a = 2640 areas do not overlap each other is used, but they may overlap. further,
In order to describe the case where one track is divided into ten and the average video code for one frame is recorded in one track, the number of divisions of one track d = 10, and the number of tracks for recording the average video code for one frame c = 1. Therefore, the number of recording medium areas is d × c × f = 10 × 1 × 11 = 110. The correspondence between the screen area and the recording medium area will be described in the case of equal distribution. It should be noted that in the present invention, it is not always necessary to equally distribute. Therefore, the number of screen areas in one recording medium area e = a / d × c × f = 2640
/ 10 × 1 × 11 = 24, and d = e = 24
The case of associating with × c × f = 110 regions will be described.

In FIG. 1, the same parts as those in FIG. 24 are designated by the same reference numerals, and different parts from the conventional system will be mainly described. Further, FIG. 2 shows the operation timing of this system. Here, this embodiment will be described using a block diagram on the encoder side for simplification of description, but it can also be realized on the decoder side for receiving the transmission data shown in FIG. Referring to FIG. The sync signal SYNC of the input video signal is supplied to the input terminal 27. This synchronization signal SYNC is S
It is input to the YNC signal detection circuit 28 and detected. SY
The NC signal detection circuit 28 generates a SYNC pulse synchronized with the synchronization signal SYNC to generate the track formation signal generation circuit 2
9 is being supplied. In the case of being realized by the decoder, the synchronization signal SYN in the transmission data shown in FIG.
C may be detected and input to the SYNC signal detection circuit 28.

FIG. 2A shows an input video signal, Y is a luminance signal, U and V are chrominance signals, and the numbers entered in the frame indicate the frame numbers. Figure 2
(B) is an SY signal obtained from the SYNC signal detection circuit 28.
The NC pulse is generated and is generated in synchronization with the switching point of the frame of the input video signal shown in FIG. FIG. 2C shows the track formation signal obtained from the track formation signal generation circuit 29. A and B added to the track forming signal specify a period in which the A head and the B head alternately form tracks. A
As shown in FIG. 1, the head and the B head are attached at a position opposed to the rotary drum 30 by 180 °. Here, the case where heads are attached one by one facing each other will be described. However, when the code amount that can be recorded in one track is small, p heads (p is a positive integer) are arranged facing each other. Good. In this embodiment, SY shown in FIG.
The generation timing of the NC pulse and the switching timing of the track formation signal shown in FIG. 2C are synchronized. FIG. 2D shows tracks formed by the A head and the B head, and the numbers written in the frame indicate the track numbers.

The track formation signal output from the track formation signal generation circuit 29 is supplied to the track formation control circuit 31. This track formation control circuit 31
Controls the rotation phase of the rotary drum 30, and
The timing of supplying a recording signal to the head and the B head is controlled. In this embodiment, since the average code generation amount of one frame corresponds to one track, the rotary drum 3
A case where the number of revolutions of 0 is 900 rpm will be described. However, the average generated code of one frame may be recorded in c (c is a positive integer) tracks by scanning the magnetic head c times, and the rotational speed of the rotary drum 30 may be set to a different rotational speed such as 1800 rpm.

Next, the code exchange method used in this embodiment in order to enable the high speed reproduction of the VTR will be described. First, a combination of the color signals U and V supplied to the input terminals 32 and 33 through the decimators 34 and 35 and the luminance signal Y supplied to the input terminal 36 by the multiplexer 37 is obtained. It is supplied to the subtraction circuit 12 and the motion evaluation circuit 13 as an input video signal, and the variable-length coding circuit 16 outputs the band compression-coded video code.

Here, in the conventional band compression system shown in FIG. 24, the video signal is variable length coded and transmitted, and as shown in FIG. 2I, the switching point of the frame of the video code is the frame. Depends on Figure 2
The NMP signal shown in (h) indicates the switching point of the frame of this video signal. Conventionally, there are 2640 super blocks in one frame, and these 2640 super blocks are within one frame period shown by the NMP signal in FIG. 2 (h).

Further, conventionally, there are four macro blocks in the horizontal direction on one screen, and these macro blocks are composed of 11 super blocks. Then, one superblock in the microblock per frame is forced to use the intraframe processing. The sequence in which the in-frame processing is forcibly used is included in the system control signal shown in FIG. Here, the super block for which the intra-frame processing is forcibly performed is referred to as a refresh block, and the super block for which the intra-frame processing is not forcibly performed is referred to as a non-refresh block.

In other words, as the definition of words, when the intra-frame processing is forcibly performed by one super block in one frame period of the refresh block: macro block, the super block subjected to the intra-frame processing is called a refresh block. A macro block consists of 11 super blocks, so 1
In-frame processing is forcibly performed in one frame cycle. Non-refresh block: A super block other than the above-mentioned refresh block. Within this super block, there are a block subjected to intra-frame processing and a block subjected to inter-frame processing depending on the contents of the image. For example, when a scene change or the like occurs in the input video signal, in-frame processing may be used, but this is also a non-refresh block.

Here, 240 refresh blocks (= 2640/11) are present in one frame period. Therefore, conventionally, 240 refresh blocks are present in one frame period shown in FIG. 2H as shown in FIG. Then, the conventional signal is used as it is for VT.
When recording with R, the position of the refresh block is not fixed and high-speed reproduction cannot be performed as described above.

FIGS. 3A and 3B show video signals of frame numbers F ₅ and F ₆ , respectively. In the figure, the portions indicated by G ₅ and G ₆ indicate refresh blocks, and the portions indicated by H ₅ and H ₆ indicate non-refresh blocks. Then, thereafter, the frame number, during the refresh block number and the non-refresh block number, frame number F _n (n is an integer) the refresh block number G _n frames, the non-refresh block number and H _n.

In the present invention, the arrangement of the refresh block and the non-refresh block on the track is different.

In this embodiment, one track is divided into ten and recorded. When one track is divided into 10, high-speed reproduction can be performed up to 10 times speed. During high-speed reproduction of 11 times or more, all refresh blocks cannot be reproduced, so that an area in which an image cannot be formed occurs as in the case shown in FIG. 31 (d). If, as a VTR specification, high-speed reproduction at 20 times speed is desired, one track may be divided into 20. Further, when it is desired to realize fast high speed reproduction, refresh blocks may be arranged on the track at equal intervals.

FIG. 2 (e) shows a timing pulse for dividing one track into ten, and the one track period shown in FIGS. 2 (b) and 2 (c) is divided into ten equal parts.
Then, this one divided period is referred to as a sector.

In other words, as a definition of the word, sector: 1 track period is divided into approximately equal parts (in this case, 1
0) The divided period.

In this embodiment, as shown in FIG. 2 (f), 24 refresh blocks are placed in one sector. In this way, one track consists of 10 sectors, and 240 refresh blocks are inserted in one track, which is equal to the number of refresh blocks in one frame of the video signal. That is, the number of refresh blocks e in one sector is b, which is the number of super blocks on which periodic intraframe processing is performed.
If b intra-frame processed signals are recorded on c tracks, e = b / c × d (in this case, 240/1 × 10
= 24).

By performing the code exchange as described above, the refresh block for one frame is arranged in one frame period indicated by the NMP signal in the past, but the refresh block for one frame is replaced in one track period. Can be arranged to be present.

FIG. 4 shows a track pattern. That is, the tracks T _{1 to} T ₁₁ on the magnetic tape 26.
The G _{1 to} G ₁₁ entered in the frame of No. correspond to the refresh block number G _n described above. The relationship between this refresh block and the track T _n is the number G in the track T _n .
The relationship is that _n refresh blocks are recorded. Further, H _{1 to} H ₁₁ entered in the frames of the tracks T _{1 to} T ₁₁ are the non-refresh block numbers H described above.
Corresponds to _n . The switching point of the non-refresh block is the thick line portion shown in the frame of the tracks T _{1 to} T ₁₁ .

Track 38 in FIG. 4 shows the relationship between sectors and tracks. The track 38 is divided into 10 and d =
It is divided into 10 sectors. In this one sector,
e = 24 refresh blocks are arranged. The non-refresh block is inserted between the refresh blocks.

[0042] Here, if the track T _5, T ₆ will be described in detail as an example, the track T ₅ to record refresh blocks G ₅ of the frame F _5. Also, track T
The ₆ records the refresh block G ₆ of the frame F _6. A non-refresh block is recorded in the free space where this refresh block is arranged. The track T ₅ records non refresh block H _5, H _6, the track T ₆ records the non-refresh block H _6, H _7.

Therefore, in order to realize the above recording mode, the band compression encoded video code obtained from the variable length encoding circuit 16 in FIG. 1 is supplied to the code exchange circuit 39 again. Further, the refresh block control circuit 40 generates the code position signal of the refresh block described above, and this code position signal is supplied to the code exchange circuit 39. The code exchange circuit 39 rearranges refresh blocks and non-refresh blocks based on the input video code and code position signal.

That is, a process of inserting 24 refresh blocks into each of 10 sectors provided in one track is performed. In order to perform this processing, the code is temporarily stored in a memory (not shown), and when the code is read from the memory, 24 refresh blocks are read in one sector.

The output of the code exchange circuit 39 is
It is supplied to the index insertion circuit 41. The index insertion circuit 41 inserts an index signal into the control data section of each sector so that it can be detected during reproduction that the non-refresh block is partially separated and recorded. The index signal is prepared by the index generation circuit 42 to which the code position signal from the refresh block control circuit 40 is supplied. The output of the index insertion circuit 41 is
The data is supplied to the A head and the B head via the multiplexer 43 and recorded on the magnetic tape 26.

When the refresh block and the non-refresh block are exchanged in the decoder, the PCM / DPC of the head data existing at the head of the macro block inside the video code shown in FIG.
A refresh sequence code included in the M determination code and the system control signal may be detected and used as an output signal of the refresh block control circuit 40.

FIGS. 5A and 5B show trace traces X _{1 to} X ₁₁ of the head during double speed reproduction. It should be noted that the refresh block G _n and the non-refresh block H are arranged in the frame of each track T _{1 to} T ₂₂ as in FIG.
_n is shown. Then, in the head trace at the time of double speed reproduction shown in FIG. 5, reproducible refresh blocks are shown in FIGS. 6 (a) to 6 (h) and FIGS. 7 (a) to 7 (c). 6 (a) to (h) and FIG. 7 (a) to
Frames 1 to 11 shown in (c) are 2 shown in FIG.
Speed indicates playable refresh block at a head trace loci X ₁ to X ₁₁ at the time of reproduction.

For example, in the frame 1, by performing the head trace X ₁ , it is possible to display the refresh block G1 in the upper half of the screen and the refresh block G ₂ in the lower half of the screen. Similarly, in the frames 2 to 11, the refresh block G ₃
Up to G ₂₂ can be reproduced. Therefore, when reproducible refresh blocks are stored in frames 1 to 11, the codes of all screen areas can be reproduced as shown in FIG. 7 (d).

The code subjected to inter-frame processing and the code subjected to intra-frame processing according to the contents of the image are put between the codes subjected to the intra-frame coding processing periodically. Then, these codes have no correspondence between the image area and the recording medium area.

In the present invention, the correspondence between a image areas and d × c × f recording medium areas is 1: 1.
May be associated with, or 1: 2, 2: 1
Any correspondence may be made, such as a correspondence in which a blank is put in the area of the recording medium. The recording medium is not limited to the magnetic tape 26 but can be a video disk, and in this case, one round of the disk corresponds to one track of the tape.

High-speed reproduction is possible by inserting a refresh block in a predetermined area on the VTR track, but it is necessary to prevent the code amount from exceeding the code amount recordable in the predetermined region.

The code amount of a predetermined refresh block is
When the amount of code that can be recorded in a predetermined area of the recording medium is exceeded, refresh is not performed at the position on the screen corresponding to the exceeded code.

Even if this is not avoided, since the refresh is performed from a certain position on the image, it is highly possible that the content of the image can be determined, but in order to perform the refresh more reliably. It is necessary to control the amount of code generated in the refresh block.

Therefore, the control of the code amount of the refresh block will be described in detail.

The two-dimensional DCT circuit will be described.

First, the image is divided into small blocks (N × N) each consisting of N pixels in the horizontal and vertical directions, and two-dimensional DCT is applied to each block. The size of N at this time is set to 8 to 16 from the conversion efficiency. In this embodiment, N =
8 is used.

The transform coefficient of the two-dimensional DCT is given by equation 1, and its inverse transform equation is given by equation 2.

[0058]

[Equation 1] Here, F (0,0) represents the coefficient of the DC component, and F (0,0)
(U, v) includes a high frequency horizontal frequency component as u increases, and includes a high frequency vertical frequency component as v increases.

First, the property of the coefficient of the DC component of F (0,0) will be described. F (0,0) corresponds to a DC component representing the average luminance value in the image block, and its average power is usually considerably higher than other components.

Further, when the DC component is roughly quantized, noise (block distortion) peculiar to the orthogonal transformation, which is visually noticeable as a large image quality deterioration, occurs. Therefore, F (0,0)
Is assigned a large number of bits (usually 8 bits or more) and is uniformly quantized.

Next, the conversion coefficient F (u, v) excluding the DC component
Describe the nature of. The average value of F (u, v) is
It becomes “0” excluding that of the DC component F (0,0).

In order to perform efficient encoding, when a certain number of bits are assigned to a small block of an image for encoding, a large number of encoded bits are allocated to the transform coefficient of the low frequency component, and conversely. By assigning a small number of coding bits to the transform coefficient of the high frequency component and performing the coding, it is possible to reduce the image quality deterioration and perform the coding with a high compression rate.

The image is converted into a small block of 8 × 8 = 64 pixels consisting of 8 pixels in both the horizontal and vertical directions, and a two-dimensional D
When CT is applied, the converted coefficients for each frequency component become 8 × 8 = 64 two-dimensional coefficients as shown in FIG. In FIG. 8, the upper left is the DC coefficient (direct current component). The other 63 are AC coefficients (AC components), and the spatial frequency increases toward the lower right. Since the AC component has a two-dimensional spread, it is converted into one dimension by zigzag scanning shown in the order of 0 to 63 at the time of encoding and transmission.

Here, the 64 DCT coefficients are converted to DCT _i
It is represented by [i = 0 to 63].

In the case of an image signal, the number of quantization bits for quantizing each pixel is often 8 bits.

The DCT coefficient of the output obtained by DCT converting the 8-bit pixel may be represented by 12 bits.

Next, the quantization will be described.

The above-mentioned 64 DCT coefficients are linearly quantized with a different step size for each coefficient position, using a quantization table that defines a quantization step size for each coefficient.

There are two kinds of quantization step setting methods, but basically the same method.

The first method is a method of transmitting a code indicating the quantization table using a quantization table in which a quantization step is determined for each of 64 DCT coefficients.

FIG. 9 shows an example of the quantization table. In the figure, q = 0 to q = 9 are quantization table codes that represent a quantization table, and by transmitting this code, the decoder can perform inverse quantization.

Further, 64 numbers arranged in a square represent the number of quantization bits, and have a correspondence relationship with the 64 two-dimensional coefficients shown in FIG. For example, 7 at the upper left of the quantization table for q = 0 indicates that the DC component is quantized with 7 bits.

Hereinafter, each coefficient is similarly quantized with the number of bits shown in the quantization table.

In the second method, first, 64 DCT coefficients are weighted by a weighting matrix.

After this, the quantization width data QS (Quantize-S
cale) is used to uniformly divide each coefficient and then quantize it. When transmitting, a code corresponding to the quantization width data is sent. Also, the weighting matrix has a predetermined default value. Furthermore, it is possible to transmit a specific type of weighting matrix.

As an example, MPEG. In I, 5 bits are assigned to the code of the quantization width data QS, and 32 types can be designated. Therefore, this value is set to QS _j [j
= 0 to 31].

Here, the quantization width data QS _{j will be} defined.

The coefficient value of the DCT is quantized with the maximum number of quantization bits, and j = 0 is used for quantization, and QS ₀ = 1.

Further, the case where the coefficient value of the DCT is not transmitted is represented by j = 31, and at this time, the number of quantization bits described later is QL ₃₁ = 0.

Here, j is named a quantization level.

FIG. 10 shows MPEG. The default value of the weighting matrix of the luminance signal used in I is shown.

In the figure, the 64 numbers of 8 × 8 are
There is a correspondence relationship with the 64 two-dimensional coefficients shown in FIG.
The weighting value for each DCT coefficient is shown.

In the encoder, each DCT coefficient is divided by the corresponding weighting value and the quantization width data QS.

The coefficients of 64 DCTs are converted into DCT _i [i = 0
~ 63] and each value of the weighting matrix is WEIG
HT _i [i = 0 to 63] Each value after quantization is Q _i [i = 0 to
63],

[0085]

[Equation 2] It is represented by.

The number of quantization bits at this time is

[0087]

[Equation 3] It is represented by.

An example is shown below.

MPEG. First vertical direction of I luminance signal
The th AC component is represented by DCT ₁ in FIG. 8 described above.

The value corresponding to DCT ₁ of the weighting matrix is WEIGHT ₁ = 16. This is shown in FIG.
It corresponds to the part marked with a circle. When the quantization width data QS ₀ = 1

[0091]

[Equation 4] Since the coefficient of DCT _i is represented by 12 bits, log ₂ D
The maximum value of CT _i is 12. The number of quantization bits at this time is

[0092]

[Equation 5] Becomes

FIG. 11 shows the maximum number of quantization bits required after passing through the weighting matrix when QS ₀ = 1. This figure is a matrix representing the number of quantization bits of 8 × 8 = 64, and each number indicates the number of quantization bits corresponding to each position of the DCT coefficient shown in FIG.

FIGS. 12 and 13 quantitatively show typical 9 types of quantization tables among the quantization tables when 32 types of quantization width data QS _j are set.

This table is based on the quantization width data QS in order to explain the case of using the above-mentioned second method regarding the quantization table.

Here, j = 31 is an example in which no data is generated at all, and corresponds to quantizing all coefficients with 0 bits. Further, j = 0 is the quantization width data QS ₀ = 1
Therefore, it is equivalent to quantization with a weighting table. That is, in this case, the bit allocation is based on the weighting table shown in FIG.

12 and 13, the horizontal axis is DCT.
64 coefficients of the above, which correspond to the order of the zigzag scanning shown in FIG. The vertical axis is D
In each coefficient of CT, the number of bits to be transmitted is shown.

When quantizing the DCT coefficient, M
SB (Most Significant Bit) to LSB (Least Sign
ificant Bit) exists. When limiting the number of bits to be transmitted, naturally, the MSB is preferentially transmitted.

As described above, when the number of quantization bits for the DC component is reduced, block distortion becomes conspicuous, so the DC component is treated separately.

MPEG. In the case of the luminance signal of I, the maximum value of the AC component is 8 bits as described above.

The number of quantization bits and the quantization width data will be quantitatively described with reference to FIGS.

The generated code amount becomes maximum when j = 0, and as j increases, the generated code amount decreases and j =
It becomes 0 at 31 and no code is generated.

It is possible to control the code amount generated by controlling the quantization width data.

There are two types of code amount control methods. The first method is a method of controlling the quantization level as described above. In this case, since the generated code amount of the refresh block is suppressed, the image quality of the refresh block itself is deteriorated. However, in the next frame, since the difference between the intra-frame processed signal of the refresh block and the video signal of the next frame is sent, the image quality is only momentarily degraded. This method will be described in detail later.

The second method divides the code, which has been quantized once, into two, and determines the code amount of the MSB or the low frequency component by VTR.
This is a method that keeps the code amount that can be read out at high speed on a recording medium such as.

The control of the encoded information amount when the first method is used will be described below.

When the video signal is high-efficiency coded by using the variable length coding as in the present embodiment, the generated information amount is generally not constant. This is because the amount of information contained in the video signal varies with time.

On the other hand, when a fixed rate transmission system is used, coding control is required to keep the coded information amount constant.

The general method of fixed rate conversion is to prepare a buffer memory at the output of the encoder, input it at a variable rate to this buffer memory, and output at a fixed rate to smooth the encoded information amount. Is. Since the amount of data in the buffer memory changes according to the amount of input information, overflow or underflow may occur. In order to prevent this, when overflow or underflow is likely, the encoding parameter is changed so as to reduce or increase the encoded information amount, respectively. For example, the quantization characteristic may be made coarser or finer.

The larger the capacity of the buffer memory is, the higher the smoothing effect is, but there is a limitation on coding delay and cost.

Further, since a relatively small buffer memory allows finer control of encoding depending on the local nature of the image, a buffer memory of about 1 frame may be used.

The conventional example also controls the amount of coded information in the same manner. FIG. 32 is a diagram showing control of the coded information amount in the conventional example. In the figure, the occupancy of the FIFO circuit 17 which constitutes the buffer memory is represented by the quantization level setting circuit 44.
To the quantization level j of the quantization circuit 15.
, The quantization width data is set by setting
Quantize the T coefficient.

The quantization level for each macroblock is set by feeding back the occupancy rate of the FIFO described above.

Further, the fine adjustment of the quantization level can be performed in units of super blocks. This allows the quantization level to be set in the direction of decreasing the generated code amount based on the code amount generated in one macroblock. This is for extreme cases such as scene changes of complicated images,
This is to avoid a buffer overflow.

In the conventional example, since one refresh block exists in the macro block and is controlled by the rate buffer occupancy, the refresh block alone does not control the code amount.

That is, the code amount of the refresh block is arbitrarily determined.

On the other hand, in a recording medium such as a VTR, when special playback is realized using refresh blocks, the code amount of the refresh blocks is suppressed to a predetermined code amount so that the screen can be refreshed reliably at a constant cycle. ..

Regarding this, Japanese Patent Application No. 3-250671
No. etc.

There are the following two methods depending on the special reproduction method of the VTR.

The first method is a method using DTF as the servo system of the VTR. Let α be the maximum recording code amount that can be recorded on P tracks formed in one scan, and refresh the area of 1 / c of the image of one frame when recording a video signal with a head scan of c times per frame. It is necessary to keep the maximum code amount of the block below the above-mentioned α.

The second method is a case where DTF is not used. When the DTF is not used and the high-speed reproduction speed is i, 1 / th of P tracks formed in one scan
The area of i will be traced.

Similarly to the above, when the maximum code amount that can be recorded on P tracks formed in one scan is α, and when a video signal is recorded by scanning c times per frame, 1
It is necessary to limit the maximum code amount in the 1 / c × i area of the refresh block of the frame to α / i or less. In this case, the case where an extremely wide head width is not used as the special reproduction head is shown.

The control of the code amount will be specifically described.

First, the method used in the conventional example will be described in detail. In the method using the rate buffer, as shown in FIG. 14, an equal capacity rate buffer is provided in the encoder and the decoder.

The input / output code amount of these buffers and the buffer occupancy will be described with reference to FIG.
Reference numeral a in FIG. 14 indicates an input signal of the rate buffer b of the encoder. This signal is the output signal of the variable length coding circuit 16 of the encoder. A characteristic of this signal is that each block is input at a constant cycle, but the generated code of each block is a variable length code, so that it has a variable length rate. Further, the output signal c of the rate buffer of the encoder is transmission data, and the code is output at a fixed rate. Further, the input signal d of the rate buffer e of the decoder is a fixed rate code input, and the output signal f is a variable rate code output.

The characteristics on the encoder side and the decoder side will be described in detail with reference to FIGS. 15 and 16. The horizontal axes in FIGS. 15A to 15C and 16A to 16C indicate frame numbers. Here, FIG.
16 (a) to 16 (c) and FIGS. 16 (a) and 16 (b) are the same as the input frame numbers, but the frame numbers in FIG. 16 (c) are shifted by 8 frames. This is necessary in order to absorb the fluctuation of the delay time of the transmission code of the encoder and the decoder due to the use of the variable length code.

FIGS. 15A to 15C and FIGS. 16A to 16C.
The vertical axis of (c) indicates the code amount. In this example, the capacity of the rate buffer is 4 Mbits, and the transmission code amount per frame is 0.5 Mbits / frame. 15 (a) to 15 (c) are on the encoder side, FIG.
6 (a) to 6 (c) show the characteristics on the decoder side.

FIG. 15A shows the generated code amount per frame. The broken line in the figure indicates the capacity of the rate buffer for reference. Since the variable length code is used, the generated code amount of each frame differs depending on the frame. The frame number represented by F _n. F _{1 to} F ₉ show examples of code generation when the buffer overflows and underflows. A code of 4.5 M bits is generated in F ₁ , and the generated code is set to 0 in F _{2 to} F ₉ .

The maximum value of the generated code amount of each frame is determined by the sum of the buffer capacity and the transmitted code amount. In this example, the buffer capacity is 4 Mbits, and the transmitted code amount per frame is 0.5 [Mbits. / Frame], the maximum possible code amount per frame is 4.5 Mbits.
F _{20 to} F ₃₀ are examples in which the generated code amount of each frame is controlled by the occupancy of the buffer.

FIG. 15B shows the occupancy of the encoder buffer. In this example, the buffer capacity is 4M
The capacity of the buffer is indicated by a broken line. F
_{Since a} large amount of generated code is generated in ₁ frame, F
_At the time of ₁ , a buffer overflow has occurred. Further, since a state in which no code is generated continues from F _{2 to} F ₉ , the buffer underflow occurs at the time of F ₉ .

FIG. 15C shows the transmission code amount from the encoder. A solid straight line A drawn diagonally in the figure shows the cumulative transmission code amount. This inclination indicates the amount of transmitted code per frame. In this example, 0.5 M bits are transmitted per frame time. Frame rate is 30
In the case of [Hz], 30 × 0.5 [M / Frame] = 15
The transmission code amount is [Mbps]. The broken line shows the maximum value determined by the maximum capacity of the buffer.

The polygonal line shown in FIG. 15C is
The cumulative generated code amount is shown. That is, FIG. 15 (a)
Is the integrated value of the generated code amount per frame.
When the accumulated generated code amount contacts the broken line, the buffer overflows, and when it contacts the solid line, the buffer underflows. Also, the dotted line drawn horizontally between the cumulative generated code amount and the cumulative transmitted code amount indicates the delay time in the encoder buffer when transmitting the generated code, and the longer one indicates the longer time until transmission. This shows that.

In FIG. 16 (a), the solid line B shows the cumulative received code amount. This solid line B is shown in FIG.
Is the same as the real straight line A. The polygonal line indicates the projection code amount of each frame when the image is output. This is shown in FIG.
This corresponds to a value obtained by integrating the projection code amount per frame in (c). Also, the dotted line drawn horizontally represents the delay time when the received code is projected, and the sum of the delay time in the encoder and the delay time in the decoder are all equal, and the buffer delay shown in FIG. Time (Buffer D
elay).

FIG. 16B shows the occupation rate of the buffer of the decoder. Here, FIG. 15B and FIG.
Compare with (b). Figure 1 shows only the buffer delay time.
When 5 (b) is shifted, FIGS. 15 (b) and 16 (b) are vertically inverted. That is, an encoder overflow results in a decoder underflow, and an encoder underflow results in a decoder overflow.

FIG. 16C shows the projected code amount per frame of the projected code. FIG. 15A and FIG.
6 (c) is delayed by the buffer delay time of the encoder and the decoder.

When the subscriber changes the channel, it is possible to output the video after accumulating the code of the required code amount in the buffer of the decoder. This accumulated amount is
It is equal to the value for accumulating the received code amount only for the time shown by the dotted line in FIG. This value has a corresponding relationship with the NMP signal of the conventional example. That is, the decoder may store the code in the buffer for the time determined by the NMP signal and then output the video.

As shown in F ₁ of FIG. 15A, when the maximum code amount occurs in the first frame, the maximum buffer delay time occurs in the decoder buffer.
In this case, it is possible to output a normal video signal after accumulating the received code in the buffer for the time indicated as buffer delay in FIG. In this case, a normal video signal is output after the buffer of the decoder is filled with the reception code.

That is, the received codes are accumulated from F _{0 to} F ₈ and a normal video signal is output after the initialization state filling the buffer memory is completed. When the projection code is output at F ₁ in FIG. 16C, the buffer of the decoder is underflowed. In addition, FIG.
When the state in which the projection code is not output continues from F _{1 to} F _{9 in} (c), the buffer of the decoder overflows at F ₉ . This coincides with the state in which the buffer state of the encoder is delayed by 8 frames and the overflow and underflow are inverted.

When the subscriber changes the channel, in order to output a normal video signal, it is necessary to store the code in the buffer of the decoder for the time according to the NMP signal. It is possible to output an incomplete image as shown by the dotted line in 16 (c).

FIG. 17 shows an example of the relationship between the occupancy rate of the buffer and the increase / decrease of the quantization level set for each macroblock. The quantization level is not changed while the buffer occupancy rate is at a predetermined value, and the quantization level is increased or decreased when the buffer occupancy exceeds the predetermined value. In FIG. 17, when the buffer occupancy is 45 to 55%, the quantization level is not changed,
When this value is exceeded, the quantization level is changed. This makes it possible to control the rate of the buffer.

Since the quantization level is roughly quantized when the value of j is large and the generated code amount is small, the quantization level is lowered when the buffer occupancy is small, and the quantization level is decreased when the buffer occupancy is large. Operate in the raising direction.

FIG. 18 is a diagram showing another embodiment of the present invention. In the figure, the same components as those in the conventional example are designated by the same reference numerals. Further, the present embodiment is a minimum change in consideration of minimizing the difference from the conventional example, but it goes without saying that the block configuration can be variously changed without changing the gist of the present invention. Yes.

The gist of the present invention is to keep the generated code amount of the refresh block for performing the intra-frame processing in the entire area of the screen in a cycle of f frames to a predetermined code amount or less determined from the recording medium such as VCR.

In order to realize this purpose, in this embodiment, the code amount of the refresh block is calculated independently, and the quantization level of the refresh block is set using this value. The configuration is such that the refresh block code amount calculation circuit 45 and the refresh block quantization level setting circuit 4
6 was used as the main configuration other than the conventional example. The refresh block code amount calculation circuit 45 calculates the code amount of the refresh block for a predetermined period.

A method of calculating the code amount of the refresh block will be described in detail.

First, the output of the quantization circuit 15 is input to the variable length coding circuit 16. In this circuit, first, the zigzag scanning circuit 16a reads the 8 × 8 DCT coefficient by the scanning method shown in FIG. To enter.

Further, the number of consecutive 0 coefficients and the amplitude of the non-zero coefficient are input to the block code amount calculating circuit 47. The block code amount calculation circuit 47 calculates the generated code amount using the ROM that stores the table shown in FIG.

FIG. 19 shows the amplitude of the non-zero coefficient on the horizontal axis and the number of consecutive zero coefficients on the vertical axis, which is also used in the conventional example. Also, the numbers in the frame indicate the number of bits of the code. By adding the number of bits of this code, the generated code amount can be calculated in block units or super block units. Further, the generated code amount of the refreshed super block, that is, the refresh block is output from the block code amount calculation circuit 47, and the refresh block code amount calculation circuit 45 sequentially adds the code amounts of the refresh blocks. In this embodiment, the addition is performed during the period of 120 super blocks that are going to be put in one sector on the tape.

1 is used without using DTF as the VTR servo.
When a video signal is recorded by c = 1 head scan per frame and i = 2 × speed is realized as a special reproduction speed,
A case will be described in which the code amount of the refresh block is calculated for each 1 / c × i = 1/2 area of one frame of video. When the code amount of this refresh block is the maximum recording code amount α that can be recorded on P tracks formed in one scan, the code amount of the refresh block in the area of 1/2 of one frame is α / c × i = Refresh block quantization level setting circuit 5 so that it becomes α / 2 or less
2 sets the quantization level.

The refresh block quantization level setting circuit 46 inputs the macro block quantization level determined by the refresh block cumulative code amount and the buffer memory occupancy rate and the output coefficient of the DCT circuit 14, and outputs the refresh block quantization level. ..

First, the control of the code amount of the refresh block will be described.

FIG. 20, which will be described in detail later, shows a setting method when the quantization level is set by the output signal of the refresh block code amount calculating circuit 45. In this example, the case where the head scan of the VTR is one scan and the average code amount of the video signal of one frame is recorded will be described. In addition, a case will be described in which the special reproduction speed is doubled. In the embodiment, since there are 240 refresh blocks per frame, 120 refresh blocks are recorded per sector. This will be described in detail.

21 (a) and 21 (b) show a refresh block in one screen and a dividing method when the refresh block is further divided. F _n shown in FIG. 21A shows the screen of the nth frame. Further, G _n represents a refresh block in the nth frame. This refresh block is 240
There are individuals. In addition, G shown on the left side of the screen
_n (0) and G _n (1) indicate refresh blocks obtained by dividing 240 refresh blocks into two equal parts in the vertical direction. That is, G _n (0) indicates 120 refresh blocks existing above the screen among the G _n refresh blocks. G _n (1) is
The refresh block in the lower area of the screen is shown and includes 120 refresh blocks.
FIG. 21B shows the refresh block of frame number F _{n + 1} , and the definitions of G _{n + 1} (0) to G _{n + 1} (1) are the same as in FIG. 21 (a). ..

Next, the track pattern of the VTR will be described. FIG. 22 shows a track pattern on the magnetic tape 26. T _{0 to} T ₁₁ indicate tracks recorded by using the rotary head 30. Here, a case where the average generated code amount of one frame is recorded on one track will be described. That is, the case of C = 1 described above will be described. This corresponds to the case where the b = 240 refresh blocks are recorded on one track. That is, the refresh block G having the frame number F _n
n will be recorded on track T _n .

In this structure, when reproducing at a double speed, the reproducing head will cross two tracks. Therefore, one track is divided into two equal parts.
While reproducing the area of 2, the reproduction signal is obtained over two tracks. Here, if one part divided into two is called a sector, one track is formed per frame, so that two sector numbers S ₀ and S ₁ are assigned as shown in FIG.

Incidentally, in general, an area obtained by dividing one track into approximately equal parts is named a sector.

In order to realize high-speed reproduction at i-times speed, the head is to straddle i tracks, so that one track is reproduced in an area of 1 / i. Therefore, assuming that the maximum high-speed playback speed is i _max , i _max ≦
Set to the relationship of d. Then, the sector names are S _{0 to} S _d-1
Express with.

Next, the relationship between the refresh block and the sector will be described. When recording the refresh block G _n of the frame number n in one track T _n, G _n (0)
... S ₀ , G _n (1) ... S ₁ is recorded.

If the number of refresh blocks in one sector is evenly arranged, the number of refresh blocks in one sector is as follows. That is, 1
If the number of refresh blocks per frame is b, the number of tracks for recording b refresh blocks is c, the number of track divisions is d, and the number of refresh blocks in one sector is e, then e = b / c × d Become. That is, e = 240/1 × 2 = 120.

In FIG. 22, the head traces X _{0 to} X ₄ represent the head locus at double speed. That is, in the head trace X _0, sector S ₀ of the track T ₀ (refresh block G ₀ (0)), the sector S ₁ of the track T ₁ (refresh block G
₁ (1)), sector S ₀ (refresh block G ₂ (0)) of track T ₂ can be reproduced.

Here, since the recording capacity which can be recorded in the sectors S ₀ and S ₁ of the recording medium on the tape is determined,
Within this recording capacity, the refresh block G _n (0),
The generated code amount of G _n (1) must be suppressed.

In FIG. 20, the horizontal axis represents the refresh block number. In this embodiment, the refresh block number of the sector 0 and the refresh block number of the sector 1 are shown to record the refresh block of one frame in two sectors. Further, in this example, the recording code amount α / 2 of one sector is not exceeded in 120 refresh blocks.

The vertical axis of FIG. 20 shows the code amount of the refresh block. The maximum code amount is α / 2 as described above.
Set to. Here, it is assumed that α / 2 = 250 K bits. In FIG. 20A, the solid line C is the target code amount of the refresh block, and the generated code amount is controlled so as not to exceed this line. Since this solid line C is an example for control, it need not be a straight line, and what is necessary is to suppress the generated code amount per sector to α / 2. The polygonal line D is a line showing an example of changes in the refresh block cumulative code amount. This shows the output signal of the refresh block code amount calculation circuit 45. The quantization level is determined so that the refresh block target code amount (solid line C) is not exceeded.

FIG. 23 shows macroblock quantization levels,
An example of setting the quantization level of the refresh block will be described.

As shown in FIG. 18, first, the quantization level of the macroblock is determined by the occupation rate from the buffer memory. For the quantization level of this macroblock,
By increasing the quantization level as necessary, the quantization level of the refresh block is set only in the direction of decreasing the generated code amount. The quantization level correction level indicating the quantization level of the difference between the quantization level of the macro block and the quantization level of the refresh block can be transmitted as additional data.

In FIG. 23, the horizontal axis represents the quantization level j = 31 to 0 of the macro block. It shows a state where no code is generated when j = 31 and a state where the maximum code amount is generated when j = 0. Further, the numbers entered below this are examples of the number of bits used to indicate the quantization level correction level.

The vertical axis represents the quantization level j = 31 to 0 of the refresh block. A circle mark in the drawing indicates a quantization level that can be taken as a refresh block. In each case, a quantization level that reduces the code generation amount is assigned to the macroblock quantization level.

Since the output signal of the DCT circuit 14 is input to the refresh block quantization level setting circuit 46, by comparing with the refresh block accumulated code amount, the quantum value is set so that the refresh block target code amount is not exceeded. It is possible to choose a chemical table.

Details will be described with reference to FIG.

FIG. 20 (b) is an enlarged view of the horizontal axis of FIG. 20 (a). Refresh block number 80 to 8
A method of determining the quantization level to 1 will be described with reference to FIG. First, it is assumed that the refresh block code amount calculation circuit 45 has calculated the code amounts up to the refresh block number 80, which is the code amount indicated by E in FIG. Further, it is assumed that the target code amount is determined by the refresh block number, and the refresh block number 81 has the code amount indicated by F in FIG.

Assuming that the macroblock quantization level is set at j = 15, if the quantization level relationship shown in FIG. 23 exists, j = 15, 19, 23, 27 is set as the refresh block quantization level. It is possible.

Since the refresh block quantization level setting circuit 46 is supplied with the coefficient signal obtained by DCT of the video signal as the output signal of the DCT circuit 14, the quantization level is set to j = 15, 19, 23, 27. The generated code amount when set can be calculated. The results are G, H,
Suppose it is decided by I and J. This generated code amount G, H, I,
By comparing J with the target code amount F, it is possible to select the refresh block quantization level j = 23 which is the code amount of I.

In this way, by controlling the code amount of the refresh block and inputting it to the above-mentioned code exchange circuit 39 and index insertion circuit 41 for recording, it is possible to surely perform refresh at the time of high speed reproduction. Become.

The present invention is not limited to the above embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0175]

As described in detail above, according to the present invention,
It is possible to provide an extremely good band compression processing device that can easily obtain a good reproduced image during high-speed reproduction.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a band compression processing device according to the present invention.

FIG. 2 is a timing chart shown for explaining the operation of the embodiment.

FIG. 3 is a view showing a relationship between refresh blocks having frame numbers F ₅ and F ₆ and non-refresh blocks in the embodiment.

FIG. 4 is a diagram showing a track pattern in the same embodiment.

FIG. 5 is a diagram showing a head trace locus during double speed reproduction in the example.

FIG. 6 is a diagram showing refreshable refresh blocks of frames 1 to 8 in the embodiment.

FIG. 7 is a diagram showing a reproducible refresh block of frames 9 to 11 and a refresh block in which 11 frames are accumulated in the embodiment.

FIG. 8 is a diagram showing a scan order when performing zigzag scanning of DCT coefficients.

FIG. 9 is a diagram showing an example of a quantization table.

FIG. 10 is a diagram showing an example of a weighting table.

FIG. 11 is a diagram showing an example in which the same weighting table is converted into the number of bits.

FIG. 12 is a diagram showing the number of generated bits based on a quantization table.

FIG. 13 is a diagram showing the number of generated bits based on a quantization table.

FIG. 14 is a diagram showing a configuration of a rate buffer.

FIG. 15 is a diagram showing an operation of a rate buffer on the encoder side.

FIG. 16 is a diagram showing the operation of the rate buffer on the decoder side.

FIG. 17 is a diagram showing increase / decrease in buffer occupancy and quantization level.

FIG. 18 is a diagram showing another embodiment of the present invention.

FIG. 19 is a diagram showing a generated code amount when variable length coding is performed.

FIG. 20 is a diagram showing an operation of controlling the code amount of a refresh block.

FIG. 21 is a diagram showing frame numbers F _n and F _{n + 1} in the same embodiment.
FIG. 6 is a diagram showing the relationship between refresh blocks and non-refresh blocks of FIG.

FIG. 22 is a diagram showing a head trace locus during double speed reproduction in the example.

FIG. 23 is a diagram showing an example of quantization levels of a macro block and a refresh block.

FIG. 24 is a block diagram showing a conventional band compression system.

FIG. 25 is a diagram showing a format of a signal transmitted from the conventional system.

FIG. 26 is a diagram showing refresh blocks that can be reproduced in frames 1 to 8 during normal reproduction in the conventional system.

FIG. 27 is a diagram showing refreshable blocks that can be played back from frames 9 to 11 and refresh blocks that have accumulated 11 frames during normal playback in the conventional system.

FIG. 28 is a diagram showing a track pattern in the conventional system.

FIG. 29 is a diagram showing a head trace locus during double-speed reproduction in the conventional system.

FIG. 30 is a diagram showing refresh blocks capable of reproducing frames 1 to 8 during double speed reproduction in the conventional system.

FIG. 31 is a diagram showing refreshable blocks that can be played back from frames 9 to 11 and refresh blocks that have accumulated 11 frames during double-speed playback in the conventional system.

FIG. 32 is a view showing another conventional example.

[Explanation of symbols]

11 ... Input terminal, 12 ... Subtraction circuit, 13 ... Motion evaluation circuit, 14 ... DCT circuit, 15 ... Quantization circuit, 16 ... Variable length coding circuit, 17 ... FIFO circuit, 18 ... Output terminal,
19 ... Inverse quantization circuit, 20 ... Inverse DCT circuit, 21 ... Addition circuit, 22 ... Frame delay circuit, 23 ... Motion compensation circuit,
24, 25 ... Switch, 26 ... Magnetic tape, 27 ... Input terminal, 28 ... SYNC signal detecting circuit, 29 ... Track forming signal generating circuit, 30 ... Rotating drum, 31 ... Track forming control circuit, 32, 33 ... Input terminal, 34, 35 ... Decimator, 36 ... Input terminal, 37 ... Multiplexer, 38
... track, 39 ... code exchange circuit, 40 ... refresh block control circuit, 41 ... index insertion circuit,
42 ... Index generating circuit, 43 ... Multiplexer,
44 ... Quantization level setting circuit, 45 ... Refresh block code amount calculating circuit, 46 ... Refresh block quantization level setting circuit, 47 ... Block code amount calculating circuit

Claims (4)

[Claims] 1. A frame in which a (a is a positive integer) image area is formed in a video signal of one screen, and the video signal is subjected to intraframe coding processing using information in the frame. An intra-processed signal and an inter-frame processed signal that has been subjected to inter-frame encoded processing using difference information between frames are created, and after the intra-frame encoded processing, the inter-frame encoded processing is applied, and this signal A band compression unit that adaptively repeats the processing method according to the motion evaluation of the input video signal, and f frames (f is an integer of f ≧ 2) as a cycle, and b units of the a regions are set for each frame Refresh encoding processing means for periodically performing the intraframe encoding processing on the signal in the image area, a circuit for calculating the generated code amount of the refresh block subjected to the refresh encoding processing, and a predetermined number of refreshes So as not to exceed the predetermined maximum encoding amount in block, band compressor system being characterized in that and means for controlling the generation code amount of the refresh blocks. 2. A frame in which a (a is a positive integer) image region is formed in a video signal of one screen, and the video signal is subjected to intraframe coding processing using information in the frame. An intra-processed signal and an inter-frame processed signal that has been subjected to inter-frame encoded processing using difference information between frames are created, and after the intra-frame encoded processing, the inter-frame encoded processing is applied, and this signal A band compression means that adaptively repeats the processing method according to the motion evaluation of the input video signal; and a period of f frames (where f is an integer of f ≧ 2) as the period of a signals of the a image regions. Refresh code processing means for performing a coding process, a circuit for calculating the generated code amount of the refresh coding process, and the refresh code by the output signal of the refresh code generated code amount calculation circuit. A circuit for setting the quantization levels of the process, the code amount calculation circuit for calculating the sum of the code amount of the refresh encoding a non-refresh encoding process is not applied the refresh encoding process,
A band compression processing apparatus comprising a circuit for setting a quantization level of the non-refresh coding processing with an output signal of the code amount calculation circuit. 3. The signal processing means having the code amount control means for the refresh block is provided in a magnetic recording / reproducing apparatus, and the predetermined maximum code amount means 1 of the head.
2. The band compression processing apparatus according to claim 1, wherein the recording code amount α of the P track formed by scanning. 4. An apparatus for recording an average code amount per frame by c-scan, wherein the high-speed reproduction speed is i (i is a positive integer), the high-speed reverse reproduction speed is k = 2-i,
Α / c for the print code amount α per head scan
2. The band compression processing device according to claim 1, wherein the generated code amount of b / c × i refresh blocks of the b blocks is suppressed within a maximum code amount of × i.