JPH05268520A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To improve the sensitivity of an image pickup element by increasing the channel length of a load MOS transistor(TR) connected to each pixel signal line wired in a vertical direction in an FWA(Floating Well Amplifier) amplifier type solid-state image pickup element, and thereby improving the property of a constant current. CONSTITUTION:A load MOS TR 6 connected to each pixel signal line 4 [4O, 4E] is formed within a width L2 by two picture elements in a horizontal direction. Furthermore, the load MOS TRs 6O connected to every other pixel signal line 4O are arranged to a 1st column close to an image pickup area 30 and load MOS TRs 6E connected to every other pixel signal line 4E are arranged to a 2nd column remote from the image pickup area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device.

[0002]

2. Description of the Related Art In response to the demand for higher resolution of solid-state image pickup devices, research and development of internal amplification type solid-state image pickup devices for amplifying optical signal charges for each pixel have been advanced. Various types of image pickup device structures such as a static induction transistor (SIT), an amplification type MIS imager (AMI), and a charge modulation device (CMD) are known as main ones of the internal amplification type solid-state image pickup device.

[0003]

On the other hand, signal charges such as holes obtained by photoelectric conversion are accumulated in the P-type well region of an N-channel MOS transistor, which is a unit pixel, and the potential fluctuation of this P-type well region, so-called An amplification type solid-state imaging device called an FWA (Floating Well Amplifier) type has been developed that reads out a change in channel current due to a change in potential of a back gate.

In this FWA type amplification type solid state image pickup device, M
Similar to the OS type solid-state image sensor, a unit pixel is selected by a vertical scanning circuit through a vertical selection line, and a pixel signal is obtained from a source follower circuit composed of a unit pixel and a load MOS transistor connected to the end of the pixel signal line. The pixel signal for one horizontal scanning line is stored in the sample hold circuit, and the signals of each pixel are output by sequentially turning on the switching MOS transistors connected to the horizontal scanning circuit. By performing this operation for each horizontal scanning line while sequentially changing the vertical selection line for selecting, the signal output of the solid-state imaging device is obtained.

In this FWA amplification type solid-state imaging device, a load MOS transistor 6 having a source 41, a drain 42 and a gate 43 is connected to a pixel signal line 4 connected to each unit pixel 1 as shown in FIG. It is arranged in a row below the imaging region 30 along the horizontal direction.

By the way, in the case of a high-definition television of 1/2 inch optical system, for example, the load MOS transistor 6 connected to each pixel signal line 4 arranged in the vertical direction is set to 1
If formed with a pixel pitch, the load MOS transistor must be formed within a width of 3.65 μm. The gate length (so-called channel length) L ₁ of the load MOS transistor 6 in this case can be only about 0.5 to 0.7 μm, and the short channel effect strongly acts, and the drain current I _ds −drain of FIG. As shown by the voltage V _ds characteristic, the load MO
The constant current characteristic of the S transistor 6 is significantly deteriorated. As a result, the gain of the source follower circuit formed by the unit pixel (driving MOS transistor) 1 and the load MOS transistor 6 connected to the pixel signal line 4 is lowered, and the sensitivity of the FWA amplification type solid-state imaging device is lowered. ..

In view of the above points, the present invention is to improve the constant current characteristic by controlling the short channel effect of the load transistor and improve the sensitivity of the image pickup device even when the resolution is increased. An element is provided.

[0008]

According to the present invention, for example, an image pickup region 30 in which unit pixels 1 made of transistors are arranged in a matrix, a vertical scanning circuit 3 for selecting unit pixels 1 in the vertical direction, and unit pixels in the horizontal direction are provided. In the solid-state imaging device having the horizontal scanning circuit 5 for selecting 1, the pixel signal lines 4 wired in the vertical direction, and the load transistor 6 connected to each pixel signal line 4, two pixels in the horizontal direction are provided. The load transistor 6 is formed within the width d _{H of the} minute.

Further, the load transistors 6 connected to every other pixel signal line 4 are arranged at a position close to the image pickup region 30, and the load transistors 6 connected to the other every other pixel signal line 4 are picked up. It is arranged to be located far from the region 30.

[0010]

In the present invention, the channel length L ₂ of the load transistor 6 can be increased by forming the load transistor 6 connected to the pixel signal line 4 within the width d _H of two pixels.

Further, the load transistor 6 _O connected to every other pixel signal line 4 _O is arranged at a position close to the image pickup region 30, and the load transistor 6 _O connected to every other pixel signal line 4 _E. By arranging 6 _E at a position far from the imaging region 30, that is, by arranging in a so-called checkered pattern,
The channel length L ₂ of the load transistor 6 can be increased.

Therefore, the load transistor 6 [6 _O ,
6 _E ], the short channel effect is controlled and its constant current characteristic is improved, so that the gain of the source follower circuit is increased and the sensitivity of the image pickup element is improved.

[0013]

Embodiments of the solid-state image sensor according to the present invention will be described below with reference to the drawings. It should be noted that this example is a case where it is applied to an FWA-type amplification type solid-state imaging device.

FIG. 2 shows a circuit configuration example of the FWA type amplification type solid-state image pickup device. In the figure, reference numeral 1 denotes a unit pixel formed by a MOS transistor element, which will be described later, and reference numeral 30 denotes an imaging region in which the unit pixel 1 is two-dimensionally arranged in a matrix. The gate of each unit pixel 1 is commonly connected to each corresponding vertical selection line 2 from the vertical scanning circuit 3 for each pixel of one horizontal line,
The source of each unit pixel 1 is commonly connected to the corresponding pixel signal line 4 for each pixel of one vertical line. A load MOS transistor 6 is connected to the end of each pixel signal line 4, and the unit pixel 1 and the load MOS transistor 6 form a source follower circuit.

The drains of the unit pixels 1 are commonly connected to the pixels of one vertical line and connected to the power supply V _DD .
The pixel signal line 4 is connected to the horizontal signal line 11 via the sample hold circuit 7 and the switching MOS transistor 8, and the gate of each switching MOS transistor 8 is connected to the horizontal scanning circuit 5. Power supply V _DD and signal line 4
A switching MOS transistor 9 for resetting is connected in between.

In the FWA amplification type solid-state image pickup device, as described above, the unit pixel 1 is selected by the vertical scanning circuit 3 through the vertical selection line 2, and the unit pixel 1 and the load MO are selected.
A pixel signal is obtained from a source follower circuit composed of an S transistor 6, a pixel signal for one horizontal scanning line is stored in a sample hold circuit 7, and a switching MOS transistor 8 is sequentially turned on by the horizontal scanning circuit 5. Then, the signal of each pixel 1 is output from the horizontal signal line 11.

By performing this operation for each horizontal scanning line while sequentially changing the vertical selection line 2 to be selected, the signal output of the solid-state image pickup device is obtained. However, 2 during the horizontal blanking period
The readout operation is performed by changing the vertical selection line that is selected twice, that is, the signals of two pixels that are vertically adjacent to each other are read out, passed through the sample hold circuit 7, and then the signals of the two pixels are combined to perform field readout. ..

FIG. 4 is a sectional view of the unit pixel 1. The unit pixel 1 includes a P-type silicon substrate 2 of the first conductivity type.
A first conductivity type P-type well region 23 is formed on the N-type well region 22, and a surface of the P-type well region 23 is formed on the N-type well region 22. Is formed by forming an N-type source region 24 and a drain region 25, and forming a gate electrode 27 on the P-type well region 23 between the source region 24 and the drain region 25 via a gate insulating film 26. 28 is a source electrode and 29 is a drain electrode.

The gate electrode 26 of the unit pixel 1 is connected to the vertical selection line 2 from the vertical scanning circuit 3, the drain electrode 29 is connected to the power source V _DD , the source electrode 28 is connected to the pixel signal line 4, The equivalent circuit shown in FIG. 3 is formed.

In this unit pixel 1, signal charges generated by photoelectric conversion due to light reception, holes 31 in this example, are accumulated in the P-type well region 23, and become the accumulation state in the potential distribution chart of FIG. 7 (see FIG. 7A). .. This accumulated hole 3
1 controls the channel current 32 in the read operation (see FIG.
(See B potential distribution), that is, if a large number of holes 31 are accumulated, the channel current increases, and the potential of the source of the source follower circuit configured by the unit pixel 1 and the load MOS transistor 6 changes. Is read out as a signal output.

5 and 6 show the operation timing of the FWA amplification type solid-state image pickup device.

FIG. 5 shows an enlarged timing chart of each applied voltage and signal output in the horizontal blanking period T _HB . φ _{VO and} φ _VE are selected and two vertical selection lines 2 _O ,
2 _E applied voltage, φ _Vn is applied voltage to non-selected vertical selection lines, V _{su b} is substrate applied voltage, φ ₁
Is an applied voltage applied to the gate of the switching MOS transistor 9, φ _VGG is an applied voltage applied to the gate of the load MOS transistor 6, and S is a signal output. Further, φ _{PO and} φ _PE represent electronic shutter pulses.

Two pixel rows corresponding to one horizontal scanning line are read separately in the first half and second half of the horizontal blanking period T _HB as indicated by the applied voltages φ _{VO and} φ _VE of the vertical selection lines, respectively.

That is, first, when receiving light, the applied voltage to all the vertical selection lines 2 is set to a high level (for example, 5 V), and the substrate voltage V _sub
Is 0 V, the load MOS transistor 6 is in an OFF state (φ _{VG G} is 0 V, for example), and the switching MOS transistor 9 is in an ON state (φ ₁ is 5 V, for example). As shown by, the holes 31 generated by photoelectric conversion are accumulated in the P-type well region 23 below the gate region of each unit pixel 1.

Next, in the first half of the horizontal blanking period T _HB , two adjacent vertical selection lines 2 selected.
The vertical selection line 2 _E to be read out in the latter half of [2 _O , 2 _E ] is set to a low level (φ _VE is 0 V, for example), and the switching MOS transistor 9 is off (φ ₁ is 0 V, for example). .. Then, by turning on the load MOS transistor 6 (φ _VGG is, for example, 5 V),
As shown by the potential distribution in FIG. 7B, the signal of the pixel 1 in the first row of the two pixel rows corresponding to one horizontal scanning line is output to the pixel signal line 4.

During the read operation, the vertical selection line 2
_In the pixel 1 in the second row in which _E is at a low level (so-called off state), the potential distribution shown in FIG. 7C is obtained and no signal is read out.

Next, the switching MOS transistor 9 is turned on, the load MOS transistor 6 is turned off, and the vertical selection line 2 _O is set to a higher level (φ _VO is, for example, 10).
V) and the substrate potential is negative (V _sub is, for example, −1).
5V), the accumulated holes 31 are discharged to the substrate side as shown in the potential distribution of FIG. 7D, and the pixels 1 in the first row are reset.

At this time, the potential distribution of the pixel 1 in the second row in which the vertical selection line 2 _E is low level is as shown in FIG. 7E and is not reset.

After resetting, the substrate voltage V _{sub is set} to 0 V, the vertical selection line 2 _{O is set} to a high level (φ _VO is 5 _V, for example), and the switching MOS transistor 9 is turned off (φ ₁
Is set to 0 V), the load MOS transistor 6 is turned on (φ _{VGG is set} to 5 V, for example), and dark signal reading is performed. In this way, the signal output of the pixel in the first row is obtained in the first half of the horizontal blanking period _THB .

Next, in the latter half of the horizontal blanking period T _HB , signal reading of the pixels in the second row is similarly performed.

As a result, the output signal S is obtained on the pixel signal line 4, and the difference between the signal level S ₁ and the dark signal level S ₂ becomes the signal amount a. The respective signal quantities a are sample-held separately by the sample-hold circuit 7 having two circuits shown in FIG. 2, and pixel signal output corresponding to one horizontal scanning line is made. In addition, in FIG. 2, the horizontal signal line 11 is one for convenience, but two horizontal signal lines are derived from the sample hold circuit 7 for two circuits.

This solid-state image pickup device has an electronic shutter function, and shutter pulses φ _{PO and} φ _PE are applied to the vertical selection lines 2 _O and 2 _E in other horizontal blanking periods, respectively, and are synchronized with each other. As a result, the substrate voltage V _sub also becomes a potential at the same level as that at the time of resetting (for example, −15 V), the accumulated holes 31 are discharged to the substrate side, and the electronic shutter operation is performed.

FIG. 6 shows an odd field and an even field.
Read each vertical selection line 2 [2₁, 2₂，
... 2₇, ...] applied voltage φ_V1,φ_V2,...
Φ _V7,Show ... Φ in odd fields_V1When
φ_V2, Φ_V3And φ_V4, Φ_V5And φ_V6, Is selected and is even
Φ in the field_V2And φ_V3, Φ_V4And φ_V5, Φ_V6And φ_V7,
... is selected. Shutter pulse φ_PO,φ_PEIs horizontal
The shutter pulse φ given within the ranking period
_PO,φ_PEAnd time T until signal reading_SPIs an electronic shutter
Equivalent to speed.

In this embodiment, however, as shown in FIG. 1, a load MOS transistor 6 composed of a source 41, a drain 42 and a gate 43 connected to each pixel signal line 4 is horizontally arranged below the imaging region 30. Of the load MOS transistors 6 _O connected to every other pixel signal line 4 _O (for example, odd-numbered) while being formed within a 2-pixel pitch of 2 pixels, that is, within a width d _H of 2 pixels. The load MOS transistors 6 _E, which are arranged in the column and are connected to every other (for example, even-numbered) pixel signal lines 4 _E , are arranged in the second column far from the imaging region 30. In this case, in consideration of the connection wiring, the load MOS transistors 6 _O in the first column and the load MOS transistors 6 _{E in} the second column are arranged horizontally offset from each other so as to form a checkerboard pattern.

According to this structure, each load MOS transistor is
The width of the star 6 is 2 pixels_HBy forming using
The gate length of each load MOS transistor 6 (channel
Length) L ₂Can be taken longer. At the same time every other
Pixel signal line 4_OLoad MOS transistor 6 connected to_O
And every other pixel signal line 4_ELoad MO connected to
S transistor 6_EAnd the first and second columns, respectively
Each load MOS transistor is arranged in a checkerboard pattern.
Type 6_O, 6_EIs the width d of 2 pixels_HCan be formed within
Channel length L₂Can be lengthened.

Therefore, the short channel effect of the load MOS transistor can be suppressed, and the constant current characteristic of the load MOS transistor is improved as shown by the I _ds -V _ds characteristic of FIG. For example, when the pixel pitch is around 3.7 μm, the channel length L ₂ can be 3 μm or more. Therefore, the unit pixel 1
The gain of the source follower circuit composed of the load MOS transistor 6 and the load MOS transistor 6 approaches 1, and the sensitivity of the FWA amplification type solid-state imaging device increases.

The gain (AC gain during small signal) of the source follower circuit as shown in FIG. 3 is described by the following equation 1.

[0038]

[Equation 1]

However, g_mIs a unit pixel (driving MOS transistor
Transistor) 1 transconductance, g_dIs a unit pixel
(Driving MOS transistor) 1 drain conductance
Su, g _bIs the unit pixel (driving MOS transistor) 1
CK gate conductance g_dlIs the load MOS transistor
This is the drain conductance of transistor 6.

When the short channel effect of the load MOS transistor 6 is large, g _dl becomes large and the gain of the source follower circuit is lowered. Conversely, load MOS transistor 6
If the channel length L of is taken long and the short channel effect is suppressed, g _dl can be made negligibly small with respect to g _m , and the gain approaches 1. As shown in FIG. 9 _, g _d, g _dl of this MOS transistor is g _d, g _dl = ΔI _ds / ΔV _ds
Becomes

Therefore, in the configuration of this example, I _ds -V of FIG.
_{As is} apparent from the _ds characteristic, g _dl is so small that it can be ignored, so that the gain of the load MOS transistor 6 is increased, and as a result, the sensitivity of the image sensor can be improved.

In the above example, the N-channel MOS transistor is used as the unit pixel 1 and the accumulated signal charge is a hole. However, a P-channel MOS transistor having the signal charge as an electron may be used in the unit pixel.

In the above example, the element forming the unit pixel shown in FIG. 4 has a structure in which a channel region (so-called surface channel) is formed on the surface of the P-type well region. An element forming a so-called buried channel may be the unit pixel 1.

Furthermore, the present invention is not limited to the FWA-type amplification type solid-state image pickup device of the above example, but a solid-state image pickup device having a circuit configuration in which a pixel signal is taken out through a source follower circuit composed of a unit pixel and a load transistor. Can also be applied to.

[0045]

According to the present invention, the channel length of the load transistor connected to each pixel signal line wired in the vertical direction can be increased and the short channel effect can be controlled. As a result, the gain of the source follower circuit composed of the unit pixel and the load transistor is increased, and the sensitivity of the solid-state imaging device can be improved. Therefore, it is suitable for application to, for example, a solid-state imaging device for high-definition television.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a main part of a solid-state imaging device of the present invention.

FIG. 2 is a circuit configuration diagram of an FWA type amplification type solid-state imaging device according to the present invention.

FIG. 3 is a signal readout equivalent circuit diagram of a unit pixel of an FWA type amplification type solid-state imaging device.

FIG. 4 is a cross-sectional view of a unit pixel of an FWA amplification type solid-state imaging device.

FIG. 5 is a timing chart of the FWA amplification type solid-state imaging device.

FIG. 6 is a timing chart of field reading of the FWA amplification type solid-state imaging device.

FIG. 7 is a potential distribution diagram in each operating state of the FWA amplification type solid-state imaging device.

FIG. 8 is a drain current-drain voltage characteristic diagram of the load MOS transistor according to the present invention.

FIG. 9 is a drain current-drain voltage characteristic diagram of a load MOS transistor according to a comparative example.

FIG. 10 is a configuration diagram of a main part of a solid-state imaging device according to a comparative example.

[Explanation of symbols]

1 unit pixel 2 vertical selection line 3 vertical scanning circuit 4 pixel signal line 5 horizontal scanning circuit 6, 6 _O , 6 _E load MOS transistor 7 sample hold circuit 8 switching MOS transistor 9 switching MOS transistor

Claims (2)

[Claims] 1. An image pickup area in which unit pixels are arranged in a matrix, a vertical scanning circuit for selecting the unit pixels in the vertical direction, a horizontal scanning circuit for selecting the unit pixels in the horizontal direction, and wirings in the vertical direction. A solid-state imaging device having each pixel signal line and a load transistor connected to each pixel signal line, wherein the load transistor is formed within a width of two pixels in the horizontal direction. 2. A load transistor connected to every other pixel signal line is arranged at a position close to the imaging region, and another load transistor connected to every other pixel signal line is positioned far from the imaging region. The solid-state image pickup device according to claim 1, wherein the solid-state image pickup device is arranged.