JPH05268253A - Reception processing system for communication control data - Google Patents

Abstract

(57) [Summary] [Object] To enable efficient use of a data storage area of a data memory and miniaturization of the data memory for reception processing of communication control data such as signaling data. A transmission data storage unit (SDM) is provided with a data memory (DM) and a table memory (TM) for collating an address stored in the data memory (DM) with calling terminal information. ) Sequentially stores the communication control data in the order of input, and the analysis control unit (SC) refers to the table memory (TM) to store the signaling data from a specific originating information terminal in the data memory (DM). The address is detected, and the communication control data is read from the data memory (DM) based on the address and analyzed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effectively applied to a reception process of communication control data such as signaling data.

[0002]

2. Description of the Related Art B-ISDN is a next-generation communication technology.
(Broad-band Integreated Service Digital Network) is under study, and ATM (Asynchronous Transfer Mode) is used as a communication exchange technology for realizing this B-ISDN.
Exchange technology is being considered. With this ATM exchange technology,
This is a technology to transfer data such as voice or image in fixed length packets called cells, and the conventional STM (Synchrono) that allocates a fixed band according to the amount of information.
It is expected to be a technology that enables the transfer processing of enormous amounts of data such as image information that is difficult to handle with the us Transfer Mode) method.

By the way, in the ATM switch, in order to analyze the signaling data (data for controlling one call, such as dial number) received from the terminal equipment (TA), the signaling data is accumulated for each subscriber. It has a data memory (DM) for controlling. In the data memory (DM), the signaling data area of the same subscriber needs to be secured in a portion where the addresses on the data memory (DM) are continuous.

Therefore, if n addresses of the data memory (DM) are allocated to one signaling data (subscriber), 1 k of signaling data (the data memory (DM when the subscriber 9 is processed is processed. )
1k × n worth of addresses were required above.

[0005]

However, depending on the usage status of the subscriber's terminal equipment (TA), the area on the data memory (DM) for a certain signaling data (subscriber) is frequently used, but another area is used. The area of the data memory (DM) for the signaling data (subscriber) of (1) is rarely used, and the usage frequency is biased.

As described above, in the prior art in which the area on the data memory (DM) is uniformly assigned to all the signaling data (subscribers), the data memory (DM) is used efficiently. Absent. The present invention has been made in view of the above problems, and an object thereof is to realize efficient reception processing of signaling data on a data memory (DM).

[0007]

According to the present invention, a received data storage unit (RDM) has a data memory (DM) and a table memory (comparing with an address stored in the data memory (DM) and calling terminal information. TM) is provided, communication control data is sequentially stored in the data memory (DM) in the order of input, and the analysis control unit (SC) refers to the table memory (TM) so that the signaling data from a specific originating information terminal is received. The address of the stored data memory (DM) is detected, and based on this, the data memory (D
The communication control data is read from M) and analyzed.

[0008]

According to the present invention, since the data is stored in the data memory (DM) in the order of arrival of the cells 1, the data memory (DM) having the capacity calculated from the operation rate of the ATM switch statistically obtained. Should be set. Further, a table memory (TM) is provided to manage the data memory (DM) for each subscriber. The table memory (TM) collates calling terminal information with the address of the data memory (DM). You only need to register the minimum necessary information to do so.

[0009]

(Embodiment 1) FIG. 2 schematically shows the system configuration of an ATM exchange according to this embodiment. As shown in the figure, it has an exchange switch (ATM-SW), a reception data storage unit (RDM), and a main control unit (CC).

Received data storage unit (RDM) of this embodiment
Has a table memory (TM) and a data memory (DM), which are controlled by an analysis control unit (SC) provided in the main control unit (CC). The format of the cell 1 in the ATM will be briefly described here. As shown in FIG. 8, the cell 1 has a fixed length format of 53 bytes, a header 4 of 5 bytes, and a payload of 48 bytes. It is composed of. V in header 4
Path information such as PI and VCI is stored, and control information, audio information, image information, etc. are stored in the information field (DATA) of the payload. When the signaling data is stored in the cell 1, the additional information header 2 in addition to the information field (DATA) in the payload,
An additional information tailor 3 is provided.

VPI and V of header 4 in cell 1
It is possible to identify the originating terminal device (TA) from the CI. Further, the additional information header 2 stores a segment type (ST) and a sequence identifier (SN),
Effective data length information (LEN) is stored in the additional information tailor 3. That is, the signaling data originally has a variable-length frame format. On the other hand, the ATM cell format is limited in the amount of information that can be stored in a single cell 1 as described above. Therefore, if the signaling data is 44 bytes or less, it can be accommodated in a single cell 1.
In the case of more than this, it will be divided into a plurality of cells 1. Therefore, it becomes necessary to identify whether the signaling data stored in the cell 1 is the head portion, the middle portion, the tail portion, or a single piece. The segment type (ST) makes this distinction, and the order identifier (SN) shows the order.

Further, in the case of the single cell 1 or the last cell 1 storing the signaling data, not all 44 bytes of the information field (DATA) are used. Therefore, effective data length information (LEN) is provided to indicate how many bytes of the information field are effective information. FIG. 5 shows the internal structure of the reception data storage unit (RDM) in more detail.

As shown in the figure, the table memory (T
The table memory address counter (TM
ACT) is provided. The table memory address counter (TMACT) is for counting access addresses to the table memory (TM).
Further, a data memory address counter (DMACT) is provided in front of the data memory (DM) and counts access addresses to the data memory (DM).

Valid data length information holding unit (LEN-L)
Has a function of latching valid data length information (LEN) in the additional information tailor 3 of the cell 1, and has a function of correcting the count value of the data memory address counter (DMACT). However, this point will be described later. In addition, a route information holding unit (VPI / VCI-L)
Has a function of latching the VPI and VCI of the header 4 information and notifying the analysis control unit (SC).

The segment type holder (ST-L) is
Segment type (S in the additional information header 2 of cell 1
It has a function of latching T). The timing generation unit (TMG) is the segment type holding unit (ST-L).
When the output from the cell 1 indicates “single” or “final” of the cell 1, a function of sending a start signal to the analysis control unit (SC) at the end of storage in the data memory (DM) of the cell 1 have.

As shown in FIG. 5, the table memory (TM) and the data memory (DM) are two-port RAMs.
The access on the upstream side consists of an exchange switch (ATM-
The access from the latter side is performed by the analysis control unit (S).
C). As shown in FIG. 3, the table memory (TM) has a VPI of the input cell 1 for one address.
Area and segment type (S
Area for registering T), area for registering address of data memory (DM), and effective data length information (LEN)
There is an area for registering.

On the other hand, as shown in FIG. 4, the data memory (DM) is of a format in which the information of the cells 1 sequentially arrived from the lowest address is stored. Next, the operation of the reception data storage unit (RDM) will be described with reference to FIG. First, at the time of initialization, the analysis control unit (SC) performs the following control on the reception data storage unit (RDM). [Initial setting of received data storage unit (RDM)] (1). The ST registration area of all addresses in the table memory (TM) is set to "intermediate". (2). Set both the table memory address counter (TMACT) and the data memory address counter (DMACT) to "-1". (Because the cell 1 that arrived first is stored from the address "0") Here, as signaling data, the cell length is divided into two cells 1 as shown in FIG.
A case will be described in which the invalid cell 1 intervenes and arrives at the reception data storage unit (RDM) of the present embodiment.

The first cell 1 is a received data storage unit (RDM)
When it arrives at, the VPI / VCI from the header 4 is latched by the route information holding unit (VPI / VCI-L).
Further, the segment type (ST) is latched by the segment type holding unit (ST-L) from the additional information header 2. Further, the effective data length information (LEN) from the additional information tailor 3 is latched by the effective data length information holding unit (LEN-L).

When the cell 1 is a valid cell, first, the table memory address counter (TMACT) is incremented to "-1" → "0". According to the address counted by the table memory address counter (TMACT), the VPI / V of the head cell 1 concerned
CI, segment type (ST), data memory (D
The M) address (here, "0") and the valid data length information (LEN) are written in the table memory (TM) at the timing of FIG.

The data memory address counter (DM
ACT) is also counted up (“−1” → “0”), and the payload information is sequentially written from the lowest address as shown in FIG. That is, the additional information header 2 of the first cell 1 is stored in addresses "0" and "1", the first byte of signaling data is stored in "2", and the last byte of signaling data (44th byte) is stored in "45". To be done. Further, the 2-byte additional information tailor 3 is stored in "46" and "47".

An invalid cell (see FIG. 7) arrives after the first cell, but at this time, the received data storage unit (R
DM) does not perform any processing. Next, when the final cell 1 arrives, the table memory address counter (TMAC
T) is incremented from “0” to “1”, and the VPI / VCI of the last cell 1 and the segment type (S
T) and the data memory (DM) address (here, "48") are written at the timing of FIG.

The data memory address counter (D
MACT) also increased from "47" to "48",
According to this, 48-byte data of the payload is sequentially written in the data memory (DM). When all the data of the final cell 1 is stored in the data memory (DM) (see FIG. 7).
At the time point indicated by middle X), the timing generation unit (TMG) notifies the analysis control unit (SC) of the activation request.

In the analysis control unit (SC), the terminal device (T
It is necessary to analyze what kind of signaling data A) has sent and respond to it. First, the analysis control unit (SC) needs to specify the terminal device (TA), which can be recognized by the VPI / VCI of the cell 1 sent from the route information holding unit (VPI / VCI-L). is there.

Next, when analyzing the signaling data, it is necessary to know where in the data memory (DM) the signaling data is stored. This is done as follows. When the analysis control unit (SC) receives the activation request from the timing generation unit (TMG), the analysis control unit (SC) searches the table memory (TM) for VPI / VCI and segment type (ST) from the lowest address, and stores the route information holding unit (SC). It matches the output from VPI / VCI-L) and the segment type (ST) is "single" or "head".
To find out what is showing. [When "single" is searched for] Here, it is assumed that the content of the segment type (ST) indicating "single" is found at the address "j" of the table memory (TM).

At this time, the address "j" of the table memory (TM) and the address of the data memory (DM) stored corresponding to this (assumed here to be "m").
And are taken into the analysis control unit (SC). Data memory (D
In M), the actual signaling data starts after the address (“m” and “m + 1”) where the additional information header 2 is stored, that is, “m + 2”.

Since the cell 1 is a "single" cell 1, the signaling data is not stored in all the areas of the information field (DATA) as described above. Therefore, it is necessary to determine up to where “m + 2” of the data memory (DM) stores the signaling data. This can be obtained from the effective data length information (LEN) of the additional information tailor 3 stored in the addresses "m + 46" and "m + 47" of the data memory (DM).

The valid data length information (LEN) may be directly taken into the analysis control unit (SC) from the valid data length information holding unit (LEN-L). As described above, the analysis control unit (SC) can accurately recognize the address where the signaling data is stored on the data memory (DM). The analysis control unit (SC) stores the data in the table memory (TM) at a stage when the analysis of the signaling data is completed (it may be immediately after the analysis control unit (SC) takes in “j” and “m” before the analysis). The content of the segment type (ST) of the address "j" is returned to "intermediate".

This is to prepare for the case where the next signaling data frame is received from the same terminal device (TA) and the analysis control unit (SC) is activated next. [When the "head" is found] Table memory (TM)
It is assumed that the segment type (ST) of "1" indicates "start" is found at the address "j" of the table memory (TM).

Also in this case, the table memory (TM)
The address "j" and the address "m" of the data memory (DM) corresponding to the address are temporarily stored. Here, the fact that the segment type (ST) of the table memory (TM) indicates the "head" indicates that the signaling data is divided and sent to a plurality of cells 1.

Here, the signaling data can be analyzed only when one frame is complete. Therefore, it is necessary for the analysis control unit (SC) to recognize where in the data memory (DM) the signaling data for one frame is stored. Therefore, the contents of the VPI / VCI of the table memory (TM) are stored in the path information holding unit (VPI / VC) when the activation is received.
The part that matches the output from I-L) and the content of the segment type (ST) indicates "intermediate" or "final" is subsequently searched from the table memory (TM).

Here, the table memory (TM) indicates that the content of the segment type (ST) indicates "intermediate".
Suppose it was found at address "j '" of. Next, the analysis control unit (SC) fetches the address "j '" of the table memory (TM) and the address "m'" of the data memory (DM) corresponding to this address.

Next, the analysis control unit (SC) matches the contents of the VPI / VCI of the table memory (TM) with the output from the route information holding unit (VPI / VCI-L) when it is activated, In addition, the portion in which the content of the segment type (ST) indicates "final" is followed by the table memory (T
Search from M). Here is the segment type (ST)
It is assumed that the contents of the above "final" are found at the address "j ''" of the table memory (TM).

Here, the analysis control unit (SC) is similar to the above, and the address “j ″” of the table memory (TM),
The address “m ″” of the data memory (DM) corresponding to this address is fetched. As described above, this signaling data is the address "m + 2" of the data memory (DM).
From "m '+ 2" and "m" +2 ", it can be seen that 44 bytes each are stored. However, in the case of the final cell 1, as in the case of the single cell 1, the signaling data is not always stored in all 44 bytes. Therefore, it is necessary to refer to the valid data length information (LEN) stored in “m ″ +46” and “m ″ +47”.

FIG. 7 shows a case where two valid cells are continuously input to the ATM switch although the invalid cell is interposed from the same terminal device (TA). In this way, when one frame of signaling data from the same terminal device (TA) is continuously received, these signaling data are stored in the data memory (D
Since it is stored in consecutive addresses on M), "m '" from address "j'" and "m""fromaddress" j "of the table memory (TM) in the above description.
It is not necessary to store the data in the analysis control unit (SC).

However, in general, even if a plurality of cells 1 are continuously transmitted from the terminal device (TA), the cells 1
In most cases, the cell 1 sent from another terminal device (TA) enters between these cells 1 at the stage of reception by the ATM switch. In such a case, the terminal device (T
One frame of signaling data from A) is not stored in consecutive addresses on the data memory (DM), but is scattered. In order to grasp the entire signaling data scattered for this purpose, a table memory (TM) is used.
It is indispensable to fetch "m '" from the address "j'" and "m""from the address" j "into the analysis control unit (SC).

After the analysis control section (SC) recognizes the storage area of the signaling data for one frame in this way, the analysis control section (SC) checks the sequence identifier (SN). This is to confirm whether or not there is a cell 1 drop (cell 1 dropout) during transmission in the information divided into a plurality of cells. Order identifier (S
N) is the address “j” or “j” of the data memory (DM).
+1 "," j '","j' + 1 "," j "," J "+1"
Since they are respectively stored in the memory, the order identifier (SN) is sequentially read from these addresses and checked.

In the analysis control unit (SC), as a result of checking the above sequence identifier (SN), if there is no cell 1 drop, the signaling data for one frame is read and analyzed. When the drop in cell 1 is found as a result of checking the sequence identifier (SN), the analysis control unit (SC) ignores the received data at all, or retransmits the signaling data to the terminal device (TA) that is the transmission source. Is requested.

When the analysis in the analysis controller (SC) is completed, the address "j" of the table memory (TM) is read.
The contents of the segment type (ST) on the table memory (TM) of "j '" and "j""are returned to" intermediate "as in the initial setting. (Embodiment 2) This embodiment 2 is characterized in that the count value of the data memory address counter (DACT) is corrected by using the valid data length information holding unit (LEN-L) in FIG.

As described above, the segment type (ST)
Is "single" or "final" cell 1, the signaling data is not stored in all areas of the information field, and the effective number of bytes of data refers to effective data length information (LEN). It can be identified by
Here, as shown in the upper diagram of FIG. 6, the valid data is up to the "P" byte of the information field, and "P + 1"
It is assumed that the invalid (unnecessary) cell 1 at the "Q" th byte arrives at the ATM exchange shown in FIG.

At this time, the data memory address counter (DMAC) sequentially counts up as described in the first embodiment, and the payload data of the preceding cell 1 is sequentially written in the data memory (DM). At the same time, the valid data length information (LEN) of the cell 1 is latched by the valid data length information holding unit (LEN-L), and based on the information of the valid data length information (LEN), "P + 1"- "Q" byte is invalid (not required)
Identify that. Effective data length information storage unit (LE
NL) counts down (subtracts and corrects) the data memory address counter (DMAC) by "QP" bytes based on the identification result.

Then, the valid data length information (LEN) latched before the next cell 1 (subsequent cell 1) is written in the data memory (DM) is written in the data memory (DM). At this time, since the address of the data memory (DM) indicates the address in which “P + 1” of the preceding cell 1 is stored, the valid data length information (LEN) concerned is the preceding cell 1
The result is that the invalid data part of is overwritten.

When the succeeding cell 1 arrives, the data memory address counter (DMAC) sequentially writes the valid data length information (LEN) in the data memory (DM). Thus, in the second embodiment,
When the segment type (ST) indicates "single" or "final", the number of bytes of invalid data is detected from the valid data length information (LEN), and the beginning of the invalid data is registered in the data memory (DM ) Up to the upper address, the data memory address counter (DMAC) is subtracted and corrected, and the effective data length information (LEN) of the cell 1 is overwritten.
Therefore, unnecessary (invalid) data memory (DM)
The data memory (DM) can be used more efficiently without storing data.

In the case of the second embodiment, the data memory (D
Since the invalid data portion is not stored in M), the analysis control unit (SC) can perform the continuous read processing similar to that of the "intermediate" cell 1 even in the case of "single" and "final". As described above, according to each embodiment, the area of the data memory (DM) is sequentially used for each arrival order of the cell 1, so that the total capacity of the data memory (DM) is significantly reduced as compared with the conventional technique. can do.

That is, the transmission frequency of signaling data and the number of terminal devices (TA) having the transmission frequency are modeled by statistical calculation, and the data memory (D) at each transmission frequency is modeled.
It is possible to optimize the M) area. As a result,
It is possible to analyze the signaling data with a smaller capacity of the data memory (DM) than the conventional technique. In addition, in each of the above-described embodiments, the table memory (TM) is required in addition to the data memory (DM).
If M + 1 addresses “0” to “M” are prepared as the area M), 48 bytes in one cell 1 are written to the data memory (DM) as the table memory (TM) area. , (M + 1) / 48 address areas are sufficient, and there is no concern of enlarging the received data storage unit (RDM) by providing the table memory (TM).

[0045]

According to the present invention, the data storage area of the data memory can be used efficiently and the data memory can be miniaturized.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram showing the configuration of an ATM exchange of the present invention.

FIG. 3 is an explanatory diagram showing the contents of a table memory (TM).

FIG. 4 is an explanatory diagram showing the contents of a data memory (DM).

FIG. 5 is a block diagram showing an internal configuration of a reception data storage unit (RDM).

FIG. 6 is an explanatory diagram showing the principle of the second embodiment.

FIG. 7 is a timing chart showing processing in a reception data storage unit (RDM).

FIG. 8 is an explanatory diagram showing a cell configuration.

[Explanation of symbols]

 1 --- Cell 2--Additional information header 3--Additional information tailor 4--Header TA-Terminal device DM-Data memory TM-Table memory SDM-Sending data storage unit SC-Analysis control unit TMACT-・ Table memory address counter DMACT ・ Data memory address counter LEN-L ・ ・ Effective data length information holding unit CC ・ ・ Main control unit VPI / VCI-L ・ ・ Route information holding unit ST-L ・ ・ Segment type holding unit TMG ..Timing generation unit ATM-SW ... Exchange switch

Claims (3)

[Claims] 1. A data memory (DM) for accumulating communication control data stored in a cell 1 and received from a terminal device (TA) in the order of input, an address stored in the data memory (DM), and transmitting terminal information. And a table memory (TM) for collating the received data, and a reception data storage unit (RD) for receiving a start signal when all the communication control data are stored.
M) and an analysis control unit (SC) that controls the reception data storage unit (RDM), and the analysis control unit (SC) includes the reception data storage unit (R).
Table memory (T
M), the address of the data memory (DM) is detected, the communication control data is read from the data memory (DM), and this is analyzed and processed. 2. The data memory (DM) and the table memory (TM) are provided with a data memory address counter (DMACT) and a table memory address counter (TMACT) which generate an address in the preceding stage, and When 1 is received, the information stored in the payload of the cell 1 is sequentially counted up by both the counters and stored in the designated data memory (DM) and table memory (TM). The communication control data reception processing method according to claim 1. 3. The reception data storage unit (RDM) comprises:
It has a valid data length information holding unit (LEN-L) which holds valid data length information (LEN) of the cell 1, and the valid data length information held in the valid data length information holding unit (LEN-L). (LEN) to data memory (D
The invalid data length of the cell 1 stored in M) is detected, and the data memory address counter (D
When the address value of (MACT) is subtracted and the next cell 1 is written, first, the valid data length information holding unit (LEN-
3. The communication control data according to claim 2, wherein the effective data length information (LEN) held in L) is overwritten at the end of the previous cell 1 and the next cell 1 is written in the area following this. Reception processing method.