JPH05264696A - Superconductive multiplexed circuit - Google Patents

Abstract

(57) [Abstract] [Object] The present invention relates to a superconducting multiplex circuit, and SQUI
Even if the number of channels of the D sensor increases, it is possible to perform multiplexing with a single circuit and to prevent an increase in power consumption. [Configuration] The shift register (23 ₁ ~23m) in multiple-bit configuration, sequentially shifts the bits to output a true value.
AND circuits (22 ₁ ~22n) is provided with a plurality for each bit of the shift register, a plurality of channels SQU
The output signals of the respective ID sensors are supplied, and only the output signals of the SQUID sensors corresponding to the bits for outputting the true value of the shift register are extracted. The plurality of OR circuits (24 _{1 to} 24 a) are the same as those of the shift register.
The output signals of a plurality of AND circuits corresponding to the bits that output the true value of the shift register are provided in the same number as the AND circuits provided for the bits and are supplied to the room temperature system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting multiplexer circuit, and relates to a multi-channel digital SQUID (Superconductin) circuit.
g QUantum Interference Devices) for superconducting multiplexer circuit.

A magnetic field sensor using SQUID is characterized by having excellent sensitivity characteristics as compared with other sensors using semiconductors. In particular, many SQs are used in the measurement of minute magnetic fields such as magnetism emitted from the living body (heart and brain).
Development of a method for simultaneously detecting signals from UID sensors is strongly desired.

[0003]

2. Description of the Related Art In recent years, a digital SQUID having good compatibility with a superconducting digital integrated circuit has been proposed as compared with a conventional analog SQUID. This digital SQUA
The ID quantizes the input magnetic field with 1 bit by using an AC bias as the bias current of the SQUID that senses the input magnetic field. That is, when the input magnetic field increases, a positive pulse
When it decreases, one negative pulse is generated. Further, in the case of the one-chip SQUID, the generated pulse is written into the superconducting storage loop by one flux quantum through the write gate, and a part of the pulse is fed back to the SQUID sensor so that the operating point of the SQUID sensor is also increased. The pulse is controlled so that no pulse is output from the sensor so that it is returned to and (zero point operation) (eg, Fujimaki, Tamura, Imamura, Hasuo "One-chip SQUID magnetometer", Theoretical theory, pp.33-37, 19
See April 21, 1988).

In this system, the feedback circuit is superconducting.
Since it is composed of a circuit, it can be fed back to the room temperature system.
No path is required, and the number of signal lines taken out to the room temperature system is
Multi-channel SQUID because it can be reduced
Suitable for configuring. Furthermore, the applicant of the present invention is Japanese Patent Application No. 2
-336401, Title of Invention "Multi-channel SQ
UID magnetometer ", multi-channel S
QUID sensor 10 ₁Output data of 10 to 10n
One by multiplexing with the multiplexer 11 which is a conductive integrated circuit
By taking out from the terminal 12 of the room temperature system, SQUI
Low temperature environment system and room where D sensor and multiplexer are placed
Proposal of a superconducting circuit that greatly reduces the connection cable with the temperature system
did.

[0005]

In the circuit of FIG. 8, each S
Supplying a bias current shown in FIG. 9 (A) to QUID sensor 10 ₁ to 10n, the SQUID sensor 10 _1, 1
0 _2, ..., Fig than 10n 9 (B), (C ), and it outputs a digital signal which is positive or negative pulse shown in (D).
The multiplexer multiplexes the outputs of all the SQUID sensors 10 _{1 to} 10 n during a period T ₁ (a period equal to or less than ¼ of the bias cycle) in which each SQUID sensor outputs a positive or negative pulse, and the multiplexer shown in FIG. Output a signal.

During this time, the multiplexer outputs pulse signals corresponding to the number of channels. Therefore, if the number of channels is n, the signal processing speed of the multiplexer is S
It must be at least 4n times the bias frequency of the QUID. For example, SQU of 100 channels
If the ID were biased at 10 MHz, the multiplexer would have to process the signal at a high clock frequency of 4 GHz. It is virtually impossible to perform signal processing at such a high speed, and the number of SQUIDs that can be processed by one multiplexer is limited by the signal processing speed. Therefore, as the number of channels increases, it becomes necessary to perform parallel processing using a plurality of multiplexers. As described above, if the number of multiplexers increases, the power consumption for operating the circuit increases correspondingly, and the amount of liquid helium consumed increases.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a superconducting multiplex circuit that can be multiplexed with a single circuit even if the number of channels of the SQUID sensor is increased, and that prevents an increase in power consumption.

[0008]

A superconducting multiplex circuit of the present invention is a superconducting multiplex circuit in which output signals of SQUID sensors of a plurality of channels are multiplexed and taken out to a room temperature system. A shift register that sequentially shifts the bits that output the signal, and a plurality of SQUIDs for a plurality of channels provided for each bit of the shift register.
The output signals of the respective sensors are supplied, and only a plurality of S corresponding to the bits for outputting the true value of the shift register are output.
Output signals of a plurality of logical product circuits which are provided in the same number as the logical product circuits for extracting the output signals of the QUID sensor and the logical product circuits provided for 1 bit of the shift register and which correspond to the bits for outputting the true value of the shift register. And a plurality of OR circuits for taking out and supplying it to the room temperature system.

[0009]

According to the present invention, a plurality of AND circuits are provided for each bit of the shift register, the true value bit of the shift register is shifted, and the SQUID sensor outputs of a plurality of channels are simultaneously output from the corresponding AND circuits. Since it is taken out to a room temperature system, an increase in the number of channels can be dealt with by a single multiplexing circuit, and an increase in power consumption can be prevented.

[0010]

1 is a block diagram of an embodiment of the circuit of the present invention.

In the figure, the output of each n-channel SQUID sensor enters each of the terminals 20 _{1 to} 20 n and is supplied to each of the input circuits 21 _{1 to} 21 n for each channel.

Each of the input circuits 21 _{1 to} 21 n is shown in FIG.
As shown in, it is composed of a magnetic field coupling type OR gate 30,
An input signal is supplied from the terminal 31 and an output signal is taken out from the terminal 32. The magnetic field coupling type OR gate 30 has, for example, the threshold characteristic shown in FIG. 7B, is turned off at the lower hatching portion of the curve, and is turned on at the outer portion thereof, and is supplied with the bias current shown by the broken line from the terminal 33 to operate. .. This threshold characteristic is bilaterally symmetric, and switches from off to on regardless of whether a positive or negative input pulse is supplied.

The output signals of the input circuits 20 _{1 to} 20 n are supplied to AND circuits 22 _{1 to} 22 n, which are AND circuits, respectively. AND circuits 22 ₁ output of 1-bit shift register 23 ₁ is supplied to the ~22a AND circuit 22 _i
The output of the 1-bit shift register 23 ₂ is supplied to +22 _{i + a,} and the output of the 1-bit shift register 23 _m is supplied to the AND circuits 22 _{na to} 22 _n . In this embodiment, there is a relationship of n = a × m.

The AND circuits 21 _{1 to} 21 n are shown in FIG.
As shown in (A), this is a 2-OR AND circuit composed of two OR gates 35 and 36 and an AND gate 37. The output signal of the input circuit is supplied to the terminal 38, the output signal of the 1-bit shift register is supplied to the terminal 39, and the output signal is taken out from the terminal 40. This OR gate has the threshold characteristic shown in FIG. 3B, is turned off at the hatched portion inside the curve and turned on at the outside thereof, and is supplied with the bias current shown by the broken line from the terminal 41. When both are on, the AND gate 37 is on.

As shown in FIG. 4, each of the 1-bit shift registers 23 _{1 to} 23 m includes a 2-OR AND circuit including OR gates 50 and 51 and an AND gate 52, and an OR gate 53 and OR gate 53.
And 54. The OR gates 50 and 51 are supplied with the power supply φ ₁ shown in FIG. 5A, the terminal 55 is supplied with the output of the preceding 1-bit shift register, and the terminal 5
6 is supplied with a shift signal. This shift signal is "1"
At this time, the input signal of the terminal 55 is taken out from the AND gate 52 and is output from the terminal 57 to the AND circuits 22 _{1 to} 22n of FIG.
Is supplied to. The output of the AND gate 52 is sequentially shifted by the OR gates 53 and 54 which are supplied with the power supplies φ ₂ and φ ₃ whose phases are delayed by 120 degrees, and is supplied from the terminal 58 to the 1-bit shift register of the next stage.

[0016] Here, by supplying an input signal that is true value, that value "1" only at the beginning t ₀ of time period T ₁ of the 9 to 1 bit shift register 23 ₁ shown in FIG. 1, the period T ₁ is The value "1" is stored in all the 1-bit shift registers 23 ₁ to 23 m.
Shift signal is supplied to the one at the end tm period T ₁
The 1-bit shift registers 23 ₁ to 23 m are shift-driven so that the output of the bit shift register 23 m becomes the value “1”.

As a result, first, at time t₀1 bit
Shift register 23₁And is supplied with the value ‘1’
Road 22₁22a is the input circuit 21₁~ 21a output signal
OR circuit 24 which is a logical sum circuit₁~ 24a
Supply to the OR circuit 24₁~ 24a each by terminal 25
₁It is taken out to a room temperature system through .about.25a. Next one bit
Shift register 23₂Value "1" is supplied. A
Circuit 22_i~ 22 _{i + a}Is the input circuit 22_i~ 22_{i + a}
Take out the output signal of the terminal 25₁Output from ~ 25a
Then, in the same manner, at the time tm, 1-bit shift register
AND circuit 22 supplied with the value "1" from the controller 23m._na
22n is the input circuit 21_naTake output signal of ~ 21n
Take out the terminal 25₁It outputs from ~ 25a.

As described above, since the signals for the a channel can be simultaneously taken out from the terminals 25 _{1 to} 25a to the room temperature system, the signal processing speed of the multiplexing performed in the circuit of FIG. It can handle an increase in the number of channels. Moreover, since the circuit of FIG. 1 performs the multiplexing operation by itself, it is possible to prevent an increase in power consumption and an increase in the consumption amount of liquid helium.

By the way, instead of the OR circuit 36 of the AND circuit shown in FIG. 2A, a magnetic field coupling type S as shown in FIG.
The QUID OR gate 42 is used to enter terminal 39.
The output signal of the 1-bit shift register may be supplied from the terminal 43 to the next AND circuit through the OR gate 42.

In this case, the 1-bit shift register 23
The number a of AND circuits that can be connected to each 1-bit shift register can be increased regardless of the fanouts of _{1 to} 23 m. Further, FIG. 7 input by the waveform illustrating the bias current supplied to the terminal 33 of the input circuit shown in FIG. 2 (A) with respect to such SQUID sensor output shown in (A) in FIG. 7 (B) circuit 21 ₁ ~ 21n each signal output period T ₂
As shown in FIG. 7C, the signal output period T ₁ of the SQUID sensor can be extended to about twice the period.

In this case, the output period of the input circuits 21 _{1 to} 21 n is twice as long as that in the conventional case, so that the signal processing speed of multiplexing can be reduced to 1 / (2 · a) of the conventional case.

[0022]

As described above, according to the superconducting multiplexing circuit of the present invention, even if the number of channels of the SQUID sensor is increased, the SQUID sensor can be multiplexed in a single circuit and the increase in power consumption can be prevented. It is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a circuit of the present invention.

FIG. 2 is a diagram for explaining an input circuit.

FIG. 3 is a diagram for explaining an AND circuit.

FIG. 4 is a circuit configuration diagram of a 1-bit shift register.

FIG. 5 is a diagram illustrating a 1-bit shift register.

FIG. 6 is a circuit configuration diagram of a modified example of an AND circuit.

FIG. 7 is an operation explanatory diagram of a modified example of the circuit of the present invention.

FIG. 8 is a block diagram of an example of a conventional circuit.

FIG. 9 is an operation explanatory diagram of a conventional circuit.

[Explanation of symbols]

21 _{1 to} 21n Input circuit 22 _{1 to} 22n AND circuit 23 _{1 to} 23m 1-bit shift register 24 _{1 to} 24a OR circuit

Claims (2)

[Claims] 1. A taking out an output signal of the SQUID sensor of the plurality of channels to room system by multiplexing the superconducting multiplexing circuit, a plurality of bits constituting the shift register (23 ₁ for sequentially shifting the bits to output a true value 23m), and a plurality is provided for each bit of the shift register,
The SQUID sensor respective output signals of a plurality of channels are supplied, a logical product circuit (22 ₁ ~22n) extracting an output signal of the plurality by SQUID sensor corresponding to the bit to output a true value of the shift register, the A plurality of logical sum circuits provided in the same number as the logical product circuits provided in one bit of the shift register, extracting the output signals of the plurality of logical product circuits corresponding to the bits that output the true value of the shift register, and supplying the output signals to the room temperature system. (24 _{1 to} 24
a) A superconducting multiplex circuit having: 2. The superconducting multiplexing circuit according to claim 1, wherein the output signals of the SQUID sensors of a plurality of channels are SQ.
Superconducting multiplexing circuit, characterized in that it has a UID greater than the signal output period of the sensor maintained for a predetermined period to each logical circuits (22 ₁ ~22n) to supply input circuit (20 ₁ ~20n).