JPH0526264B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a relative movement speed control device for controlling the relative movement speed of an information detection point in an information reading device with respect to a recording medium in a track extension direction.

For example, an information reading device in a digital audio system uses PCM (Pulse Code) recorded on a recording medium in the following format.
Modulation) data is read. That is, one frame consists of, for example, 588 channel bits, and a frame synchronization signal having a predetermined bit pattern is inserted at the beginning of each frame. PCM data is EFM (Eight to Fourteen)
Modulation method, every 8 bits are converted into 14 channel bits according to a predetermined conversion table, and then 3 channel bits of adjustment bits are added, so that there are between 1 and 1 2 or more and 10 or less throughout. O is arranged. After such data conversion processing, so-called NRZI (Nou Return to Zero Inverse) is created in which 1 corresponds to inversion and O corresponds to non-inversion.
Modulation processing is performed using a modulation method. Therefore, in an information reading device in a digital audio system, the signal read from the recording medium is a run-length limited modulation signal with a minimum inversion interval of 3T (T is the period of one channel bit) and a maximum inversion interval of 11T. It becomes a certain EFM modulation signal.

In such an information reading device, a spindle servo device as shown in FIG. 1 is provided as a relative movement speed control device for an information detection point. In FIG. 1, an RF (high frequency) signal obtained from a recording disk 2 by a pickup 1 is amplified by a preamplifier 3 and then supplied to a slicer 4.
The slicer 4 slices the vicinity of the zero level of the RF signal using, for example, the nonlinearity of a diode.
It is configured to output a value signal. The RF signal is converted into an EFM modulation signal by the slicer 4, and is supplied to a PLL circuit 5 for demodulating clock reproduction, a synchronization signal detection circuit 6, and a frequency detection circuit 7.
The demodulation clock output from the PLL circuit 5 is sent to the synchronization signal detection circuit 6 and the digital signal processing circuit 8.
is supplied to The synchronization signal detection circuit 6 includes an NRZI demodulator that performs demodulation operation using a demodulation clock, and the bit pattern of the data obtained by supplying the EFM modulation signal to this NRZI demodulator is used as the frame synchronization signal. The structure is such that when the bit pattern matches, a reproduction synchronization signal consisting of a pulse of a predetermined time width is output. In addition, the frequency detection circuit 7
is configured to output a signal having a level corresponding to, for example, the average value of the inversion intervals of the supplied EFM modulation signal. Further, the digital signal processing circuit 8 demodulates the EFM modulated signal in synchronization with the master clock output from the master clock generator 9 at a first predetermined time interval to obtain PCM data and corrects code errors. And, based on the count value obtained by counting the number of occurrences of the master clock, the second
The reference synchronization signal is configured to be output at predetermined time intervals. Master clock generator 9
consists of an oscillator that is formed using a crystal resonator and oscillates at the same frequency as the natural vibration frequency of the crystal resonator.

The reproduced synchronization signal output from the synchronization signal detection circuit 6 is supplied to a frequency detection circuit 10 and is phase-compared with a reference synchronization signal in a phase comparison circuit 11 . In the frequency detection circuit 10, the reproduction synchronization signal is supplied to a trigger input terminal of a monostable multivibrator (hereinafter abbreviated as monostable multi) 12. The values of the resistor and capacitor for time limit setting are set so that the inversion time of the monostable multi 12 is a third predetermined time shorter than the second predetermined time. The output of this monostable multiplier is supplied to a low-pass filter 12 having an integrating circuit configuration. This low-pass filter 12
A signal having a level corresponding to the repetition frequency of the pulse outputted as a reproduction synchronization signal is output from the frequency detection circuit 10. Further, the phase comparator 11 outputs a signal corresponding to the phase difference between the reference and reproduction synchronization signals. The outputs of the frequency detection circuit 10 and the phase comparison circuit 11 are added by an adder 14. The output of the adder 14 and the output of the frequency detection circuit 7 are alternatively supplied to the spindle servo amplifier 16 as an error signal by a changeover switch circuit 15. A drive current corresponding to the error signal is supplied from the spindle servo amplifier 16 to the spindle motor 17, and the recording disk 2 is rotationally driven so that the level of the error signal is constant at a predetermined level, thereby recording the pick-up 1, that is, the information detection point. The relative movement speed in the track extension direction with respect to the disk 2 is controlled.

A lock detection signal is supplied to the control input terminal of the changeover switch circuit 15 from a lock detection circuit (not shown) when the PLL circuit 5 for demodulating clock reproduction enters a lock state. When the lock detection signal is supplied, the changeover switch circuit 13 selectively outputs the output of the adder 14 as an error signal. At other times, that is, until the demodulation clock regeneration PLL circuit 5 is in a locked state, the output of the frequency detection circuit 7 is output as an error signal.

In the above configuration, when the PLL circuit 5 is in the locked state, the output of the frequency detection circuit 10 is added to the output of the phase comparison circuit 11 to form an error signal. Therefore, in this case, the rotational speed of the spindle motor can be well controlled as in the case where a minor frequency servo loop is provided in a spindle servo device based only on phase information.
In other words, in a spindle servo device based only on phase information, as the frequency of the signals whose phases are compared increases, the amount of control obtained for the same phase difference decreases at a slope of 12 dB/oct, resulting in good stability. Another disadvantage is that appropriate damping characteristics cannot be obtained. Generally known methods to eliminate such drawbacks include providing a phase compensation circuit and providing a frequency servo minor loop, but when using the same spindle motor, considering bandwidth, gain, etc., the latter is preferable. It is better to adopt this method.

However, when a drift occurs in the frequency servo loop due to temperature changes in the time constant setting resistor and capacitor of the monostable multi 12 in the frequency detection circuit 10 forming the frequency servo loop, the phase adjustment is performed to correct this drift. In the servo loop, the phase difference between the reference and reproduction synchronization signals changes. However, if this drift becomes large enough to exceed the phase locking range, a problem occurs in that correct data reading cannot be performed. In order to prevent the occurrence of such problems, a separate temperature compensation circuit is provided, resulting in the inconvenience of complicating the circuit configuration. Further, when integrated into an integrated circuit, external terminals for a resistor and a capacitor for setting a time constant are required, which makes integration into an integrated circuit difficult.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to detect information in an information reading device that can control the relative movement speed of an information detection point with a simple configuration without causing data reading errors due to temperature drift, and that can be easily integrated into an integrated circuit. An object of the present invention is to provide a point relative movement speed control device.

A relative movement speed control device for an information detection point in an information reading device according to the present invention is inserted at a predetermined position in each frame so that a frame containing a predetermined number of encoded digital data and a boundary between the frames can be detected. reading means for reading from a recording medium an information signal containing a synchronization signal that is read and has a predetermined bit pattern; and synchronization signal detection means for detecting the synchronization signal from the read signal obtained from the reading means and generating a reproduction synchronization signal. and clock signal generating means for generating a clock signal for processing the digital data at predetermined time intervals. A relative movement speed control device for controlling a relative movement speed, comprising a counting means for generating a speed control pulse having a pulse width over a period for counting a predetermined number of the clock signals in response to the reproduction synchronization signal, The configuration is such that the relative moving speed is controlled depending on the timing of pulse generation.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.

FIG. 2 is a circuit diagram showing one embodiment of the present invention, in which only the frequency detection circuit 10 is shown. The other blocks 1 to 9, 11 and 14 to 17 are omitted because they are connected in the same manner as in FIG. 1. In this example, the reproduced synchronization signal b output from the synchronization signal detection circuit 6 is transferred to a D-type flip-flop.
Supplied to the D input terminal of FF ₁ . A master clock a output from a master clock generator 9 is supplied to the clock input terminal of the D-type flip-flop _FF1 . This D-type flip-flop
The Q output c of FF ₁ is the D of D type flip-flop FF ₂ .
It is supplied to an input terminal and one input terminal of a NAND gate _G1 . In addition, the output of the D-type flip-flop _FF1 is connected to the NAND gate _G2 ,
_G3 and an inverter _IV1 is supplied to the set input terminal of an R-S flip-flop _FF3 .
The clock input terminal of the D-type flip-flop _FF2 is supplied with a master clock a, similar to the D-type flip-flop _FF1 . The output d of this D-type flip-flop _FF2 is supplied to the other input terminal of the NAND gate _G1 . NAND gate G ₁
The output of is supplied to the clear input terminal of the 4-bit binary counter _CT1 . A master clock a is supplied to the clock input terminal of the 4-bit binary counter _CT1 . The carry output f of this 4-bit binary counter _CT1 is supplied to the clock input terminal of a 4-bit binary counter _CT2 . The clear input terminal of the 4-bit binary counter _CT2 is connected to the output g of the R-S flip-flop _FF3.
is supplied. The carry output h of this 4-bit binary counter _CT2 is connected to the inverter _IV1 , which is the reset input terminal of the R-S flip-flop _FF3 .
and one input terminal of the NAND gate _G4 . The output of the R-S flip-flop _FF3 is supplied to the other input terminal of the NAND gate _G4 . The pulse i output from the NAND gate _G4 is supplied to the low-pass filter 18 as a speed control pulse j via the inverter _IV2 . The output of this low-pass filter 18 is supplied to the adder 14 as the output of the frequency detection circuit 10.

In the above configuration, when the master clock generator 9 outputs the master clock a at a predetermined time interval _T1 as shown in FIG. When the reproduction synchronization signal b consisting of a high level signal is output,
At the first rise of the master clock a after generation of the reproduction synchronization signal b, the D-type flip-flop _FF1 enters the set state. Then, at the first rise of the master clock a after the reproduction synchronization signal b disappears, the D-type flip-flop FF1 enters the reset state, and the D flip-flop _FF1 enters the reset state.
The Q output c of the type flip-flop _FF1 is as shown in FIG. The inversion operation of the D-type flip-flop _FF2 to which this Q output c is supplied occurs with a delay of one clock from the inversion operation of _FF1 . Therefore, the output d of the D-type flip-flop _FF2 becomes as shown in FIG. Both remain at a high level over the period _T2 . From the NAND gate _G1 to which these Q outputs c and Q outputs d are supplied, a clear signal e consisting of a low level signal is supplied to a 4-bit binary counter _CT1 over a period _T1 as shown in FIG. The count value of this 4-bit binary counter _CT1 is cleared when the master clock a rises while the clear signal e is being supplied, and the count value increases when the master clock a rises after the clear signal e disappears. . When the count value of the 4-bit binary counter _CT1 reaches 15, that is, at the 15th rise of the master clock a after the disappearance of the clear signal e, a carry output f consisting of a high level signal as shown in FIG. occurs. At the first rising edge of master clock a after generation of this carry output f,
The count value of the bit binary counter _CT1 returns to zero and the carry output f disappears.

The carry output f generated and disappeared as described above is supplied to the clock input terminal of the 4-bit binary counter _CT2 every _16T1 as shown in FIG. 4B.
Since the set input terminal of the R-S flip-flop _FF3 , which supplies the Q output g to the clear input terminal of the 4-bit binary counter _CT2 , is supplied with the output of the D-type flip-flop FF1, the output of the D-type flip-flop _FF1 is supplied.
S flip-flop _FF3 goes into the set state on the first rising edge of master clock a after Q output c goes low. At this time, since the Q output g becomes high level, the count value of the 4-bit binary counter _CT2 increases when the carry output f occurs after the Q output c becomes low level. When the count value of this 4-bit binary counter _CT2 reaches 15, that is, when the carry output f occurs for the 15th time after the Q output c becomes a low level, a carry output consisting of a high level signal as shown in Figure C is generated. h is output from the 4-bit binary counter _CT2 . Since this carry output h is supplied to the reset input terminal of the R-S flip-flop _FF3 , the R-S flip-flop _FF3 enters the reset state when the carry output h is generated. Therefore, the Q output g becomes a low level when the carry output h is generated, as shown in _FIG . Therefore, the carry output h is not repeatedly output unless the reproduction synchronization signal b is generated again.

A NAND gate to which this carry output h and the output of R-S flip-flop FF ₃ are supplied.
A high level signal is output from G ₄ over a period of 256T ₁ (16×16T ₁ ) as shown in E of the same figure. This high level signal is supplied to the low-pass filter 18 by the inverter _IV2 as a speed control pulse j consisting of a negative pulse as shown in FIG. A signal having a level corresponding to the generation cycle of the speed control pulse j is output from the low-pass filter 18, and is added to the output of the phase comparison circuit 11 to become an error signal. Then, as in the apparatus shown in FIG. 1, a drive current corresponding to this error signal is supplied to the spindle motor 14, and the recording disk 2 is rotationally driven so that the level of the error signal is constant.

Incidentally, in the above embodiment, the frequency detection circuit 10
The configuration is such that an 8-bit binary counter formed by two 4-bit binary counters obtains a pulse that exists during the period in which the master clock is generated 256 times and uses it as a speed control pulse. However, the frequency detection circuit 10 includes a 9-bit binary counter, and the output of the logic gate to which this counter output is supplied is connected to an inverter IV ₁ so as to generate a high level signal when the count value of this counter reaches, for example, 288. The configuration may be such that a pulse having a time width of 1/2 of the generation cycle of the reproduction synchronization signal is obtained and used as a speed control pulse.

As described in detail above, the relative movement speed control device for information detection points according to the present invention uses a master clock whose repetition frequency is set according to the natural vibration frequency of a crystal oscillator, without using a resistor or capacitor for time setting. Since the configuration allows the time width of the speed control pulse to be set, it is possible to control the relative movement speed of the information detection point without causing data reading errors due to temperature drift, and it is possible to set a time limit. This eliminates the need for external terminals for resistors and capacitors, making it easier to integrate the circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a relative movement speed control device for an information detection point in a conventional information reading device;
FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIGS. 3 and 4 are waveform diagrams showing the operation of the device shown in FIG. 2. Explanation of symbols of main parts, CT ₁ , CT ₂ ... 4-bit binary counter, FF ₁ , FF ₂ ... D-type flip-flop, G ₁ , G ₂ , G ₃ , G ₄ ... NAND gate, IV ₁ , IV ₂ ...Inverter.

Claims (1)

[Claims] 1. Recording an information signal including a frame containing a predetermined number of encoded digital data and a synchronization signal inserted at a predetermined position in each frame and having a predetermined bit pattern so that boundaries between the frames can be detected. a reading means for reading from a medium; a synchronizing signal detecting means for detecting the synchronizing signal from a read signal obtained from the reading means and generating a reproduction synchronizing signal; and a clock signal for processing the digital data at predetermined time intervals. A relative movement speed control device for controlling a relative movement speed of an information detection point in a track extension direction with respect to the recording medium in an information reading device including a clock signal generating means that generates a clock signal according to the reproduction synchronization signal. and a counting means for generating a speed control pulse having a pulse width over a period for counting the clock signal by a predetermined number, and controlling the relative moving speed according to the generation timing of the speed control pulse. A relative movement speed control device for an information detection point in an information reading device, characterized in that: