JPH05260539A - Acm control circuit for exchange - Google Patents

Abstract

(57) [Abstract] [Purpose] An ACM (address control memory) control circuit of an exchange that supplies a line setting address to a data memory for switching a digital line, facilitates the discovery of a parity error, and improves system reliability. The purpose is to improve. The address supply means 6 reads the read memory selection data RSD, supplies the read address RAS to one of the first memory 1 and the second memory 2 for which a read command is issued, and supplies the read address RAS to the other.
Supply AS. The write command signal output means 7 reads the write memory selection data WSD and outputs the write command signal WES to one of the first memory 1 and the second memory 2 to which the write command is issued. The read selection means 8 reads the read memory selection data RSD, and the line setting address data CAD is read from the one of the first memory 1 and the second memory 2 to which a read instruction is given as a read line setting address CAS in the data memory. Output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ACM (address control memory) control circuit for an exchange which supplies a line setting address to a data memory for switching a digital line, and more particularly to an ACM control circuit for an exchange having a double buffer type memory. Regarding

Generally, in a digital line exchange, communication data from the subscriber side is temporarily written in a data memory, and the communication data channel is switched by changing the write address and the read address. ..

[0003]

2. Description of the Related Art In such a system, communication data from a subscriber is written in a data memory at a sequential address, and output at a random address. The random address is called a line setting address here. The line setting address is supplied from the ACM (address control memory) to the data memory based on the control signal from the controller.

FIG. 11 is a diagram showing a schematic configuration of a conventional ACM. The ACM is composed of two RAMs 201 and 202. Line setting address data CAD to be finally output as the line setting address CAS is sent to the RAM 201 and the RAM 202 from a controller (not shown).

In this ACM, at start-up, the write enable signal WES and the line setting address data CAD
Is input to the RAM 201. At this time, the line setting address data CAD is written according to the write address WAS sent from the controller.

When all the line setting address data CAD necessary for line switching is stored in the RAM 201, RA
The line setting address data CAD is sequentially read from M201 according to the read address RAS. The selector 203 outputs the line setting address data CAD from the RAM 201 to the data memory as the line setting address CAS.

When the line switching pattern in the data memory is constant, the line setting address data CAD in the RAM 201 is repeatedly read and sent to the data memory. When changing the line switching pattern, the new line setting address data CAD is stored in the RAM 20 this time.
Entered in 2. Then, when all of the new line setting address data CAD is stored in the RAM 202, the selector 203 switches the output to the data memory from the RAM 202 according to the select signal SS from the controller.

Thus, in the conventional ACM, the RAM 2
01 and RAM 202, the writing and reading of the line setting address data CAD are switched only when the line switching pattern is changed. Also,
In the ACM, a parity detector 204 is provided on the output side of the selector 203, and the RAM 201 and the RAM 202 are provided.
Parity detection is performed every time the reading from and is switched. The parity detector 204 sends an alarm signal to the controller when it detects a parity error.

[0009]

[Problems to be Solved by the Invention] However, the conventional ACM
Then, while there is no change in the communication data switching pattern on the data memory side, the line setting address CAS is one RA
It was read only from M. Therefore, the other RA
Even if a parity error occurred due to a failure or the like in M, it was not discovered until the RAM was switched to.
Therefore, there was concern about the reliability of the system.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an ACM control circuit for an exchange which facilitates the detection of a parity error and improves the system reliability.

[0011]

FIG. 1 is a principle diagram of an ACM control circuit of an exchange according to the present invention which achieves the above object. The address data output means 3 finally outputs the line setting address data CAD as the line setting address CAS.
Is output to the first memory 1 and the second memory 2. The write address output means 4 switches the write memory selection data WSD to write the write address WA to switch to which of the first memory 1 and the second memory 2 the line setting address data CAD is to be written, every first predetermined cycle.
Include in S and output. The read address output means 5 is
Read memory selection data RS for switching and instructing which of the first memory 1 and the second memory 2 to read the line setting address data CAD for every second predetermined cycle.
D is included in the read address RAS and output. The address supply means 6 reads the read memory selection data RSD, and reads the read address RAS to the one of the first memory 1 and the second memory 2 to which the read instruction is issued.
Is supplied, and the write address WAS is supplied to the other.
The write command signal output means 7 reads the write memory selection data WSD and outputs the write command signal WES to one of the first memory 1 and the second memory 2 to which the write command is issued. The read selection means 8 reads the read memory selection data RSD, and reads the line setting address data CAD from the one of the first memory 1 and the second memory 2 to which the read instruction is given as the read line setting address CAS in the data memory. Output.

[0012]

Operation: Write memory selection data WSD included in the write address WAS and switched at every first predetermined period.
And the read memory selection data RSD included in the read address RAS and switched at the second predetermined cycle, the writing and reading of the line setting address data CAD with respect to the first memory 1 and the second memory 2 at the constant cycle. Done.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing a schematic configuration of an exchange which is an embodiment of the present invention. The interface circuit 20 is provided with a plurality of interface boards 21 to 2N. The interface boards 21 to 2N receive communication data from the subscriber side via the optical fibers 21A to 2NA, convert the communication data into electric signals, and multiplex device (MUX) 3
Send to 0. The MUX 30 multiplexes the communication data from the interface 20, converts it into a parallel signal, and sends it to the T switch 10.

The T-switch 10 switches the line of communication data and sends it to the separation device (DMUX) 40. DMUX4
0 converts the line-switched communication data into a serial signal and sends it separately to the corresponding interface boards 51A to 5NA of the interface circuit 50.

These interfaces 20, 50, MUX
30, the T switch 10, and the DMUX 40 are electrically connected to the controller 60, and the controller 6
Each operates according to a command signal from 0.

FIG. 3 is a block diagram showing a schematic configuration of the T switch 10. The T switch 10 is mainly composed of a double buffer memory 11 and an ACM (address control memory) 12. The double buffer memory 11 is provided with a RAM 111 and a RAM 112. The RAM 111 and the RAM 112 have MUs.
The communication data TD that has been converted in parallel at X30 is sent. This communication data TD is written to the side to which the write enable signal ES from the controller 60 is supplied. At this time, the communication data TD is the sequential write address WAD output from the counter 113.
Written according to.

A line setting address CAS as a read address is input from the ACM 12 to the RAM 111 and the RAM 112. This line setting address CA
S is a random address, according to which RAM1
11 and the communication data TD in the RAM 112 are read. The line setting address CAS is RAM111 and R
Although supplied to both AMs 112, the selector 114 selects the communication data TD in the RAM to which the write enable signal ES has not been sent and sends it to the DMUX 40 as switching communication data TDX.

In this way, the double buffer memory 11 uses the two RAMs 111 and 112 to alternately write and read the communication data TD.
As a result, the line can be switched without causing a time delay.

FIG. 4 is a block diagram showing a specific structure of the ACM 12. The ACM12 has two RAMA12
1 and RAMB 122 are provided. ACM12
Is the line setting address data C that is finally sent to the double buffer memory 11 as the line setting address CAS.
AD is input from the controller 60. Also, ACM
A write enable signal WES and a write address WAS are input to the controller 12 from the controller 60. Here, the write address WAS is 8-bit address data, and the fourth least significant bit thereof is the write selection data WSD described later.

Further, in the ACM 12, a counter 123 for sequentially outputting the read address RAS is provided. The read address RAS is 8-bit address data like the write address WAS,
The fourth least significant bit is read selection data RSD described later. The read selection data RSD is
When the level is high, the RAMB 122 is instructed to be read, and when the level is low, the RAMA 121 is instructed to be read. The output level of the read selection data RSD changes every time eight read addresses RAS are output.

The switching circuit 124 switches and supplies the write enable signal WES to either the RAMA 121 or the RAMB 122. The switching circuit 124 has an AND
A circuit 124a and an AND circuit 124b are provided. The write enable signal WES is input to one input terminal of the AND circuit 124a, and the NOT circuit 1 is input to the other input terminal.
The write selection data WSD inverted by 24c is input. Further, the write enable signal WES is input to one of the input terminals of the AND circuit 124b, and the write selection data WSD is input to the other.

In the switching circuit 124, the write enable signal WES is at the high level, and the write selection data WS.
When D is low level, the write enable signal WES is output to the output side of the AND circuit 124a, that is, the enable terminal E1 of the RAMA 121. This gives R
The line setting address data CAD is input to the AMA 121 via the input terminal IN1. On the other hand, when the write enable signal WES is at the high level and the write selection data WSD is at the high level, the output side of the AND circuit 124b, that is, the enable terminal E2 of the RAMB 122.
The write enable signal WES is output to. As a result, the line setting address data CAD is input to the RAMB 122 via the input terminal IN2.

The write address WAS and the read address RAS are both the selector 125 and the selector 12 respectively.
Sent to 6. The selector 125 selects the read address RAS and sends it to the address terminal AD1 of the RAMA 121 when the read selection data RSD inverted and input by the NOT circuit 127 is at the high level. Also,
When the read selection data RSD inverted and input by the NOT circuit 127 is at the low level, the selector 125 selects the write address WAS and selects the RAMA12.
1 to the address terminal AD1. The other selector 1
26 is a RAM for selecting the read address RAS when the input read selection data RSD is at the high level.
It is sent to the address terminal AD2 of B122. Further, the selector 126 selects the write address WAS and RA when the input read selection data RSD is at the low level.
It is sent to the address terminal AD2 of the MB122.

The selector 128 provided on the output side of the RAMA 121 and the RAMB 122 reads the line setting address data CAD written in the RAMB 122 from the output terminal OUT2 according to the read address RAS when the read selection data RSD is at the high level,
Double buffer memory 1 as line setting address CAS
Send to 1. Further, the selector 128 reads the line setting address data CAD written in the RAMA 121 from the output terminal OUT1 according to the read address RAS when the read selection data RSD is at the low level,
Double buffer memory 1 as line setting address CAS
Send to 1.

A parity detector 129 is provided on the output side of the selector 128 and detects the parity of the line setting address CAS output from the selector 128. The parity detector 129 immediately sends an alarm signal to the controller 60 when it detects a parity error.

Next, the operation of the ACM 12 having the above configuration will be described. FIG. 5 is a time chart explaining the operation at the time of starting the ACM 12. In the present embodiment, each RAM
The line setting address data CAD is written to the A121 and the RAMB122 every one address, and when read, every eight addresses. In addition, the controller 60
The write address WAS from the counter and the read address RAS from the counter 123 are output asynchronously with each other.

At startup, the line setting address data CA
D is first written in the RAMA 121. To do this, the controller 60 sets the write selection data WSD to low level. Since the read selection data RSD is at the low level between the time ta and the time tb, R
The read address WAS is input to the address terminal AD1 of the AMA 121. However, at startup, RAMA12
Since no data is written in 1, output terminal O
The line setting address data CAD is not output from the UT1. Further, between the time ta and the time tb, the RAM 1
The write address WAS is input to the address terminal AD2 of the line 22. Here, the line setting address data CAD
Is not entered.

Next, between time tb and time tc,
Since the read selection data RSD is at the high level, the write address RAS is input to the address terminal AD1 of the RAMA 121. At this time, the controller 6
From 0, the write enable signal WES is RAMA12.
1 is input to the enable terminal E1. This gives R
The line setting address data CAD for one address is input to the input terminal IN1 of the AMA 121. Also, at time tb
From the time to time tc, the read address RAS is input to the address terminal AD2 of the RAMB 122, but the line setting address data CAD is not output here.

In this way, after the time tc, the above operation is repeated, and the data is written only in the RAMA 121. However, during this period, the line setting address CAS is not output from the selector 128. RAMA121
When the line setting address data CAD for 8 addresses is written in, the writing is switched to the RAMB 122 this time.

FIG. 6 is a time chart for explaining the operation of the ACM 12 when the writing is switched to the RAMB 122. RAMB for line setting address data CAD
When writing to 122, the controller 60 switches the write selection data WSD from low level to high level. Since the read selection data RSD is at the low level from the time tf to the time tg, the RAMA1
The read address WAS is input to the address terminal AD1 of 21. However, RAMA121 is still in this state.
Since no data is written inside, output terminal OU
The line setting address data CAD is not output from T1.

Further, between time tf and time tg, R
The write address W is applied to the address terminal AD2 of the AM122.
AS is input. At this time, the controller 60 inputs the write enable signal WES to the enable terminal E2 of the RAMB 122. This allows RAMB
The line setting address data CAD for one address is input to the input terminal IN2 of 122.

Next, between time tg and time th,
Since the read selection data RSD is at the high level, the write address RAS is input to the address terminal AD1 of the RAMA 121. However, at this time, RA
The line setting address data CAD is not written to the MA 121. Further, the read address RAS is input to the address terminal AD2 of the RAMB 122 from the time tg to the time th. However, since the data to be read is not yet in the RAMB 122, the line setting address data CAD is not output.

In this way, after the time th, the above operation is repeated, and the data is written only in the RAMB 122. However, during this period, the line setting address CAS is not output from the selector 128 as in the case of FIG. When the line setting address data CAD for 8 addresses is written in the RAMB122, the RAMA121 is again read.
Switch to writing to.

As described above, at the time of start-up, the line setting address data CAD is alternately written to the RAMA 121 and the RAMB 122 by 8 addresses. Figure 7 shows RA
It is a figure which shows the concept of the storage area in MA121 and RAMB122. As you can see from the figure, RAMA121
When the line setting address data CAD for 8 addresses is written in the area of the address numbers 0 to 7, the next line setting address data CAD for 8 addresses is stored in the RAMB12.
No. 2 is written in the area of address numbers 8 to 14. That is, even if the line setting address data CAD is divided and written in two memories, it is continuously written as address numbers. As a result, the line setting address data CAD can be read out sequentially.

When a predetermined line switching pattern is written in the RAMA 121 and the RAMB 122, the RAMA 121
The line setting address data CAD is alternately read from the 121 and the RAMB 122. While the line switching pattern is constant in the double buffer memory 11, the line setting address data CAD written in the RAMA 121 and the RAMB 122 at the time of startup is repeatedly read. When switching the line switching pattern, the controller 60 sequentially reads the line setting address data CAD, while randomly rewriting the contents of the RAMA 121 and the RAMB 122.

FIG. 8 shows A when this data is rewritten.
7 is a time chart explaining the operation of the CM 12. Figure 8
Between time tk and time tl at RAMA12
While the line setting address data CAD is read from 1, the new line setting address data CAD is written in the RAMB 122.

In addition, between the time tl and the time tm, and between the time tm and the time tn, the RAMA 12 is set.
1 and data is read from the RAMB 122 only. Then, from time tn to time to RA
While the line setting address data CAD is read from the MB 122, new line setting address data CAD is written in the RAMA 121.

As described above, even when the new line setting address data CAD is written in the desired address,
Since the line setting address data CAD are alternately read from the RAMA 121 and the RAMB 122,
The line setting address CAS is always sent to the double buffer memory 11.

As described above, in this embodiment, the RAMA 12
1 and line setting address data C to RAMB122
A certain number of addresses (8
RAMA1 because it was done alternately for each address)
If a parity error occurs in either 21 or RAMB 122, it can be found quickly.

FIG. 9 is a conceptual diagram for explaining the operation of the T switch 10 having the ACM 12 of this embodiment. Now, the multiple input data D1 to DN are input to the double buffer memory 11 in the order of input data numbers T1, T2, ... TN. At this time, the multiple input data D from the ACM 12
The line setting address CAS is output so as to instruct to switch and output 1 to DN in the order of T3, T1, T4, T2, T5 ....

The double buffer memory 11 outputs multiple output data in the order instructed by the line setting address CAS. That is, the multiplexed output data are D3, D1, D4, D2, D5 in the order of output data numbers S1 to SN.
... is output.

The ACM 12 of this embodiment is not limited to the switching of multiplexed data as shown in FIG.
UX) and the like. FIG. 10 is a conceptual diagram of data processing when the ACM 12 of this embodiment is used in a multiplexer. The selector 300 has a large amount of data D1
~ DN is input. The ACM 12 uses this selector 30
The output order of the data D1 to DN is commanded to 0 by the line setting address CAS. As a result, a large number of data D1 to DN are time-divided and output to one signal line 301.

[0043]

As described above, according to the present invention, the write memory selection data included in the write address and switched in the first predetermined cycle, and the read memory included in the read address and switched in the second predetermined cycle. Writing and reading of the line setting address data with respect to the first memory and the second memory are alternately performed at regular intervals depending on the selection data. For this reason,
The data in the first memory and the second memory can be read through while the one pattern of the line setting address data is read. Therefore, when a failure or the like occurs in any of the memories and a parity error occurs, it can be quickly found. Therefore, the reliability of the system can be improved.

Further, according to the present invention, when the line setting address data is rewritten to a new pattern, it is not necessary to write all the new patterns in one memory as in the prior art, and one memory is used for reading while the other is being read. It is possible to write new line setting address data to a desired address of the memory. Therefore, the control efficiency for rewriting data is improved.

[Brief description of drawings]

FIG. 1 is a principle diagram of an ACM control circuit of an exchange according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of an exchange that is an embodiment of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a T switch.

FIG. 4 is a block diagram showing a specific configuration of an ACM.

FIG. 5 is a time chart illustrating an operation at the time of starting the ACM.

FIG. 6A when switching to writing to RAMB
6 is a time chart explaining the operation of the CM.

FIG. 7 is a diagram showing the concept of storage areas in RAMA and RAMB.

FIG. 8 is a time chart explaining the operation of the ACM when rewriting data.

FIG. 9 is a conceptual diagram illustrating an operation of the T switch including the ACM according to the present embodiment.

FIG. 10 is a conceptual diagram of data processing when the ACM of this embodiment is used in a multiplexing device.

FIG. 11 is a diagram showing a schematic configuration of a conventional ACM.

[Explanation of symbols]

 1 Memory 2 Memory 3 Address Data Output Means 4 Write Address Output Means 5 Read Address Output Means 6 Address Supply Means 7 Write Command Signal Output Means 8 Read Selection Means

Claims (4)

[Claims] 1. A line setting address which is finally output as the line setting address (CAS) in an ACM (address control memory) control circuit of an exchange which supplies a line setting address to a data memory for digital line switching. Address data output means (3) for outputting data (CAD) to the first memory (1) and the second memory (2); and the line setting address data (CAD) for the first memory (1) and Write memory selection data (WSD) for switching and instructing which of the second memories (2) is to be written for each first predetermined cycle is used as a write address (WA).
Write address output means (4) for including and outputting in S)
Read memory selection data (RSD) for switching and instructing from which of the first memory (1) and the second memory (2) the line setting address data (CAD) is read every second predetermined cycle. ) Read address (RA
Read address output means (5) for including and outputting in S)
Reading the read memory selection data (RSD),
The first memory (1) and the second memory (2)
An address supply means (6) for supplying the read address (RAS) to one of the read commands and a write address (WAS) for the other, and reading the write memory selection data (WSD),
The first memory (1) and the second memory (2)
A write command signal output means (7) for outputting a write command signal (WES) to the one to which a write command is issued, and reading the read memory selection data (RSD),
The first memory (1) and the second memory (2)
And a read selection means (8) for reading out the line setting address data (CAD) from the one having a read instruction and outputting the line setting address data (CAD) to the data memory as the line setting address (CAS). ACM control circuit. 2. The write memory selection data (WS)
2. The ACM control circuit for an exchange according to claim 1, wherein D) is first predetermined bit data of the write address (WAS). 3. The read memory selection data (RS
2. The ACM control circuit for an exchange according to claim 1, wherein D) is second predetermined bit data of the read address (RAS). 4. The write address output means (4)
Is configured to output the write address (WAS) asynchronously with the read address (RAS).
Control circuit.