JPH05260388A - Defect correction device for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To correct a defect in both storage modes by one defect data even without provision of defect data in the frame mode by introducing defect data in the frame storage mode from the defect data in the field storage mode so as to correct the defect. CONSTITUTION:Whether or not defect is corrected at frame storage is discriminated by comparing data of both odd and even number fields at a discrimination process in the measurement of defect by a CCD imager. The result of discrimination is stored in a ROM 2 together with defect data as a 1-bit control graph. The storage data are read by a microcomputer 3 and fed to a defect correction circuit 4. The circuit 4 introduces the defect data for the defect correction in the frame storage mode based on the defect data in the field storage mode stored in the ROM 2 and outputs the defect correction pulse to a signal processing circuit 5. The circuit 5 uses the image pickup output data of one preceding picture element to correct the defect in place of the image pickup output data of the defect picture element data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect correction device for a solid-state image pickup device, and more particularly to a defect correction device for correcting image quality deterioration due to image pickup output of a defective pixel included in the solid-state image pickup device by signal processing.

[0002]

2. Description of the Related Art Generally, a charge-coupled device (CCD: Charge) is used.
In a solid-state imaging device formed of a semiconductor such as a Coupled Device), a defective pixel whose sensitivity is lowered due to a local crystal defect of the semiconductor may occur, and in such a case, it is caused by the imaging output of the defective pixel. It is known that image quality deterioration occurs.

In order to correct the image quality deterioration due to the image pickup output of the defective pixel by signal processing, conventionally, defective data regarding position information of the defective pixel included in the solid-state image pickup device is stored in advance in a memory. When deriving the imaging output, the defective pixel is specified based on the defect data stored in this memory, and the imaging output of the defective pixel is used instead of the imaging output of the defective pixel to perform the defect correction. I was doing.

[0004]

By the way, conventionally, CC
The defect correction of the D solid-state image sensor was performed only in the field accumulation mode and not in the frame accumulation mode. Recently, however, driving in the frame accumulation mode has been strongly requested. It is necessary to correct the defect. However, since the appearance of the defect differs depending on the defect in the field accumulation and the frame accumulation, it is necessary to prepare both the defect data in the field accumulation mode and the defect data in the frame accumulation mode. No. 1-103374).

Therefore, if both the defect data in the field accumulation mode and the defect data in the frame accumulation mode are directly recorded and shipped, the storage capacity of a storage medium such as a ROM or a floppy disk is required to be doubled, Further, since the current defect correction circuit has a RAM inside and all the defect data is written therein, there is a drawback that the RAM capacity of the defect correction circuit is doubled.

Therefore, the present invention is directed to a defect correction apparatus for a solid-state image pickup device, which enables defect correction in the frame accumulation mode without preparing defect data in the frame accumulation mode in addition to defect data in the field accumulation mode. The purpose is to provide.

[0007]

In order to achieve the above object, the present invention comprises storage means for storing defect data relating to defective pixels included in a solid-state image pickup device, among output signals of the solid-state image pickup device. In the defect correction device for a solid-state image pickup device, wherein the defect correction is performed at the output timing of the output signal of the defective pixel specified by the defect data read from the storage unit, the storage unit stores the defect data in the field accumulation mode. In the frame accumulation mode, the defect data for defect correction in that mode is stored.
It is derived based on the defect data in the field accumulation mode stored in the storage means.

[0008]

When the solid-state image pickup device is driven in the frame accumulation mode, the defect generation method changes from that in the field accumulation mode. Therefore, paying attention to the defect generation method in the field accumulation and the frame accumulation, The defect data in the frame accumulation mode is derived from the defect data in the mode and the defect correction is performed according to the defect data, so that the defect correction in both the field / frame accumulation mode can be performed with one defect data.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. The CCD imager 1 which is a solid-state image pickup device to which the present invention is applied has a configuration capable of being driven in both field accumulation / frame accumulation modes. In the figure, the ROM 2 stores in advance defect data representing, for example, 10-bit position information in the vertical and horizontal directions of defective pixels obtained by measurement in the field accumulation mode during defect measurement in the production process of the CCD imager 1. There is.

As the ROM 2, for example, a horizontal 4-bit ROM for 10-bit defective data is used.
Then, as shown in the memory map of FIG. 2, in 10 bits out of a total of 12 bits in the first three areas, an absolute address is provided as vertical position data of the first defective pixel,
Absolute addresses are recorded as horizontal position data of the first defective pixel in 10 bits of the next three areas, and relative addresses are recorded as vertical position data of the second and subsequent defective pixels. The absolute address is recorded as the position data in the horizontal direction.

As is apparent from FIG. 3, the CCD imager 1 outputs the data obtained by adding the outputs of two vertically adjacent sensors (pixels) in the field accumulation mode (a) as data. In the frame accumulation mode (b), the output of each sensor is sent as data. At this time, as shown in the figure, if there is a sensor in which a defect occurs, defects appear in both odd (ODD) / even (EVEN) fields in the field accumulation mode (a), so defect correction in both fields is performed. Is required, and a defect appears in only one field in the frame accumulation mode (b), so that the defect is corrected only in one field.

That is, as is clear from FIG. 4, the defect data in the field accumulation mode (a) and the defect data in the frame accumulation mode (b) include defect data in the field accumulation mode in both odd / even fields. In the case of the same value, defects appear only in odd fields during frame accumulation, and conversely, if different values, defects appear only in even fields.

Therefore, when the defect of the CCD imager 1 is measured, as shown in FIG. 5, by comparing the data of both odd / even fields in the discrimination step, whether or not the defect is easily corrected during frame accumulation can be determined. Can be determined. The determination result is stored in the ROM 2 as a 1-bit control flag together with the defect data. As the storage area of this control flag, in the memory map of FIG.
One of the bits (hatched portion) is assigned.

Data stored in the ROM 2 is read out by a microcomputer (hereinafter abbreviated as a microcomputer) 3 and supplied to a defect correction circuit 4. FIG. 6 shows an example of a specific configuration of the defect correction circuit. In the figure, the defect data including the control flag supplied from the microcomputer 3 is written in the defect data RAM 41. Then, at the time of defect correction, as shown in the time chart of FIG.
Defect initial data (defective data at the first point in the vertical direction) is loaded into the defect counter 42 based on a FLCK (field clock) pulse synchronized with a VD (vertical synchronization) pulse.

The defect counter 42 is also used for counting in both the vertical and horizontal directions and alternately performs the counting operation. When counting in the vertical direction, HD (horizontal synchronization) is performed.
Each pulse is counted as a clock with a number as shown in FIG. 4, and when the count value and the value of the defect data in the vertical direction match, a defect correction pulse is output, and at that time, a count command in the horizontal direction is issued. Is issued, the clock is switched from the HD pulse to the horizontal transfer clock H1 of the CCD imager 1, and this is counted,
When the count value matches the horizontal defect data, a defect correction pulse is output.

Further, in the defect correction circuit 4, in the frame accumulation mode, the state ("1") of the previous control flag is set.
Or a "0") gate 43 is provided to monitor
This gate output controls whether or not the defect counter 42 can generate a defect correction pulse, that is, whether or not to perform defect correction. In this way, by stopping the defect correction in one field according to the control flag, it is possible to perform the defect correction during frame accumulation.

The defect correction pulse output from the defect counter 42 is supplied to the signal processing circuit 5 for performing signal processing defect correction on the output of the CCD imager 1. When the defect correction pulse is input, the signal processing circuit 5 is configured to perform defect correction, for example, by using the imaging output data of one pixel before instead of the imaging output data of the defective pixel.

By the way, as is apparent from the time chart of FIG. 7, the position on the time axis of the FLCK pulse for loading the defect initial data into the defect counter 42 is different between the odd / even fields, so that the defect initial data Since the timing of loading also changes, the way of counting by the defect counter 42 differs between odd fields and even fields. As a result, the count number of the HD pulse immediately after reading from the sensor is "5" in the odd field and "4" in the even field.

FIGS. 8 to 11 show time charts of 1H (H is a horizontal scanning period) of readout in field accumulation / frame accumulation and odd field / even field, and states of vertical registers and sensor charges at that time. Show.
In these figures, V1 to V4 are CCD imagers 1
Of the four-phase vertical transfer clocks, of which the first-phase and third-phase vertical transfer clocks V1 and V3 also serve to read out signal charges from the sensor by taking ternary levels.

First, consider the case where the second sensor (S2) is defective during field accumulation. In this field accumulation mode, in the case of odd fields, it is necessary to correct the second read data, as is apparent from FIG. Further, in the case of an even field, as is clear from FIG. 9, similarly, the first read data must be corrected.

Here, as a method of counting defects, as described above, in the case where the beginning of counting defect positions is before the reading portion and the output immediately after reading is "5" in the case of odd fields,
In the case of an even field, it is counted as "4". As a result, when the second sensor has a defect, as is apparent from FIG. 12, the correction is performed at the position of the count number "6" in the odd field and the position of the count number "5" in the even field. In the case of this frame accumulation, it is only necessary to correct when the count number of the even field is "5".

Consider also the case where the third sensor (S3) has a defect in the field accumulation. As is apparent from FIG. 12, the count number is “6” in the odd field.
When the count number is "6" even in the even field, the correction is performed. Further, when this is frame accumulation, as is apparent from FIG. 12, it is sufficient to correct only when the count number of the odd field is "6".

When this defect correction is generalized with reference to FIG. 12, the count numbers of the first, second and third sensors are as shown in the figure from the above description. From this, it can be derived that the count number of the sensor at the 2k-1 or 2k position is generally as shown in the figure. In FIG. 12, it is assumed that the defect exists in the 2kth (even number) sensor. For field accumulation, k for odd fields
Correct the + 4th data, and k + 5 in the even field
Correct the second data. When this is stored as a frame, only the k + 4th data in the odd field is corrected.

Next, it is assumed that the defect exists at the 2k-1th (odd number). At this time, in the case of field accumulation, the k + 4th data is corrected in the odd field and the k + 4th data is corrected in the even field. When this is stored as a frame, only the k + 4th data in the odd field is corrected. Since k can be any value, this relationship holds for all sensors.

From the above, if there is a defect in the even-numbered sensor, the defect data will have different values in both odd / even fields, and if this is set as frame accumulation, the data in the even field of the defect data at the time of field accumulation It means that the correction should be performed using only. Conversely, if there is a defect in the odd-numbered sensor, the defect data will have the same value in both the odd and even fields, and if this is set as frame accumulation, only the odd field data of the defect data during field accumulation will be used for correction. Will be good.

In other words, when the defect data is different in both odd / even fields, only the defect correction on the even field side should be carried out when frame accumulation is performed. Further, in the case of the same in both odd / even fields, it means that only the defect correction on the odd field side needs to be performed when the frame accumulation is performed. Which field is used for defect correction is determined based on the control flag stored together with the defect data.

As described above, since the defect data in the frame accumulation mode is derived from the defect data in the field accumulation mode and the defect correction is performed according to the defect data, in addition to the defect data in the field accumulation mode. Even if defect data in the frame accumulation mode is not prepared, it is possible to realize defect correction in both the field / frame accumulation mode with one defect data, and it is also possible to use it together with the field accumulation mode. Also, when measuring defects,
The defect data in the frame accumulation mode can be known only by the measurement in the field accumulation mode without performing the measurement in the frame accumulation mode.

In the above embodiment, when the defect is measured, the control flag for identifying in which field the defect is to be corrected is obtained and stored in the ROM 2 together with the defect data in advance. However, the defect correction circuit 4 loads the defect data. When reading, read the data of both odd / even fields,
It is also possible to determine in which field the defect correction is to be performed by hardware depending on whether they are equal or different. In this case, since the data can be discriminated by actually comparing the least significant 1-bit data, it can be realized by one gate. However, this data comparison must be performed using absolute addresses, but since the second and subsequent defective data use relative addresses, it is necessary to perform calculations using absolute addresses using an adder circuit.

Further, in the above embodiment, the case where the defect counter 42 in the defect correction circuit 4 is also used for counting in the vertical direction and the horizontal direction has been described. However, defect counters are provided for vertical and horizontal directions respectively and count separately. Of course, the operation may be performed.

[0030]

As described above, according to the present invention,
Focusing on the appearance of defects in the case of field accumulation and frame accumulation, the defect data in the frame accumulation mode is derived from the defect data in the field accumulation mode, and the defect correction is performed according to the defect data.
Even if the defect data in the frame accumulation mode is not prepared in addition to the defect data in the field accumulation mode, it is possible to correct the defect in both the field / frame accumulation mode with one defect data.

In addition, a control flag for identifying a field in which the defect correction should be stopped in the frame accumulation mode,
Although it is stored in the memory together with the defect data in the field accumulation mode, and in the frame accumulation mode, the defect correction in one field is stopped based on this control flag, so that the memory capacity increases by 1 bit, In terms of the circuit, it is sufficient to stop the defect correction in accordance with the control flag from the memory, so that it can be realized by a small-scale circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a memory map showing an example of a ROM that stores defect data.

FIG. 3 is a diagram showing a difference in appearance of defects due to a change in accumulation mode.

FIG. 4 is a diagram showing how to count read data.

FIG. 5 is a process diagram showing a procedure for adding a control flag at the time of defect measurement.

FIG. 6 is a block diagram showing an example of a specific configuration of a defect correction circuit.

FIG. 7 is a time chart of internal signals of the defect correction circuit.

FIG. 8 is a diagram showing a time chart of a read operation in the case of odd field / field accumulation and a state of charge transfer at that time.

FIG. 9 is a diagram showing a time chart of a read operation in the case of even field / field accumulation and a state of charge transfer at that time.

FIG. 10 is a diagram showing a time chart of a read operation in the case of odd field / frame accumulation and a state of charge transfer at that time.

FIG. 11 is a diagram showing a time chart of a read operation in the case of even field / frame accumulation and a state of charge transfer at that time.

FIG. 12 is a principle diagram of conversion of defective data of field accumulation / frame accumulation.

[Explanation of symbols]

 1 CCD imager 2 ROM 4 defect correction circuit 5 signal processing circuit 41 defect data RAM 42 defect counter

Claims (2)

[Claims] 1. A defective pixel specified by defective data read out from the storage unit in an output signal of the solid-state image sensor, the defective pixel being included in the solid-state image sensor. In the defect correction device for a solid-state image sensor, which is adapted to perform defect correction at the output timing of the output signal of, the storage means stores defect data in the field accumulation mode, and in the frame accumulation mode, the defect in the mode is stored. A defect correction apparatus for a solid-state image pickup device, wherein defect data for correction is derived based on defect data in a field accumulation mode stored in the storage means. 2. The storage means stores a control flag for identifying a field for which defect correction should be stopped in the frame accumulation mode together with defect data in the field accumulation mode. In the frame accumulation mode, the control flag is based on the control flag. 2. The defect correction device for a solid-state image pickup device according to claim 1, wherein the defect correction in one field is stopped.