JPH05257873A - Priority determination method and priority determination circuit - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Efficient bus transfer can be realized without exceeding the maximum waiting time for bus access unique to the module. [Structure] A fixed priority register 210 stores a fixed priority determined in advance for each module, and a fixed priority comparison unit 220 compares each module. The fluctuation priority comparing unit 240 compares the fluctuation priorities stored in each module and changing each time the bus permission signal is issued. Of the bus request signals based on the comparison results of the fixed priority comparison unit 220 and the variable priority comparison unit 240, the priority determination control unit 260 issues a bus permission signal to the module having the highest fixed priority, and the highest fixed priority. When there are two or more modules, the bus grant signal is output to the one having the highest variation priority. The fluctuation priority comparison unit 240 sets the fluctuation priority of the module to which the bus permission signal is output to the minimum and increases the other modules one by one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a priority judging circuit for judging the priority of a plurality of bus request signals or interrupt signals in a bus arbiter or interrupt controller.

[0002]

2. Description of the Related Art In a bus arbiter, as a priority determination method for performing bus arbitration, there are a fixed priority determination method for fixedly determining the priority of a module and a variable priority method for changing the priority each time arbitration is performed. ..

The fixed priority determination method is as follows:
The priority is fixedly determined in advance, and when the bus request signal is output from multiple modules, the fixed priorities of these modules are compared and the module with the highest fixed priority is assigned the bus priority. This is a method of outputting a permission signal. Therefore, the fixed priorities are all set to different values, and the higher values are set in the descending order of the modules in which the bus right acquisition is required.

The variation priority method varies the priority of the module each time the bus arbitration is performed, and when a bus request signal is output from a plurality of modules,
This is a method of comparing the fluctuation priorities of these modules at that time and outputting the bus permission signal to the module having the highest fluctuation priority.

As a variable priority method, the LRU algorithm is used to minimize the priority of the module to which the bus permission signal is output and increase the priority of other modules by one each time the bus arbitration is performed. Therefore, the cyclic priority determination method in which the priority is averaged in each module is general. For this method, see Japanese Patent Laid-Open No.
It is described in detail in Japanese Patent Publication No. 59950.

Further, in Japanese Patent Laid-Open No. 2-219156, it is necessary to shorten the time until the bus right is acquired by dividing each module into a high priority level and a low priority level in addition to the cyclic priority determination method. There is a countermeasure for a certain module.

[0007]

In the fixed priority determination method, one module may occupy the bus because a module with a high priority can always acquire the bus right.

Further, in the cyclic priority determination method, since the priority of all the modules is equal, it is not possible to give the bus right early to the module requiring a short response time such as I / O of the communication system. This problem can be solved to some extent by dividing each module into a high priority level and a low priority level, as described above, but since the bus usage rate and the maximum waiting time until the bus right is acquired differ depending on the module, Flexible classification is lacking just by classifying into two levels.

An object of the present invention is to enable efficient bus transfer in the priority determination in the bus arbitration without exceeding the maximum waiting time of the bus access unique to the module.

[0010]

In order to achieve the above object, the present invention combines two methods, a fixed priority determination method and a cyclic priority determination method.

That is, first, of the modules requesting the bus right, the module having the highest fixed priority is selected by the fixed priority determination method. At this time, when there are a plurality of modules having the highest fixed priority, the module having the earliest time when the bus right was given before this time is selected by the cyclic priority determination method.

More specifically, the present invention is applied to a bus arbiter which controls any one of a plurality of modules connected to a system bus to give a bus right to the system bus. In a priority determination circuit that determines one of these modules that gives the bus right when the right is requested,
A fixed priority storage unit that stores a predetermined fixed priority for each of a plurality of modules, and a fixed priority comparison unit that compares the fixed priority stored in the fixed priority storage unit between the modules. And a variable priority storage unit that stores, for each of the plurality of modules, a variation priority that varies each time the bus right is given to one of the plurality of modules, and a variation priority storage unit that stores the variation priority. Among the two or more modules requesting the bus right, the module with the highest fixed priority is the one with the variable priority comparison unit that compares the variable priority among the modules and the fixed priority comparison unit. If it is one, it is decided to give the bus right to that module. If there are two or more modules with the highest fixed priority, the comparison result of the variable priority comparison unit shows that the highest fluctuation among those modules. So that and a priority decision control section for determining to provide a bus right to Sakido module.

Then, the bus arbiter gives the bus right to one of the modules when the bus right is requested from one module, and uses the priority decision circuit when the bus right is requested from two or more modules. Grant the bus right to the module determined to grant the bus right.

The variation priority comparing section sets the variation priority of the module determined to be given the bus right by the priority determination control section to the minimum, and increases the variation priority of other modules by one. This makes it possible to change the change priority each time the bus right is given to any one of the plurality of modules.

A bus arbiter to which such a priority determination circuit is applied can be used in a computer system including a system bus and a plurality of modules connected to the system bus.

Further, according to the present invention, it is possible to determine the priority of the interrupt right requested from a plurality of I / Os.

That is, first, the fixed priority determination method selects the I / O having the highest fixed priority among the I / Os requesting the interrupt right. At this time, if there are a plurality of I / Os with the highest fixed priority, the cyclic priority determination method selects the I / O with the earliest time when the interrupt right was given before this time.

More specifically, the present invention is applied to an interrupt controller that controls any one of a plurality of I / Os connected to the system bus to give an interrupt right to a processor connected to the system bus. 2 or more I /
When the interrupt right is requested from O, a priority determination circuit that determines one of these I / Os to which the interrupt right is given, has a fixed fixed priority for each of a plurality of I / Os. The fixed priority storage unit storing the degree and the fixed priority stored in the fixed priority storage unit
A fixed priority comparison unit that compares between O and a variable priority that stores, for each of a plurality of I / Os, a variable priority that changes each time an interrupt right is given to any one of a plurality of I / Os. Degree storage unit, the variation priority comparison unit that compares the variation priority stored in the variation priority storage unit between I / Os, and the comparison result of the fixed priority comparison unit, and the interrupt right is requested. There is 2
If there is one I / O with the highest fixed priority among two or more I / Os, it is decided to give the interrupt right to that I / O, and two or more I / Os with the highest fixed priority are given. In this case, as a result of the comparison of the fluctuation priority comparison unit, a priority determination control unit that determines to give the interrupt right to the I / O having the highest fluctuation priority among those I / Os is provided.

Then, the interrupt controller uses one I
If the interrupt right is requested from the I / O, the interrupt right is given to this I / O. If the interrupt right is requested from two or more I / Os, the priority decision circuit gives the interrupt right. The interrupt right is given to the determined I / O.

The variation priority comparison unit sets the variation priority of the I / O determined to be given the interrupt right by the priority determination control unit to the minimum, and sets the variation priority of other I / O to one. It is possible to change the change priority each time the interrupt right is given to any one of the plurality of I / Os.

An interrupt controller to which such a priority determination circuit is applied is used in a computer system including a system bus, a plurality of I / Os connected to the system bus, and a processor connected to the system bus. You can

[0022]

In the present invention, the fixed priority is set high for the module which needs to immediately acquire the bus right, so that the module can be immediately acquired regardless of the time when the bus right is given.
You can get the bus right soon. Also,
It is possible to equally give the bus right to the modules having the same fixed priority by the cyclic priority determination method. As a result, efficient bus transfer can be realized without exceeding the maximum waiting time for bus access unique to the module.

In the present invention, by setting all fixed priorities to different values, it is possible to perform only the fixed priority determination method. Similarly, all fixed priorities are set to the same value. Accordingly, it is possible to perform only the cyclic priority determination method.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

First, an example of a computer system in which the priority determination circuit of the present invention is applied to a bus arbiter will be described.

FIG. 2 is a block diagram of a computer system according to this embodiment.

In the figure, 1 is a CPU, 2 is a main memory device, 3 is a bus arbiter using the priority determination circuit of this embodiment, and 4 to 7.
Is a module, 8 is a processor bus, and 9 is a system bus.

The CPU 1 and the main memory 2 are connected by a processor bus 8. The CPU 1 fetches a program and reads / writes data to / from the main memory 2.
Perform write transfer. In addition, the CPU 1 uses the module 0
Through (4), module 1 (5) of system bus 9
~ Module n (7) can be accessed.

The bus arbiter 3 centrally controls the arbitration of the system bus 9.

For example, when the module 0 (4) asserts the bus request signal BREQ [0] 301 to the bus arbiter 3 in order to acquire the bus right of the system bus 9, the bus arbiter 3 receives the module 0 (4). ), The bus right can be given to module 0 (4),
Assert the bus grant signal BGRT [0] 401. Module 0 (4) uses the bus grant signal BGRT [0] 40
When 1 is asserted, it becomes a bus master of the system bus 9, and when the bus access ends, the bus arbiter 3 negates the bus request signal BREQ [0] 301 to notify the release of the bus right. When the bus arbiter 3 detects the negation of the bus request signal BREQ [0] 301, it negates the bus grant signal BGRT [0] 401. The same applies to other modules. All control signals used for bus arbitration are output in synchronization with the bus clock.

FIG. 1 is a block diagram of the bus arbiter in this embodiment.

In the figure, 210 is a fixed priority register, 22
0 is a fixed priority comparison unit, 240 is a variable priority comparison unit, 26
Reference numeral 0 is a priority determination control unit.

The fixed priority register 210 stores a fixed priority assigned to each module in advance, and a fixed priority signal SLVL [0:
n] <2.0 ... 320 is output. Where [0: n]
Indicates a set of [0], [1], ..., [n], and []
Indicate the module number. Fixed priority signal SLVL
[0: n] <2..0> 320 has a bit width of 3 bits, and <2..0> indicates a bit string of <2>, <1>, and <0>. A numerical value indicating a fixed priority is set in this bit string, and a larger value indicates a higher fixed priority. However, the bit width does not matter in this embodiment.

The fixed priority comparison unit 220 compares the fixed priorities set in the fixed priority register 210 between the modules and outputs the comparison result. That is, the fixed priority comparison unit 220 compares the fixed priority of the module i and the fixed priority of the module j, and outputs signals SiGTj330, SiEQj340, which indicate the comparison result.
Outputs SjGTi350. Signal SiGTj330
Indicates that the fixed priority of module i is greater than the fixed priority of module j, and signal SiEQj340 is
It indicates that the fixed priority of module i and the fixed priority of module j are equal. In addition, the signal SjGTi350
Indicates that the fixed priority of module i is lower than the fixed priority of module j. Here, the subscripts i and j represent module numbers, i represents an arbitrary number of 0 or more and n-1 or less, and j represents an arbitrary number of i + 1 or more and n or less.

The fluctuation priority comparing section 240 compares the fluctuation priorities that change for each bus arbitration between the modules, and outputs the comparison result. That is, the fluctuation priority comparing unit 240 compares the fluctuation priority of the module i with the fluctuation priority of the module j, and outputs the signals DiGTj360 and DjGTi370 indicating the comparison result. The signal DiGTj 360 indicates that the fluctuation priority of the module i is higher than the fluctuation priority of the module j, and the signal DjGTi 370 indicates that the fluctuation priority of the module i is lower than the fluctuation priority of the module j.

The priority determination controller 260, based on these pieces of information, uses the bus permission signals BREQ [0]-[n] 400.
To generate.

The flip-flops of each block except the fixed priority register 210 are reset signals BRS.
Initialized to "0" by T390, the bus clock BC
It operates in synchronization with LK380. Fixed priority register 2
10 makes it possible to set by software,
No specific reference is made to the specific implementation method.

The procedure of bus arbitration will be described below with reference to FIG.

Bus request signal BRE from one module
When Q [0: n] 300 is asserted (step 3000, step 3100), the bus permission signal is asserted for the module (step 3200).

Further, when the bus request signals BREQ [0: n] 300 are asserted from two or more modules (step 3000, step 3100), priority determination is performed by the fixed priority, and the fixed priority is the highest. The higher module (the module with the largest value set in the fixed priority signal SLVL [0: n] <2..0> 320 output from the fixed priority register 210) is selected (step 3300).

This selection is performed by the fixed priority comparing section 220 by comparing the fixed priorities of the modules. If the fixed priority of the module i is higher than the fixed priority of the module j with respect to any module number i, j of 0 ≦ i <j ≦ n, the SiGT
j330 becomes "1" (true). Conversely, if module j has a higher fixed priority than module i, then Sj
GTi340 becomes "1" (true). If module i and module j have the same priority, SiEQj40
0 becomes "1" (true).

If the number of selected modules is one (step 3400), the bus permission signal is asserted for this module (step 3500).

If there are two or more selected modules (step 3400), priority judgment is made based on the fluctuation priority, the module having the highest fluctuation priority at that time is selected, and the bus is granted to this module. Assert the signal (step 3600).

The fluctuation priority is a priority that changes for each bus arbitration. The module that has become the bus master has the lowest fluctuation priority, and the modules that have fluctuation priorities lower than that have the fluctuation priority. Goes up by one. Since the variable priority changes for each bus arbitration, the method of comparing the encoded data like the fixed priority described above lacks the delay. For this reason, the variation priority comparison unit 240 holds the variation priority comparison result (upper / lower relationship) between modules in an internal register. Then, for any module number i, j with 0 ≦ i <j ≦ n, if the module i has a higher variation priority than the module j, then the DiGT
j360 becomes "1" (true). On the contrary, when the module j has a higher variation priority than the module i, Dj
GTi370 becomes "1" (true). DiGTj360
And DjGTi370 always have opposite values and it is impossible for both to be "1" or both to be "0".
These values correspond to the bus permission signals BGRT [0: n] 400.
Is fed back and fluctuates. That is, when the bus permission signal BGRT [i] 400 is asserted to the module i, the module i becomes the bus master. As a result, the variation priority of the module i becomes the lowest, and i ≠
DiGTj 360 becomes “0” and DjGTi 370 becomes “1” for all j of j.

FIG. 4 is a block diagram showing the contents of the fixed priority comparison unit 220.

In FIG. 4, the fixed priority comparison unit 220 is shown.
Is composed of a set of (n + 1) × n / 2 fixed priority comparison circuits 221 for comparing fixed priorities among the respective modules with respect to n + 1 modules from module 0 to module n. The signal distributor 222 also outputs two sets of three-bit encoded signals SLVL [i] <2..0> 3.
21 and SLVL [j] <2..0> 322 are provided to the fixed priority comparison circuit 221 for convenience of drawing.

The fixed priority comparison circuit 221 has two sets of 3
Bit-encoded signal SLVL [i] <2.0.
> 321 and SLVL [j] <2..0> 322 are input. SLVL [i] <2..0> 321 is SLVL
If [j] <2.0 ... 322, then SiGT
j330 becomes “1”. Conversely, SLVL [i] <2 ..
When 0> 321 is smaller than SLVL [j] <2..0> 322, SjGTi350 becomes “1”. SLV
L [i] <2..0> 321 and SLVL [j] <2..0>
If 322 is the same, SiEQj340 is "1".
become.

FIG. 5 is an internal block diagram of the fixed priority comparison circuit 221.

In FIG. 5, a fixed priority comparison circuit 221.
Are two sets of 3-bit encoded signals SLVL
[I] <2.0.321 and SLVL [j] <2.0.
It is a circuit for comparing the magnitude of> 322.

Table 1 is a truth table showing the state of the comparison result of the fluctuation priorities among the modules held by the fluctuation priority comparing section 240.

In Table 1, when the bus permission signal BGRT [i] 405 is asserted for the module i, the fluctuation priority of the module i becomes the lowest, so that the DiGTj 360 for all j of i ≠ j. Becomes "0". Conversely, DjGTi 370 becomes "1" for all j where i ≠ j. Similarly, when the bus grant signal BGRT [j] 406 for the module j is asserted, i ≠ j
DiGTj 360 becomes “1” and DjGTi 370 becomes “0” for all i in the above. Since the bus grant signal cannot be asserted for two modules at the same time, DiGTj 360 and DjGTi 37 when both the bus grant signal BGRT [i] 405 and the bus grant signal BGRT [j] 406 are asserted.
The state of 0 is not considered.

FIG. 6 is an internal block diagram of the variation priority comparison unit 240.

In FIG. 6, the variation priority comparison unit 240
(N + 1) × n / 2 fluctuation priority comparison circuits 241 which compare and hold the fluctuation priority among the modules for n + 1 modules 0 to n.
It consists of a set of. The signal distributor 242 has two bus permission signals BGRT [i] 405 and BGRT [j].
This is provided for convenience of the drawing in order to give 406 to the variation priority comparison circuit 241. Here, the subscript i indicates an arbitrary number of 0 or more and n-1 or less, and the subscript j indicates an arbitrary number of i + 1 or more and n or less.

FIG. 7 is an internal block diagram of the variation priority comparison circuit 241.

In FIG. 7, a variation priority comparison circuit 241.
Is an expansion of the truth table shown in FIG. 8 into actual logic.

In the change priority comparison circuit 241, when the reset signal BRST390 becomes "LOW" level, the flip-flop 244 is initialized to 0≤i <.
DiGTj 360 becomes “0” and DjGTi 370 becomes “1” for any i and j of j ≦ n. In this case, since i <j is always satisfied, in the initial state, the larger the module number, the higher the variation priority. Further, the flip-flop 244 is connected to the bus clock BCLK38.
Operates in synchronization with 0. NOR circuit 242 and NOR
The circuit 243 is a combinational logic for realizing the truth table of Table 1.

FIG. 9 is an internal block diagram of the priority determination control section 260.

The priority determination control section 260 includes modules 0 to 0.
It is composed of n + 1 bus grant signal generation circuits 261 to 263 which generate the bus grant signals BGRT [0: n] 400 of each module for the n + 1 modules of the module n.

Bus grant signal BGRT to module 0
[0] 401 is generated by the BGRT [0] generation circuit 261. Also, BGRT [1] 402 is BGRT [1]
Generated by the generation circuit 262, the BGRT [n] 403 is B
It is generated by the GRT [n] generation circuit 263.

FIG. 10 shows the bus grant signal BG of the module 0.
BGRT [0] generation circuit 2 for generating RT [0] 401
It is an internal block diagram of 61.

The signal distributor 269 is provided for convenience of drawing in order to distribute the input signal to the combinational circuit for determining the assertion of the bus permission signal BGRT [0] 401.

In order for the module 0 to become the bus master by asserting the bus grant signal BGRT [0] 401,
It is necessary to satisfy the following two conditions.

The first condition is that the bus request signal BREQ [0] 301 is asserted from the module 0, and the second condition is that the module 0 asserts the bus request signal to all other modules. In contrast, it is in a priority state. Module 0 is in the priority state with respect to other modules in the following cases. If the bus request signal is not asserted from another module, and the fixed priority of module 0 is higher than the fixed priority of the other module, the fixed priority of module 0 is equal to the fixed priority of the other module and the variable priority is changed. This is the case where either of the cases where the degree is high is applicable.

Here, the comparison of the priority with the module 1 will be described as an example.

When the priority of the module 0 is higher than that of the module 1, it means that the bus request signal B is transmitted from the module 1.
If REQ [1] 302 is not asserted, the fixed priority of module 0 is higher than the fixed priority of module 1 (when S0GT1 (331) is “1”), the fixed priority of module 0 is module 1 When the variable priority of module 0 is higher than the variable priority of module 1 (S0EQ1 (341) is “1”,
And D0GT1 (361) is “1”). These judgments are based on AN
This is performed by the D circuit 262 and the OR circuit 264. Similarly, it compares the priorities with all other modules.

Further, the bus arbitration is performed at any time when the bus permission signal is not assigned to any module or when the module which is the bus master negates the bus request signal to release the bus right. It is. Conversely, bus arbitration is not performed while the module that has been given the bus enable signal and is the bus master is asserting the bus request signal.
This determination is performed by the AND-NOR circuit 263.

When all of these conditions are satisfied, AND
The output result of the circuit 268 becomes "1", and the bus grant signal BGRT [0] 401 of the module 0 is asserted.
The negate of BGRT [0] 401 is BREQ [0] 3.
01 is negated. This is AN
This is performed by the D circuit 266. The same applies to the method of generating the bus permission signal of another module.

FIG. 11 is a timing chart of bus arbitration.

D0GT1 (361), D0GT2 (36
2) and D0GT3 (364) are “0” in the initial state, indicating that the fluctuation priority is in the order of module 2, module 1, and module 0. Also,
It is assumed that the fixed priority of module 0 is higher than the fixed priority of module 1, and the fixed priority of module 1 and the fixed priority of module 2 are equal.

In cycle number 1, module 0 and module 1 simultaneously assert bus request signal BREQ [0] 301 and bus request signal BREQ [1] 302, respectively. Here, since the fixed priority of module 0 is higher than the fixed priority of module 1, the bus arbiter 3 selects module 0, and in cycle number 2,
Assert the bus grant signal BGRT [0] 401. Further, the module 2 asserts the bus request signal BREQ [2] 304 in cycle number 2.

Next, in cycle number 3, module 0
Negates the bus request signal BREQ [0] 301. At this time, the bus request signal BREQ [1] 302 and the bus request signal B from the module 1 and the module 2
REQ [2] 304 is asserted, but here, the fixed priority of module 1 and the fixed priority of module 2 are equal, and the variable priority of module 1 and module 2 is 0 when D1GT2 (364) is 0. , Module 1 is higher. So, Bus Arbiter 3
Selects module 2 and negates the bus grant signal BGRT [0] 401 in cycle number 4, and at the same time,
Assert the bus grant signal BGRT [2] 404. By asserting the bus permission signal BGRT [2] 404, the fluctuation priority of the module 2 becomes the lowest, so D0GT2
(362) and D1GT2 (364) become "1".

Next, in cycle number 5, module 2
Negates the bus request signal BREQ [2] 304. At this time, the bus request signal BR from only the module 1
Since EQ [1] 302 is asserted, the bus arbiter 3 selects the module 1 and in the cycle number 6,
At the same time as negating the bus permission signal BGRT [2] 404, the bus permission signal BGRT [1] 402 is asserted. By asserting the bus permission signal BGRT [1] 402, the variation priority of the module 1 becomes the lowest, so D0
GT1 (362) becomes "1" and D1GT2 (36
4) becomes "0".

As described above, according to this embodiment, first of all, the module having the highest fixed priority is selected from the modules outputting the bus request signal by the fixed priority determination method, and the fixed priority is selected. When there are a plurality of modules having the highest value, the cyclic priority determination method is used to select the module having the oldest time when the bus permission signal was output before this time and output the bus permission signal. Therefore, for modules that need to acquire bus right immediately,
By increasing the fixed priority, the bus permission signal can be output immediately regardless of the time when the bus permission signal was output before this time. Further, it is possible to evenly give the bus right to the modules having the same fixed priority. This ensures that the maximum bus access latency that is specific to the module is not exceeded.
It is possible to realize efficient bus transfer.

In the present embodiment, the procedure for acquiring the bus right is performed by using the two signals of the bus request signal and the bus grant signal. However, the present invention relates to the priority determination method. It does not specify any procedure for obtaining rights. For how to get the bus right,
Various other methods are possible. It is also possible that one module has a plurality of fixed priorities and variable priorities by dividing one module by function. Further, it is conceivable to implement part or all of the present embodiment by software.

Next, an example of a computer system in which the priority determination circuit of the present invention is applied to an interrupt controller will be described.

FIG. 12 is a block diagram of a computer system according to this embodiment.

In the figure, 1 is a CPU, 2 is a main memory device, 8 is a processor bus, 9 is a system bus, 10 is an I / O controller, 11 is an interrupt controller using the priority determination circuit of this embodiment, and 12-. 14 is an I / O.

The interrupt controller 11 uses the I / O 12 ...
Of the interrupt signals 411 to 413 output from
The one with the highest interrupt priority is output to the CPU 1 as an interrupt signal 410. The determination of the interrupt priority is performed in the unit of I / O 12 to 14 based on the fixed priority and the variable priority that varies with each interrupt occurrence, as in the above embodiment.

Next, an example of a multiprocessor system in which the priority determination circuit of the present invention is applied to a bus arbiter will be described.

FIG. 13 is a block diagram of a multiprocessor system according to this embodiment.

In the figure, 2 is a main memory, 3 is a bus arbiter, 10 is an I / O controller, 20-22 are processor elements (PE), and 24 is a multiprocessor bus.

PE0 (20) to PEn (22), I / O
The multiprocessor bus 24 connecting the controller 23 and the main memory device 2 supports the snoop protocol in order to match the contents of the cache memory in a PE with the cache memory in another PE and the main memory device 2.

The bus arbiter 3 has PE0 (20) to PEn (22) and I / O which may become a bus master.
Bus request signal BREQ [0: n from controller 23
+1] 301-304 is input and the bus permission signal BGRT
Any one of [0: n + 1] 401 to 404 is output. The priority determination of the bus arbitration is performed by the fixed priority and the variable priority, as in the above embodiment.

Next, an example of a one-chip microcomputer applied to the priority determination circuit bus arbiter of the present invention will be described.

FIG. 14 is a block diagram of a one-chip microcomputer according to this embodiment.

In the figure, 30 is a one-chip microcomputer, 31 is a processor core, 32 is a DMA controller, 33 is a bus arbiter, 34 is a peripheral circuit, and 35 is an internal bus.

The DMA controller 32 has a peripheral circuit 34.
The bus arbiter 33 performs bus control of the internal bus 35.

The priority determination of the bus arbitration of the internal bus 35 is made by the fixed priority and the variable priority as in the above embodiment.

Various embodiments to which the priority judging circuit of the present invention is applied have been described above. However, since the priority judging circuit of the present invention judges the priority of a plurality of objects, a plurality of terminals in a network system can be used. It is also possible to apply other than this, such as the processing priority of.

[0090]

As described above, the priority judgment circuit of the present invention, when judging the priority of a plurality of objects, judges the fixed priority fixedly decided in advance for the plurality of objects, and If the target with the highest fixed priority is selected as a result of performing the fixed priority determination method that selects the target with the highest fixed priority, the target with the highest fixed priority is selected before this time. A variation priority determination method is performed in which a target having the oldest selected time is selected.

Therefore, when the priority determination circuit of the present invention is applied to the bus arbiter, the fixed priority is increased for the module which immediately needs to acquire the bus right.
The bus right can be easily obtained regardless of the time when the bus right is given before this time. Also,
For modules having the same fixed priority, the waiting time until the bus right is acquired can be averaged.
As a result, efficient bus transfer can be realized without exceeding the maximum waiting time for bus access unique to the module.

When the priority judgment circuit of the present invention is applied to the interrupt controller, the fixed priority is increased for the module requiring the emergency interrupt,
Interrupts can be facilitated. Further, it is possible to equalize interrupt opportunities for modules having similar interrupt needs. This makes it possible to improve the balance of interrupts.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a bus arbiter to which a priority determination circuit of the present invention is applied.

FIG. 2 is a configuration diagram of a computer system according to the present embodiment.

FIG. 3 is a flowchart showing a procedure of bus arbitration according to the present embodiment.

FIG. 4 is a block diagram showing the contents of a fixed priority comparison unit.

FIG. 5 is an internal configuration diagram of a fixed priority comparison circuit.

FIG. 6 is an internal configuration diagram of a variation priority comparison unit.

FIG. 7 is an internal configuration diagram of a variation priority comparison circuit.

FIG. 8 is an explanatory diagram showing a truth table showing the state of the comparison result of the variation priorities among the modules held by the variation priority comparing unit.

FIG. 9 is an internal configuration diagram of a priority determination control unit.

FIG. 10 is an internal configuration diagram of a bus permission signal generation circuit.

FIG. 11 is a timing chart of bus arbitration.

FIG. 12 is a configuration diagram of a computer system in which the priority determination circuit of the present invention is applied to an interrupt controller.

FIG. 13 is a configuration diagram of a multiprocessor system in which the priority determination circuit of the present invention is applied to a bus arbiter.

FIG. 14 is a configuration diagram of a one-chip microcomputer in which the priority determination circuit of the present invention is applied to a bus arbiter.

[Explanation of symbols]

1 ... CPU, 2 ... Main storage device, 3 ... Bus arbiter, 4 ...
7 ... Module, 8 ... Processor bus, 9 ... System bus, 10 ... I / O controller, 11 ... Interrupt controller, 12-14 ... I / O, 20-22 ... Processor element, 30 ... 1-chip microcomputer, 31 ... Processor Core, 32 ... DMA controller, 33 ... Internal bus arbiter, 34 ... Peripheral circuit, 35 ... Internal bus, 210 ... Fixed priority register, 220 ... Fixed priority comparison unit, 240 ...
Change priority comparison unit 260 ... Priority determination control unit, 300-
304 ... Bus request signal, 310-313 ... Enable register value, 320-328 ... Fixed priority register value, 330-333, 340-343, 350 ... Fixed priority comparison information, 360-363, 370 ... Varying Priority comparison information, 380 ... Clock signal, 390 ... Reset signal, 400-404 ... Bus permission signal, 401-414
… Interrupt signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masataka Kobayashi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Within Hitachi Micro Software Systems Ltd. (72) Inventor Akira 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Micro Software Systems Co., Ltd. (72) Inventor Hideo Haruta, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture (72) In-house Hitachi Micro Software Systems (72) Inventor Yasuhiro Furukawa Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Address Hitachi Micro Software Systems Co., Ltd. (72) Inventor Masatsugu Shinozaki 810 Shimoimaizumi, Ebina City, Kanagawa Hitachi Ltd. Office System Design and Development Center

Claims (13)

[Claims] 1. A priority determination circuit for determining priorities of a plurality of targets, wherein fixed priorities fixedly determined in advance for a plurality of targets are determined, and a target having the highest fixed priority is selected. If multiple targets with the highest fixed priority are selected as a result of performing the method and performing the fixed priority determination method, the fluctuation that selects the target with the oldest time selected before this time among those targets A priority determination method for a priority determination circuit, characterized by performing a priority determination method. 2. In a bus arbiter for controlling a bus right to any one of a plurality of modules, a fixed priority that is fixedly fixed in advance to the plurality of modules and a bus to any one of the plurality of modules. When the bus right is requested from two or more modules, the variable priority that changes each time the right is given and the priority are stored.
The fixed priority of these modules is determined, and if there is one module with the highest fixed priority, the bus right is given to that module, and if there are two or more modules with the highest fixed priority, those modules are A bus arbitration method for a bus arbiter, characterized in that the variable priority is judged and the bus right is given to the module having the highest variable priority. 3. The bus arbitration method according to claim 2, wherein, when the bus right is granted to any one of the plurality of modules, the fluctuation priority of the module to which the bus right is granted is changed. A bus arbitration method for a bus arbiter, characterized in that the fluctuation priority of other modules becomes higher one by one. 4. An interrupt controller for performing a control for giving an interrupt right to a plurality of I / Os, wherein a fixed priority fixedly determined in advance to the plurality of I / Os,
The variable priority that changes each time the interrupt right is given to any one of the plurality of I / Os is stored, and when the interrupt right is requested from two or more I / Os, these I / Os are stored. I / O fixed priority is determined, and if there is one I / O with the highest fixed priority, the bus right is given to that I / O,
If there are two or more I / Os with the highest fixed priority, the variable priority of those I / Os is judged, and the interrupt right is given to the I / O with the highest variable priority. Interrupt control method. 5. The interrupt control method according to claim 4, wherein the variable priority is the I / O to which the interrupt right is given every time one of the plurality of I / Os is given the interrupt right.
The interrupt control method of the interrupt controller is characterized in that the change priority of the I / O is the lowest, and the change priority of the other I / O is one by one. 6. A bus arbiter for controlling a bus right to the system bus to any one of a plurality of modules connected to the system bus, when the bus right is requested from two or more modules. A priority determination circuit that determines one module to which the bus right is given from among the above modules, and a fixed priority storage unit that stores a predetermined fixed priority for each of a plurality of modules; A fixed priority comparison unit that compares fixed priorities stored in the degree storage unit between the modules, and a fluctuation that changes each time a bus right is given to any one of the plurality of modules. A fluctuation priority ratio that compares the fluctuation priority storage unit that stores priorities and the fluctuation priority stored in the fluctuation priority storage unit between modules. If there is one module having the highest fixed priority among the two or more modules requesting the bus right as a result of the comparison between the comparing unit and the fixed priority comparing unit, the bus right is given to the module. If there are two or more modules with the highest fixed priority, the priority judgment for determining the bus right to the module with the highest variable priority among the modules as a result of the comparison by the variable priority comparison unit. A priority determination circuit comprising a control unit. 7. The priority determination circuit according to claim 6, wherein the plurality of modules include a plurality of processor elements each including a processor and a cache memory connected to the system bus, and an I / O controller connected to the system bus. A priority determination circuit characterized by: 8. The priority determination circuit according to claim 6, wherein the plurality of modules are a processor connected to an internal bus of a one-chip microcomputer and a direct memory access control device connected to an internal bus of the one-chip microcomputer. ,
A priority determination circuit, which is a peripheral circuit connected to an internal bus of a one-chip microcomputer. 9. The priority judgment circuit according to claim 6, 7 or 8, wherein the fluctuation priority comparison unit minimizes the fluctuation priority of the module determined by the priority judgment control unit to be given the bus right. , A priority determination circuit for increasing the degree of variation priority of other modules one by one. 10. A plurality of I / Os connected to a system bus
In any one of the I / Os, when an interrupt right is requested from two or more I / Os in the interrupt controller which controls to give the interrupt right to the processor connected to the system bus, Is a priority determination circuit for determining one I / O to which an interrupt right is given from a fixed priority storage unit that stores a predetermined fixed priority for each of a plurality of I / Os; A fixed priority comparison unit that compares fixed priorities stored in the degree storage unit between I / Os, and an interrupt right is given to any one of the plurality of I / Os. A fluctuation priority storage unit that stores a fluctuation priority that fluctuates each time a change is made, and a fluctuation priority comparison unit that compares the fluctuation priorities stored in the fluctuation priority storage unit between I / Os, Comparison result of the above fixed priority comparison unit, interrupt right More than one I / O requesting
If there is one I / O with the highest fixed priority among them, it is decided to give the interrupt right to that I / O, and if there are two or more I / O with the highest fixed priority, the above variable priority is given. And a priority determination control unit that determines to give an interrupt right to the I / O having the highest variation priority among the I / Os as a result of the comparison by the priority comparison unit. 11. The priority determination circuit according to claim 10, wherein the variation priority comparison unit minimizes the variation priority of the I / O determined to be given the interrupt right by the priority determination control unit, and The priority determination circuit is characterized by increasing the I / O variation priority of each one. 12. A computer system provided with a system bus, a plurality of modules connected to the system bus, and a bus arbiter for controlling to give any one of the plurality of modules a bus right to the system bus. Is a fixed priority storage unit that stores a predetermined fixed priority for each of a plurality of modules, and a fixed priority that compares the fixed priority stored in the fixed priority storage unit among the modules. A degree comparison unit, a variation priority storage unit that stores, for each of the plurality of modules, a variation priority that varies each time the bus right is given to any one of the plurality of modules; and the variation priority storage unit. If there is only one module requesting the bus right, the variable priority comparison unit that compares the variable priority stored in When the bus right is given to the module and there are two or more modules requesting the bus right, one of the modules having the highest fixed priority is one of the modules as a result of the comparison by the fixed priority comparing unit. Then, the bus right is given to the module, and if there are two or more modules with the highest fixed priority, the module with the highest fluctuation priority among those modules as a result of the comparison by the fluctuation priority comparison unit A computer system comprising: a priority determination control unit for giving a right. 13. A system bus, a plurality of I / Os connected to the system bus, a processor connected to the system bus, and control for giving an interrupt right to the processor to any one of the plurality of I / Os. In the computer system including an interrupt controller for performing, the interrupt controller includes a fixed priority storage unit that stores a predetermined fixed priority for each of a plurality of I / Os and a fixed priority storage unit. A fixed priority comparison unit that compares the stored fixed priority among I / Os, and a plurality of I / Os.
For each / O, it is stored in the variation priority storage unit that stores the variation priority that varies each time the interrupt right is given to any one of the plurality of I / Os, and in the variation priority storage unit. If there is only one I / O requesting the interrupt right, the variable priority comparison unit that compares the variable priority between the I / Os, and the interrupt right is given to the I / O and the interrupt right is requested. I
When there are two or more I / Os, the I / O having the highest fixed priority among the I / Os as a result of the comparison by the fixed priority comparison unit is obtained.
If the number of I / O is 1, the interrupt right is given to the I / O. If the number of I / Os having the highest fixed priority is 2 or more, the comparison result of the variable priority comparison unit, the I / O Of these, a computer system comprising a priority determination control unit that gives an interrupt right to an I / O having the highest variation priority.