JPH05244340A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To drive the element from a high speed frequency till a low speed frequency without increasing the circuit scale. CONSTITUTION:A 3rd charge transfer path 40 exclusive for high speed drive is provided in addition to 1st and 2nd charge transfer paths 34, 38 being usual charge transfer paths, and the charge is branched from a branch electrode 37 into plural paths, and a signal is alternately read while bing divided from plural 1st and 2nd output sections 39, 41 via 2nd and 3rd charge transfer paths 38, 40 respectively when a high speed data rate is necessary. Moreover, at low speed drive, the signal is read from only the 1st output section 39 arranged at the end of the usual charge transfer path. Thus, even in the case of high speed data rate, the frequency of the drive pulse is low such as 1/2 and the valid signal period is ensured and high speed drive is attained. Furthermore, the 3rd charge transfer path 40 and the 2nd output section 41 for high speed drive exclusive are small in the scale and the circuit scale of the device is not increased even at a low speed drive not requiring high speed drive.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device applied as a so-called linear image sensor in which charge transfer type devices such as CCDs are linearly arranged.

A solid-state image pickup device is a device in which the functions of a photoelectric conversion unit and a scanning unit are built on one silicon chip. Recently, a color filter is also formed on the photoelectric conversion unit for further colorization. Such a solid-state image pickup device is used as, for example, a camera-integrated VTR, and has been developed to increase the number of pixels, and not only NTSC but also high-definition are being tried.

[0003]

2. Description of the Related Art As a specific example of a solid-state image pickup device, a CCD linear image sensor for sequentially reading out pixels arranged in a straight line will be taken as an example. As a conventional CCD linear image sensor, for example, those shown in FIGS. 4 and 5 are known.

FIG. 4 is a diagram showing a solid-state image pickup device device as a CCD linear image sensor. In this figure, a photo diode sensor array 2 as a light receiving portion for generating charges according to incident light is linearly arranged on a semiconductor substrate 1, and a shift gate 3 and a shift gate 3 are arranged substantially parallel to the photo diode sensor array 2. A charge transfer path 4 is provided.

The shift gate 3 transfers the charge generated in the photodiode sensor array 2 in response to the shift gate pulse SG applied to the terminal 3a, as indicated by an arrow in the figure.
And the charge transfer path 4 introduces the charges transferred from the photodiode sensor array 2 into the two-phase clock pulses input to the terminals 5 and 6 (that is, the charge transfer shift pulses S1 and S2).
Is transferred to the output unit 7. The output unit 7 is an output gate,
It includes a read-out unit by charge-voltage conversion, an output circuit, and the like. Then, the signal of the charge transfer path 4 is read from the output terminal 8 of the output section 7.

[0006]

By the way, in the above-mentioned conventional solid-state image pickup device, since one output portion 7 is provided at the final end of one charge transfer path 4, high-speed data transfer is possible. In the case of the rate, it is difficult to secure an effective signal period (so-called high speed driving is difficult).

That is, in the case of the CCD linear image sensor shown in FIG. 4, the shift pulse at the final end of the charge transfer path 4 is a signal which repeats the drive pulse period T1 as shown in FIG. The pulse is a signal having a reset pulse width T2 (see FIG. 5B). Therefore, the waveform of the output signal is as shown in FIG. 5C, which is one cycle including at least the reset period for extinguishing the signal charges and the read period T3 of the output signal.

At this time, the effective signal extraction period T3 is the period T1 of the shift pulse and the width T2 of the reset pulse 3.
And depends on. As a result, when driven at a high data rate, the cycle of the shift pulse becomes short, and when the width T2 of the charge reset pulse cannot be changed in principle, it is inevitably effective for reading the output signal. It becomes impossible to secure a sufficient signal extraction period T3. Therefore, in practice, high speed driving cannot be performed.

On the other hand, in order to eliminate the above-mentioned drawbacks,
A CCD linear image sensor as shown in FIG. 6 has also been developed. In FIG. 6, the photodiode sensor array 12 is linearly arranged on the semiconductor substrate 11, two charge transfer paths 13 and 14 are provided substantially in parallel with the photodiode sensor array 12, and two more charge transfer paths are provided. A first shift gate 15 and a second shift gate 16 are provided so as to correspond to the charge transfer paths 13 and 14.

The first shift gate 15 guides the charges generated in the photodiode sensor array 12 in response to the first shift gate pulse SG1 applied to the terminal 15a to the charge transfer path 13 as shown by the arrow in the figure, and Second shift gate 16
Is the second shift gate pulse SG applied to the terminal 16a
2 corresponds to the even-numbered charges generated in the photodiode sensor array 2 and corresponds to the first shift gate 15 and the charge transfer path 13.
And is led to the charge transfer path 14 as indicated by the arrow in the figure.

The charge transfer paths 13 and 14 receive charges transferred from the photodiode sensor array 12 in accordance with two-phase clock pulses (that is, charge transfer shift pulses S11 and S12) input to terminals 17 and 18, respectively. Output section 19, 20
Transfer to. Each of the output units 19 and 20 includes an output gate, a reading unit by charge-voltage conversion, an output circuit, and the like. Then, in the charge transfer path 13, the odd-numbered charges transferred from the photodiode sensor array 12 are read out from the output terminal 21 of the output unit 19, and the photodiode sensor array 1
The even-numbered charges transferred from 2 are sent from the charge transfer path 13 to the charge transfer path 14 via the second shift gate 16 and read from the output terminal 22 of the output section 20 of the charge transfer path 14.

As described above, in the CCD linear image sensor shown in FIG. 6, two charge transfer paths are prepared, a shift gate is formed between the two transfer paths, and even-numbered signals and odd-numbered signals are separately charged. It is in the format of sending on the transfer route. Therefore, the frequency at the output section (frequency of the output signal) is 1 /
However, the second shift gate and the charge transfer path are required. When these are added as an external circuit, high speed drive is required. There is a new defect that the circuit scale of the device is large and it is disadvantageous when driven at low speed. Therefore, in a CCD linear image sensor in which the data frequency to be used is not fixed, it is desired that both low speed driving and high speed driving can be achieved without the above-mentioned drawbacks.

Further, as a conventional technique similar to the CCD linear image sensor shown in FIG. 6, for example, Japanese Patent Publication No. 3-4.
There is one described in Japanese Patent Publication No. 0997. In this sensor, a light receiving section is provided in the center of a substrate, two charge transfer paths are arranged on both sides of the light receiving section, two shift gates are provided between the light receiving section and the two charge transfer paths, and two charge transfer paths are further provided. A third charge transfer path, which is coupled to the output end side of the transfer path and has its own output section, is provided. During high-speed reading, signals are read separately from the two charge transfer paths.
During low-speed reading, the signals from the two charge transfer paths are alternately read out via the third charge transfer path.

However, the sensor described in this publication can drive at a higher speed than the sensor shown in FIG. 4, but requires two charge transfer paths, two shift gates and a third charge transfer path. However, there is a disadvantage in that the circuit scale of the device is large at the time of low speed driving that does not require high speed driving, which is disadvantageous. Therefore, there is room for improvement.

Therefore, an object of the present invention is to provide a solid-state image pickup device which can be driven from a high frequency to a low frequency without increasing the circuit scale.

[0016]

In order to achieve the above object, a solid-state image pickup device according to the present invention includes a light-receiving portion that generates electric charges according to incident light information, and a signal charge read from the light-receiving portion. A first charge transfer path that transfers in one direction, a shift gate that shifts charges generated in the light receiving portion to the first charge transfer path, and a second charge gate that is coupled to the first charge transfer path through an output gate. A charge transfer path, a first output section coupled to the output end of the second charge transfer path, and the output gate are coupled to charge in a direction different from the charge transfer direction of the second charge transfer path. A third charge transfer path for transferring and a second output section coupled to the output end of the third charge transfer path are provided, and the output gate is turned on during high speed driving to alternate from the first and second output sections. Signal is output to the It is characterized in that so as to output a signal only from the first output unit.

In a preferred mode, drive pulses are respectively supplied to the second and third charge transfer paths during high speed driving to alternately output signals from the first and second output sections, and during low speed driving. The level of the drive pulse supplied to the third charge transfer path is controlled to output a signal only from the first output section.

[0018]

In the present invention, the third charge transfer path dedicated for high speed driving is provided in addition to the normal charge transfer path (that is, the first charge transfer path and the second charge transfer path), and by switching the drive pulse, When a high data rate is required, the output gate is turned on and the signals are alternately read out by dividing from the plurality of first and second output sections via the second and third charge transfer paths, respectively. Further, during low speed driving, a signal is read out only from the first output section arranged at the end of the normal charge transfer path.

Therefore, even in the case of a high data rate, it is possible to secure an effective signal period and drive from a high frequency to a low frequency. Moreover, the third charge transfer path and the second output section dedicated for high-speed driving are extremely small compared to the conventional example, and the circuit scale of the device becomes large even during low-speed driving that does not require high-speed driving. Can be eliminated.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 3 are views showing an embodiment of a solid-state image pickup device according to the present invention, which is an example in which the present invention is applied to a CCD linear image sensor.

FIG. 1 is a diagram showing a solid-state image pickup device device as a CCD linear image sensor. In this figure, a photo diode sensor array 32 as a light receiving portion is linearly arranged on a semiconductor substrate 31, and a shift gate 33 and a first charge transfer path 4 are provided substantially parallel to the photo diode sensor array 32. There is. Photodiode sensor array 3
Reference numeral 2 is composed of a plurality of cells and generates an electric charge according to incident light. Each cell has, for example, a pn between it and the semiconductor substrate 31.
It includes a diffusion semiconductor region that forms a junction.

The shift gate 33 sends the charges generated in the photodiode sensor array 32 to the first charge transfer path 4, and the shift gate pulse S applied to the terminal 33a thereof.
Driven by G, the charge generated in the photodiode sensor array 32 is guided to the first charge transfer path 34 as indicated by an arrow in the figure. The first charge transfer path 34 is specifically a CCD,
Charge transferred from the photodiode sensor array 32 by the shift gate 33 is input to the terminals 35 and 36 as a two-phase clock pulse (that is, the charge transfer shift pulse S
One direction (left, output terminal side in the figure) according to 1, S2)
Transfer to.

A second charge transfer path 38 is coupled to one side of the first charge transfer path 34 via a branching electrode (corresponding to an output gate) 37, and the output of the second charge transfer path 36 is further connected. A first output 39 is coupled to the end. A third charge transfer path 40 is connected to the branch electrode 37, and a second output section 41 is connected to the output end of the third charge transfer path 40. The third charge transfer path 40 transfers charges in a direction different from the charge transfer direction of the second charge transfer path 38 (in the present embodiment, a direction orthogonal to the charge transfer direction of the second charge transfer path 38).

The first output section 39 and the second output section 41 perform an output process for reading the transferred charge as a signal, and include an output gate, a read section by charge-voltage conversion, an output circuit and the like. Then, the signal of the second charge transfer path 38 is read from the output terminal 42 of the first output section 39, and the signal of the third charge transfer path 40 is read from the output terminal 43 of the second output section 41.

Next, the operation of the solid-state image pickup device in this embodiment will be described. For example, if the first charge transfer path 34, the second charge transfer path 38, and the third charge transfer path 40 are formed by n-channel CCDs, the one having a higher voltage in the n-channel transfer path (that is, The charge moves to the one where the potential is deep and the potential is high).

Here, when low speed driving is required, the potential on the third charge transfer path 40 side is made shallow. For details, see FIG.
As shown in the CCD row in the vicinity of the branching electrode 37, the CCD rows 40a, 40b, 40 on the third charge transfer path 40 side.
The potential of c ... is made shallow. 34a to 34d ...
Is a CCD array on the first charge transfer path 34 side, 38a,
38b, 38c, ... Are CCD columns on the second charge transfer path 38 side.

CCD array 4 on the side of the third charge transfer path 40
By making the potentials of 0a, 40b, 40c ... Shallow, the charges transferred from the first charge transfer 34 to the branch electrode 37 do not flow into the third charge transfer path 40 side. Further, at this time, if a two-phase clock pulse (that is, charge transfer shift pulses S1 and S2) having the same drive frequency as that applied to the first charge transfer 34 is applied to the branching electrode 37 and the second charge transfer path 38, the charge Is from the branching electrode 37 to the second
It is transferred to the first output section 39 through the charge transfer path 38. This state is shown in FIG. 2 as a direction from the charge transfer direction (I) to the transfer direction (II). Therefore, they are not transferred in the charge transfer direction (III). Therefore, the signal is output only from the first output unit 39 during low speed driving.

On the other hand, when high speed driving is required, the second
First with respect to the charge transfer path 38 and the second charge transfer path 40.
A clock pulse having a frequency half that of the charge transfer path 34 is applied. A concrete example of the clock pulse is shown in FIG. That is, the first charge transfer path 34 and the branching electrode 3
A charge transfer shift pulse (for example, S1) having a predetermined frequency as shown in FIG.

The second charge transfer path 38 is shown in FIG.
The charge transfer shift pulse S38 having a frequency half that of the shift pulse applied to the first charge transfer path 34 as shown in FIG.
Is given to the third charge transfer path 40 as shown in FIG.
As shown in, the charge transfer shift pulse S40 having a frequency of 1/2 of the shift pulse applied to the first charge transfer path 34 and being out of phase with the one applied to the second charge transfer path 38 by a half cycle. Is given.

Thus, the second charge transfer path 38 and the third charge transfer path 38
When the charge transfer path 40 is driven in a phase relationship such that the clock pulses thereof are offset by a half cycle, the charge is
It is alternately distributed to both the charge transfer path 38 and the third charge transfer path 40. This state is shown in FIG. 2 as a direction from the charge transfer direction (I) to the transfer direction (II) and a direction toward the transfer direction (III). Therefore, there are two charge transfer directions. The third charge transfer path 40 is a charge transfer path dedicated for high speed driving.

Then, the distributed charges are transferred through the second charge transfer path 38 and the third charge transfer path 40 at a frequency which is ½ of the original transfer rate, and the first output section 39 and the second output. Output processing is performed in the unit 41, and the output terminal 42
And output terminal 43, respectively. In this case, the even-numbered and odd-numbered signals are alternately read from the output terminals 42 and 43.

As described above, in the case of high speed driving, the charges are branched and transferred from the branching electrode 37 in two directions, and
The signals are alternately read from the second output units 39 and 40 as signals. Therefore, even at a high data rate, the frequency of the clock pulse is 1/2, so that an effective signal period can be secured. That is, high speed driving can be performed.

The third charge transfer path 4 dedicated for high speed driving
Since 0 and the second output section 41 are extremely small in size as compared with the conventional one, it is possible to obtain an effect that the circuit scale of the device does not become large even during low speed driving that does not require high speed driving. That is, it is possible to achieve both high speed driving and low speed driving without increasing the circuit scale. Therefore, particularly in the CCD linear image sensor in which the data frequency to be used is not fixed, both low speed driving and high speed driving can be achieved without increasing the device circuit scale, and a cost reduction effect can also be obtained.

In the above embodiment, charge transfer shift pulses having a frequency of ½ at the time of charge transfer at the time of high speed driving and having a phase difference of a half cycle from each other are supplied to the second and third charge transfer paths. However, not limited to such transfer control, for example, at the time of high-speed driving, the electric potential of the final stage is sequentially changed for a plurality of charge output means (for example, two systems of charge transfer paths and output units) for charge transfer. The output may be controlled to be read alternately. For example, in the n-channel transfer path, the charges move to the higher potential side. Therefore, when the potentials of the final stages of the two systems are sequentially and alternately increased, the outputs are read alternately.

On the other hand, the potential (level) of the final stage is set so that only one system of charge output means is used during low speed driving.
May be controlled to read the output. In short, it suffices to appropriately control the potentials of a plurality of small-scale charge output means.

It should be noted that the present invention is similar to the above-described embodiment in the CCD.
The invention is not limited to the example applied to the linear image sensor, and can be applied to other devices to which the solid-state image sensor is applied.

[0037]

As described above, according to the present invention,
Even in the case of a high data rate, an effective signal period can be secured, and a signal can be read by driving from a high frequency to a low frequency.

Further, since the third charge transfer path and the second output section dedicated for high speed driving are extremely small compared to the conventional one, the circuit scale of the device is large even during low speed driving which does not require high speed driving. The effect of not being obtained is obtained. That is, both high speed driving and low speed driving can be achieved without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a plan view of a CCD linear image sensor to which a solid-state image sensor according to the present invention is applied.

FIG. 2 is an enlarged view of the vicinity of a branch electrode for explaining the charge transfer direction of the embodiment.

FIG. 3 is a waveform diagram showing a drive pulse of the same embodiment.

FIG. 4 is a plan view of a conventional CCD linear image sensor.

5 is a waveform diagram showing drive pulses of the CCD linear image sensor shown in FIG.

FIG. 6 is a plan view of another conventional CCD linear image sensor.

[Explanation of symbols]

 31 semiconductor substrate 32 photo diode sensor array (light receiving part) 33 shift gate 34 first charge transfer path 35, 36 terminal 37 branching electrode (output gate) 38 second charge transfer path 39 first output part 40 third charge transfer path 41 Second output section 42, 43 Output terminal

Claims (2)

[Claims] 1. A light-receiving unit that generates electric charges according to incident light information, a first charge transfer path that transfers the signal charges read from the light-receiving unit in one direction, and a charge that is generated in the light-receiving unit. To a first charge transfer path, a second charge transfer path coupled to the first charge transfer path via an output gate, and a second charge transfer path coupled to an output end of the second charge transfer path. A first output section, a third charge transfer path coupled to the output gate and transferring charges in a direction different from the charge transfer direction of the second charge transfer path, and an output end of the third charge transfer path. And a second output unit coupled to the first output unit, which turns on the output gate during high speed driving.
A solid-state image sensor, wherein the second output section alternately outputs signals, and at the time of low speed driving, the first output section only outputs signals. 2. A drive pulse is supplied to each of the second and third charge transfer paths during high speed driving to alternately output signals from the first and second output sections, and during low speed driving the third charge is supplied. 2. The solid-state image sensor according to claim 1, wherein the level of the drive pulse supplied to the transfer path is controlled so that a signal is output only from the first output section.