JPH05243994A - Spurious cancel circuit for fractional n synthesizer - Google Patents

Abstract

PURPOSE:To provide a spurious cancel circuit for the fractional N synthesizer of easy constitution at a low cost without need for a D/A converter. CONSTITUTION:The fractional N synthesizer is constituted so as to change the frequency dividing rate of a counter counting the output of a voltage control oscillator and outputting the counted output as the other input pulse of the phase comparator at the time of the over flow of an accumulator accumulating input data. The fractional N synthesizer is provided with a binary counter 3 binary-counting a master clock, a magnitude comparator 2 generating an output when the output of the accumulator 1 is larger than that of the binary counter 3, a capacitor connected between the magnitude comparator 2 and the ground, a pulse generator 9 triggered by a reference frequency pulse and generating a prescribed pulse and a switch 10 on/off-controlled by the output from the pulse generator 9 and adding the output of the magnitude comparator 2 to the output of the phase comparator 5 at the time of on, so that the D/A converter is unnecessitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spurious cancel circuit for a fractional-N synthesizer, and more particularly to D
The present invention relates to a spurious cancel circuit of a fractional-N synthesizer having a simple structure that does not use an A / A converter.

[0002]

2. Description of the Related Art An example of a conventional fractional-N synthesizer circuit is shown in FIG. Master clock Fr
Is divided by the frequency divider 83 and input to the phase comparator 84 as the reference frequency fr. The phase comparator 84 includes a counter 8
The phase difference (phase error) between the comparison frequency pulse fV and the reference frequency pulse fr, which is the output from 8, is sent to the loop filter 86 via the adder 85, and the smoothed output is used as a control signal in the voltage controlled oscillator (VCO). Supply to 87. The oscillation output frequency pulse Fo from the VCO 87 controlled by the voltage signal smoothed by the loop filter 86 is input to the counter 88. The counter 88 has a division ratio M (M
Is given as a natural number).

On the other hand, the accumulator 81 is an m-ary accumulator, is supplied with input data n, performs an accumulator operation using the reference frequency pulse fr as a clock, and sends an overflow signal generated at the time of overflow to the counter 88. Here, the accumulator 81 causes an overflow only when the period a of the reference frequency pulse fr is a. In addition, a and m are natural numbers,
n is an integer of 0 or more, m ≧ a, m> n, that is, an ≧ m
And Upon receiving this overflow signal, the counter 88 sets the frequency division ratio to M + 1. Counter 88
The comparison frequency pulse fV which is the output of the above is sent to the phase comparator 84. At this time, in the fractional-N synthesizer, the frequency division ratio becomes M + n / m, so that there is a difference from the actual frequency division ratio M or M + 1 of the counter 88, which results in a phase error and the output of the phase comparator 84. Appears as an error voltage. As a result, a staircase voltage is generated at the output of the loop filter 86, which causes spurious emission.

FIG. 9 shows a timing chart of the above-mentioned operation for each signal of the circuit obtained by removing the D / A converter 82 and the adder 85 from the circuit of FIG. Figure 9
As is clear from the above, a staircase voltage is generated at the output of the loop filter 86 at the time of overflow of the accumulator 81, which causes spurious. Therefore, in the conventional circuit, as shown in FIG. 8, the output of the accumulator 81 is converted into an analog signal by the D / A converter 82, and the adder 85 adds the phase error signal of the phase comparator 84 to the spurious signal. The occurrence of is reduced.

[0005]

As described above, the D / A converter 82 is used for the spurious cancel circuit in the conventional fractional-N synthesizer circuit, and the output data of the accumulator 81 is D / A.
Since it is necessary to match with the A converter 82 and the data input format, there is a problem that not only the circuit configuration becomes complicated, but also the board area increases due to the increase in the data transmission wiring and the cost also rises. ..

Therefore, an object of the present invention is to provide a spurious cancel circuit of a fractional-N synthesizer which does not require a D / A converter, has a simple structure, and is low in cost.

[0007]

In order to solve the above-mentioned problems, a spurious cancellation circuit of a fractional-N synthesizer according to an aspect of the present invention includes a frequency divider that divides a master clock and outputs a reference frequency pulse. A phase comparator that outputs a phase difference error signal between the reference frequency pulse and another input pulse, a loop filter that smoothes the output of this phase comparator, and a voltage whose oscillation frequency is controlled by the output of this loop filter. A control oscillator and a counter that counts the output of the voltage controlled oscillator and outputs the count output as the other input pulse of the phase comparator, accumulates the input data, and changes the division ratio of the counter when overflowing. An accumulator and a binary counter that counts the master clock in binary A magnitude comparator that produces an output when the output of the accumulator is greater than the output of the binary counter, a capacitor connected between the output of the magnitude comparator and ground, and a predetermined pulse triggered by the reference frequency pulse. A pulse generator and a switch that is ON / OFF controlled by the output from the pulse generator and that adds the output of the magnitude comparator to the output of the phase comparator when the pulse generator is ON are configured. Further, the tuning voltage input to the voltage controlled oscillator is configured to be lowered for a short time just before the loop filter.

[0008]

According to the present invention, when the output of the voltage controlled oscillator is counted and the frequency division ratio of the counter for outputting the count output as the other input pulse of the phase comparator, the above-mentioned counter is used when the accumulator for accumulating the input data overflows. In the fractional-N synthesizer configured to change the frequency division ratio, a binary counter that binary-counts the master clock, a magnitude comparator that produces an output when the accumulator output is greater than the binary counter output, and an output of the magnitude comparator. ON / OFF control is performed by a capacitor connected between the ground, a pulse generator that is triggered by a reference frequency pulse to generate a predetermined pulse, and an output from a pulse generator, and when it is ON, the magnitude comparator is used. It provided a switch for adding the data output to the phase comparator output, and eliminates the need for D / A converter.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a block diagram showing an embodiment of a spurious cancel circuit of a fractional-N synthesizer according to the present invention. 1, the accumulator 1, the frequency divider 4, the phase comparator 5, the loop filter 6,
The VCO 7 and the counter 8 are components that perform the same operations as the same name unit in FIG. In this embodiment, the phase comparator 5 and the loop filter 6 are connected by a resistor R2, reset by a reference frequency pulse fr, and a no-lap round binary counter 3 for binary counting the master clock Fr, and an output A of the accumulator 1. And the output B of the binary counter 3 are compared with each other, and a magnitude comparator 2 for generating an output when A> B is provided, and a pulse width narrower than the reference frequency pulse fr is used as a trigger by the reference frequency pulse fr. A pulse generator 9 for generating a predetermined pulse, a capacitor C provided between the output of the magnitude comparator 2 and the ground, and a pulse from the pulse generator 9
A switch 10 that is N / OFF controlled and supplies the output of the magnitude comparator 2 to the input of the loop filter 6 via the resistor R1 is also provided.

FIG. 2 shows an operation timing chart of signals of respective parts in the embodiment of FIG. The binary counter 3 is in m-ary, no lap round, that is, m
When it counts to -1, it stops counting until it is reset. Further, when the reference frequency pulse fr is at "H" level, it is reset, and when it goes to "L" level, counting is started and the potential of the output A point of the magnitude comparator 2 is A because of the charge / discharge characteristics of the capacitor C. > B
Since the capacitance of the capacitor C is large with respect to the pulse width of the output, the state shown in FIG. 2 is obtained. Here, when the pulse generator 9 outputs a pulse having a pulse width smaller than the reference frequency pulse fr, the switch 10 is turned on, and the electric charge charged in the capacitor (not shown) of the loop filter 6 passes through the resistor R1. It is discharged toward the capacitor C. That is, since the voltage is lower than the original control voltage of the VCO 7, the VCO 7 is always affected by the phase delay. The relationship between the phase difference between the reference frequency pulse fr and the comparison frequency pulse fV and the charge pump output (output of the phase comparator 5) is shown in FIG. As is clear from FIG.
When the phase of the comparison frequency pulse fV lags behind the reference frequency pulse fr, the charge pump output becomes "H".

In FIG. 1, when the accumulator 1 overflows, the delay of the comparison frequency pulse fV with respect to the reference frequency pulse fr becomes maximum, the delay is reduced in the next reference cycle, and further in the next reference cycle. The operation of decreasing the delay is repeated, and when the overflow occurs, the delay of the comparison frequency pulse fV becomes maximum again. At this time, the capacitor C is charged and discharged with a signal whose output pulse width changes with the output value of the accumulator 1 as shown in FIG.

[0012] Here, the switch 10 is turned on.
When the pulse generator 9 triggered by the reference frequency pulse fr outputs a pulse whose width is narrower than that of the reference frequency pulse fr, which is before the binary counter 3 starts counting, the potential of the capacitor C is the previous reference cycle. It is related to the discharge characteristic when being charged by the output of the magnitude comparator 2. The relationship between these states and timing is shown in FIGS. 4 and 5. In FIG. 5, the A> B output indicates the output when the capacitor C is not provided, and the A> B output and the voltage scale of the X-point potential do not match. That is, when the accumulator 1 overflows, the delay of the comparison frequency fV in the next reference cycle becomes maximum, and the "H" level time of the charge pump output (output of the phase comparator 5) becomes long, but the potential at the X point When the switch 10 is turned on / off, the potential at the Y point is temporarily lowered to a low potential. In the next reference cycle, the delay of the reference frequency pulse fV decreases and the time of the charge pump output at the "H" level also decreases. Then, the potential at the point Y that is temporarily dropped becomes higher than that in the previous reference cycle. Further, the same operation is performed in the next reference cycle. In such a series of operations, the periodical change in the charge pump output is canceled by the change in the potential at the point X. Therefore, the output voltage of the loop filter 6 becomes constant and the generation of spurious is suppressed.

FIG. 6 shows a fractional N according to the present invention.
FIG. 3 is a configuration block diagram showing another embodiment of the spurious cancel circuit of the synthesizer, showing an example of a frequency tracking type spurious cancel circuit. In FIG. 6, the components given the same reference numerals as those in FIG. 1 are components having the same function.
In this embodiment, in the configuration of FIG. 1, an adder 11 is provided between the output of the magnitude comparator 2 and the switch 10.
Is provided, and the divided voltage obtained by dividing the output of the voltage follower 12 that receives the output of the loop filter 6 by the resistors R3 and R4 is supplied as the other input of the adder 11.

FIG. 7 is a timing chart of signals at respective parts for explaining the operation of the circuit shown in FIG. As described above, in the circuit of FIG. 1, the output of the magnitude comparator 2 is received and the charge / discharge characteristics of the capacitor C and the O of the switch 10 controlled by the pulse gellator 9 are applied.
By the N / OFF operation, the potential at the point Y immediately before the loop filter 6 is dropped to a low voltage level for a short time to remove the step difference of the stepwise voltage. Also, because of that, VCO7
Is always controlled so that its phase is delayed, and when the accumulator 1 overflows, the phase error in the next reference cycle becomes maximum. These relationships are as shown in FIG. Here, when the data [M] of the counter 8 is changed and the frequency is changed, the Y-point potential which is the tuning voltage (control voltage) is changed. Therefore, since the low voltage level (X-point potential) at which the Y-point potential is dropped when the switch 10 is turned on does not change, correction of the error voltage that causes spurious is not appropriate.

Therefore, in this embodiment, the voltage follower 12 used as a buffer by the operational amplifier receives the tuning voltage of the VCO 7, is converted into a low voltage by the resistors R3 and R4, and is input to the adder 11 together with the X-point potential. .. The output of the adder 11 turns on the switch 10.
It is added to point Y by the / OFF control. As a result, the low voltage dropped to the ON operation of the switch 10 at the point Y changes in conjunction with the tuning voltage, so that the error voltage is corrected by following the frequency.

[0016]

As described above, according to the present invention, the D / A converter is unnecessary, and spurious cancellation can be performed over a wide frequency range with a simple circuit configuration. In addition, the component mounting area for that purpose is also reduced, and the cost and power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a spurious cancel circuit of a fractional-N synthesizer according to the present invention.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 3 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

5 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 6 is a block diagram showing another embodiment of the spurious scan cell circuit of the fractional-N synthesizer according to the present invention.

FIG. 7 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

[Explanation of symbols]

 1, 81 Accumulator 2 Magnitude comparator 3 Binary counter 4, 83 Frequency divider 5, 84 Phase comparator 6, 86 Loop filter 7, 87 VCO 8, 88 (Swallow) counter 9 Pulse generator 10 Switch 11, 85 Adder 12 Voltage Follower 82 D / A converter

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] January 28, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a spurious cancel circuit of a fractional-N synthesizer according to the present invention.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 3 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

5 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 6 is a block diagram showing another embodiment of the spurious scan cell circuit of the fractional-N synthesizer according to the present invention.

FIG. 7 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 8 is a diagram showing an example of a conventional fractional-N synthesizer circuit.

FIG. 9 is a timing chart of the above-mentioned operation for each signal of the circuit in which the D / A converter 82 and the adder 85 are removed from the circuit of FIG. ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 22, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a spurious cancel circuit of a fractional-N synthesizer according to the present invention.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 3 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

5 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 6 is a block diagram showing another embodiment of the spurious cancel circuit of the fractional-N synthesizer according to the present invention.

FIG. 7 is a timing chart of signals of respective parts for explaining the operation of the embodiment of FIG.

FIG. 8 is a diagram showing an example of a conventional fractional-N synthesizer circuit.

FIG. 9 is a timing chart of the above-mentioned operation for each signal of the circuit in which the D / A converter 82 and the adder 85 are removed from the circuit of FIG.

[Explanation of Codes] 1, 81 Accumulator 2 Magnitude comparator 3 Binary counter 4, 83 Frequency divider 5, 84 Phase comparator 6, 86 Loop filter 7, 87 VCO 8, 88 (Swallow) counter 9 Pulse generator 10 Switch 11, 85 Adder 12 Voltage follower 82 D / A converter

Claims (4)

[Claims] 1. A frequency divider for dividing a master clock to output a reference frequency pulse, a phase comparator for outputting a phase difference error signal between the reference frequency pulse and another input pulse, and this phase comparator. , A voltage control oscillator whose oscillation frequency is controlled by the output of this loop filter, the output of this voltage control oscillator is counted, and the count output is used as the other input pulse of the phase comparator. A counter for outputting, an accumulator for accumulating input data and changing the division ratio of the counter at the time of overflow, a binary counter for binary counting the master clock, and an output of the accumulator being larger than the output of the binary counter. A magnitude comparator that produces an output, and A capacitor connected between the output of the magnitude comparator and the ground, a pulse generator that is triggered by the reference frequency pulse to generate a predetermined pulse, and is ON / OFF controlled by the output from the pulse generator. A spurious cancellation circuit for a fractional-N synthesizer, comprising: a switch for adding the output of the magnitude comparator to the output of the phase comparator. 2. A frequency divider for dividing a master clock to output a reference frequency pulse, a phase comparator for outputting a phase error signal between the reference frequency pulse and another input pulse, and a phase comparator for the phase comparator. A loop filter that smoothes the output, a voltage controlled oscillator whose oscillation frequency is controlled by the output of this loop filter, and the output of this voltage controlled oscillator is counted, and the count output is output as the other input pulse of the phase comparator. A counter for accumulating input data, and an accumulator for changing the frequency division ratio of the counter at the time of overflow, and reducing the tuning voltage input to the voltage controlled oscillator for a short time just before the loop filter. A fractional-N synthesizer spurious cancel circuit. 3. The spurious cancel circuit of the fractional-N synthesizer according to claim 2, wherein the tuning voltage to be reduced is changed according to the value of the accumulator output data. 4. A frequency divider that divides a master clock to output a reference frequency pulse, a phase comparator that outputs a phase error signal between the reference frequency pulse and another input pulse, and a phase comparator of this phase comparator. A loop filter that smoothes the output, a voltage controlled oscillator whose oscillation frequency is controlled by the output of this loop filter, and the output of this voltage controlled oscillator is counted, and the count output is output as the other input pulse of the phase comparator. Counter, an accumulator that accumulates input data and changes the division ratio of the counter when it overflows, a binary counter that binary-counts the master clock, and an output when the output of the accumulator is greater than the output of the binary counter. And a magnitude comparator that generates A capacitor connected between the output of the magnitude comparator and ground, a pulse generator triggered by the reference frequency pulse to generate a predetermined pulse, and a voltage corresponding to the output of the loop filter is added to the output of the magnitude comparator. A spurious cancel circuit for a fractional-N synthesizer, comprising: an adder; and a switch that is ON / OFF controlled by an output from the pulse generator and that adds the adder output to the phase comparator output when ON. ..