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JPH05242202A - Wiring design support device - Google Patents

Wiring design support device

Info

Publication number
JPH05242202A
JPH05242202A JP4075606A JP7560692A JPH05242202A JP H05242202 A JPH05242202 A JP H05242202A JP 4075606 A JP4075606 A JP 4075606A JP 7560692 A JP7560692 A JP 7560692A JP H05242202 A JPH05242202 A JP H05242202A
Authority
JP
Japan
Prior art keywords
wiring
information
signal line
connection
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4075606A
Other languages
Japanese (ja)
Inventor
Yoshikazu Ichiba
義和 市場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4075606A priority Critical patent/JPH05242202A/en
Publication of JPH05242202A publication Critical patent/JPH05242202A/en
Pending legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent input of wiring patterns except in a designated connection order by using a rat's nest to guide a user on a picture in the connection order of single-stroke signal lines at the time of input of wiring patterns. CONSTITUTION:A logical connection information extracting part 12 extracts single-stroke signal line designating information and connection designating information of connection pins with respect to a single-stroke signal line simultaneously with extraction of logical connection information from inputted circuit diagram information. Extracted information are stored in a logical connection information storage area 17 from an arranged wiring data control part 15. The logical connection information storage area 17 is retrieved by the arranged wiring data control part 15 to store the single-stroke signal line name and the connection order of its connection pins in a single-stroke signal line storage area 19. Single-stroke wiring processing is performed by the arranged wiring data control part 15 in following processings. In this case, lines (rat's nest) indicating connection between pins is displayed on the picture of a wiring pattern input part 14.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はプリント基板,セラミッ
ク基板の設計に係り、特に配線設計支援装置に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the design of printed boards and ceramic boards, and more particularly to a wiring design support device.

【0002】[0002]

【従来の技術】従来のこの種の配線設計支援装置はEW
S等の画面にプリント基板の配線設計データを映し出
し、操作者が配線データをグラフィカルに入力する際、
一筆書き配線の場合に特に接続順が指定されていても一
般配線と同じ表示を行うため、操作者の方で予め部品ピ
ンの接続順を調べておき、画面上の配線データと見比べ
ながら入力していた。
2. Description of the Related Art A conventional wiring design support device of this type is EW
When the wiring design data of the printed circuit board is displayed on the screen such as S and the operator graphically inputs the wiring data,
Even if the connection order is specified in the case of single-stroked wiring, the same display as for general wiring is displayed.Therefore, the operator should check the connection order of component pins in advance and enter it while comparing it with the wiring data on the screen. Was there.

【0003】[0003]

【発明が解決しようとする課題】上述した従来の配線設
計支援装置では、一筆書き配線で接続順が指定された場
合、操作者がまず入力前に予め一筆書き配線信号につい
て接続する部品ピンの名称,位置,接続順について調べ
ておかなければならないという課題があった。また、画
面上で実際に配線設計する際、先に調べた部品ピンを画
面上から探さなければならないという課題があり、さら
にこうして入力した配線パターンの接続順が正しいかど
うか保証されていないというなどの課題があった。
In the above-described conventional wiring design support apparatus, when the connection order is designated by the one-stroke writing wiring, the operator first names the component pin to be connected in advance for the one-stroke writing wiring signal before inputting. However, there was a problem that we had to check the position and connection order. In addition, when actually designing the wiring on the screen, there is a problem that the component pin that was previously checked must be searched from the screen, and it is not guaranteed that the connection order of the input wiring pattern is correct. There was a problem.

【0004】[0004]

【課題を解決するための手段】本発明の配線設計支援装
置は、プリント基板またはセラミック基板の配線パター
ン設計において、回路図入力の際,一筆書き信号線の指
示とこの信号線の接続順の指示を行う指示手段と、部品
配線情報を入力させる情報入力手段と、配線パターン入
力の際,上記一筆書き信号線の指示された接続順をラッ
ツネスト(接続すべきピンとピンを示す直線表示のこ
と)を用いて案内する案内手段と、上記情報入力手段に
より入力された配線パターン情報を外部ファイルへ出力
する出力手段を備えるものである。
According to the wiring design support apparatus of the present invention, in the wiring pattern design of a printed circuit board or a ceramic substrate, when a circuit diagram is input, a single-stroke signal line instruction and a connection order of this signal line are indicated. And an information input means for inputting component wiring information, and a wiring pattern input, the ratt nest (the straight line indicating the pin to be connected and the pin to be connected) It is provided with a guiding means for guiding by using and an output means for outputting the wiring pattern information inputted by the information inputting means to an external file.

【0005】[0005]

【作用】本発明においては、一筆書き信号線の接続順を
配線パターン入力の際に画面上にラッツネストを用いて
案内する。
In the present invention, the connection order of the one-stroke writing signal lines is guided by using the ratsnest on the screen when the wiring pattern is input.

【0006】[0006]

【実施例】図1は本発明の一実施例を示すブロック図で
ある。この図1において、11は回路図入力部で、この
回路図入力部11は回路図入力の際,一筆書き信号線の
指示とこの信号線の接続順の指示を行う指示手段を構成
している。12はこの回路図入力部11の出力を入力と
する論理接続情報抽出部、13は部品配置入力部で、こ
の部品配置入力部13は部品配置情報を入力させる情報
入力手段を構成している。
FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 11 is a circuit diagram input section, and this circuit diagram input section 11 constitutes an instruction means for instructing a one-stroke writing signal line and an instruction of a connection order of this signal line when a circuit diagram is input. .. Reference numeral 12 is a logical connection information extraction unit that receives the output of the circuit diagram input unit 11, 13 is a component placement input unit, and this component placement input unit 13 constitutes information input means for inputting component placement information.

【0007】14は配線パターン入力部で、この配線パ
ターン入力部14は配線パターン入力の際,一筆書き信
号線の指定された接続順をラッツネストを用いて案内す
る案内手段を構成している。15は配置配線データ制御
部で、この配置配線データ制御部15は上記情報入力手
段により入力された配線パターン情報を外部ファイルへ
出力する出力手段を構成している。16は部品ライブラ
リ、17は論理接続情報記憶域、18は配置配線情報記
憶域、19は一筆書き信号線記憶域、20は配線データ
ファイルである。
Reference numeral 14 denotes a wiring pattern input section, which constitutes a guiding means for guiding the designated connection order of the one-stroke writing signal line by using a rat's nest when the wiring pattern is inputted. Reference numeral 15 is a placement and routing data control unit, and the placement and routing data control unit 15 constitutes an output unit for outputting the wiring pattern information input by the information input unit to an external file. Reference numeral 16 is a parts library, 17 is a logical connection information storage area, 18 is a placement / wiring information storage area, 19 is a one-stroke writing signal line storage area, and 20 is a wiring data file.

【0008】このように、本発明による配線設計支援装
置は、回路図入力部11と論理接続情報抽出部12と部
品配置入力部13と配線パターン入力部14と配置配線
データ制御部15と論理接続情報記憶域17と配置配線
情報記憶域18と一筆書き信号線記憶域19より構成さ
れ、回路図情報と部品配置情報と部品ごとのT/H(ス
ルーホール)ランドや部品搭載パッドの位置や寸法を記
述した部品ライブラリ16を入力し、以降に述べる処理
を行った後配線データファイル20として外部へ出力す
る。
As described above, the wiring design support apparatus according to the present invention has the circuit diagram input unit 11, the logical connection information extraction unit 12, the component placement input unit 13, the wiring pattern input unit 14, the placement and routing data control unit 15, and the logical connection. It is composed of an information storage area 17, a layout / wiring information storage area 18 and a one-stroke writing signal line storage area 19, and circuit diagram information, component placement information, T / H (through hole) lands for each component, and the position and size of a component mounting pad. The component library 16 in which is described is input, and after the processing described below is performed, the wiring data file 20 is output to the outside.

【0009】図2および図3は図1の動作説明に供する
本発明による装置の処理方式を示したフローチャートで
ある。図4は一筆書き配線の例を示す説明図であり、図
5は図1における配線パターン入力部14の画面表示の
例を示す説明図である。
2 and 3 are flow charts showing the processing method of the apparatus according to the present invention for explaining the operation of FIG. FIG. 4 is an explanatory diagram showing an example of one-stroke writing wiring, and FIG. 5 is an explanatory diagram showing an example of a screen display of the wiring pattern input unit 14 in FIG.

【0010】つぎに図1に示す実施例の動作を図2ない
し図5を参照して説明する。まず、図2の処理ステップ
101で図1の回路図入力部11より回路図を描き込む
際、一筆書き信号線の指示およびこの信号線の接続ピン
の配線順の指定を行っておく。つぎに、処理ステップ1
02で処理ステップ101にて入力した回路図情報から
論理接続情報抽出部12において論理接続情報の抽出と
同時に、一筆書き信号線について一筆書き信号線指定情
報と接続ピンの接続順指定情報の抽出を行う。
The operation of the embodiment shown in FIG. 1 will be described below with reference to FIGS. First, when a circuit diagram is drawn from the circuit diagram input unit 11 of FIG. 1 in the processing step 101 of FIG. 2, a one-stroke writing signal line is designated and a connection order of connection pins of this signal line is specified. Next, processing step 1
In step 02, the logical connection information extracting unit 12 extracts the logical connection information from the circuit diagram information input in the processing step 101, and simultaneously extracts the one-stroke writing signal line designation information and the connection pin connection order designation information for the one-stroke writing signal line. To do.

【0011】そして、処理ステップ103で抽出した論
理接続情報と一筆書き信号線指定情報およびこの信号線
の接続順指定情報を配置配線データ制御部15より論理
接続情報記憶域17へ格納する。つぎに、処理ステップ
104で部品配置入力部13より、配線基板領域上の搭
載部品位置を指定する。その際、部品ごとのT/H(ス
ルーホール)ランドの位置、表面実装部品の場合は部品
搭載パッドを指定した部品ライブラリ16を参照する。
Then, the logical connection information extracted in the processing step 103, the one-stroke writing signal line designation information and the connection order designation information of this signal line are stored in the logical connection information storage area 17 from the placement and wiring data control unit 15. Next, in processing step 104, the position of the mounted component on the wiring board area is designated by the component placement input unit 13. At that time, the position of the T / H (through hole) land for each component is referred to, and in the case of a surface mount component, the component library 16 specifying the component mounting pad is referred to.

【0012】つぎに、処理ステップ105で配置配線デ
ータ制御部15で処理ステップ104より入力した部品
配置情報を配置配線情報記憶域18へ格納する。処理ス
テップ106で配置配線データ制御部15にて論理接続
情報記憶域17を検索し、一筆書き信号線名とその接続
ピンの接続順を一筆書き信号線記憶域19へ格納する。
Next, in process step 105, the placement and routing data control unit 15 stores the component placement information input from process step 104 in the placement and routing information storage area 18. In processing step 106, the layout and wiring data control unit 15 searches the logical connection information storage area 17, and stores the one-stroke writing signal line name and the connection order of the connection pin in the one-stroke writing signal line storage area 19.

【0013】そして、以降の処理より配置配線データ制
御部15にて、一筆書き配線処理を行っていく。まず、
処理ステップ107で一筆書き信号線名を一筆書き信号
線記憶域19より1つ取り出す。つぎに、処理ステップ
108でこの取り出した一筆書き信号線のソースピンを
配線パターン入力部14にて明示する。そして、処理ス
テップ109にて取り出したこの一筆書き信号線の接続
順カウンターnを0にする。ここでn=0はソースピン
を指すことになる。処理ステップ110でこの信号線の
第n番目のピンと第n+1番目のピン間が接続している
ことを示す直線(ラッツネスト)を配線パターン入力部
14の画面上に表示する。
Then, the placement / wiring data control unit 15 carries out a one-stroke writing wiring process from the subsequent processes. First,
In process step 107, one stroke-writing signal line name is retrieved from the stroke-writing signal line storage area 19. Next, in the processing step 108, the wiring pattern input unit 14 clearly indicates the source pin of the one-stroke writing signal line extracted. Then, the connection order counter n of the one-stroke writing signal line extracted in the processing step 109 is set to zero. Here, n = 0 means a source pin. In processing step 110, a straight line (rats nest) indicating that the n-th pin and the (n + 1) -th pin of this signal line are connected is displayed on the screen of the wiring pattern input unit 14.

【0014】処理ステップ111で配線パターン入力部
14の画面上に表示されたラッツネストを見ながら第n
番ピンと第n+1番ピン間の配線パターンを操作者に描
かせ、配置配線情報記憶域18へ配線パターン情報を格
納する。図5は配線パターン入力部14の画面表示の例
を示したもので、n=0の時、のラッツネストが表示
されn=1の時はのラッツネストが表示され、以下n
がインクリメントされるたびに,のラッツネストが
表示される。
At the processing step 111, the nth nth is seen while observing the rat's nest displayed on the screen of the wiring pattern input section 14.
The operator draws the wiring pattern between the pin #n and the pin n + 1, and the wiring pattern information is stored in the placement / wiring information storage area 18. FIG. 5 shows an example of a screen display of the wiring pattern input unit 14. When n = 0, the ratsnest of is displayed, and when n = 1, the ratsnest of is displayed.
A rat's nest of is displayed each time is incremented.

【0015】つぎに、判断ステップ112で第n番ピン
と第n+1番ピンが配線パターンによって接続されたか
を調べ、接続されている場合は処理ステップ113で第
n番ピンと第n+1番ピンの間に表示されていたラッツ
ネストを消去する。そして、処理ステップ114で一筆
書き信号線の接続順カウンターnをインクリメントし、
判断ステップ115でn+1が一筆書き信号線の終端ピ
ンの接続順を超えたか調べ、超えるまで処理ステップ1
10から判断ステップ115を繰り返す。この判断ステ
ップ115が真になったら次の判断ステップ116で先
の一筆書き信号線記憶域が空になっているか調べ、空に
なるまで処理ステップ107から判断ステップ116を
繰り返す。
Next, in a decision step 112, it is checked whether or not the nth pin and the n + 1th pin are connected by a wiring pattern, and if they are connected, a processing step 113 displays between the nth pin and the n + 1th pin. Erase the rat's nest that had been done. Then, in processing step 114, the connection order counter n of the one-stroke writing signal line is incremented,
In the judgment step 115, it is checked whether n + 1 exceeds the connection order of the termination pin of the one-stroke writing signal line, and until it exceeds the processing step
The determination step 115 is repeated from 10. When this judgment step 115 becomes true, it is checked in the next judgment step 116 whether the previous one-stroke writing signal line memory area is empty, and the processing steps 107 to 116 are repeated until it becomes empty.

【0016】以上のようにして、回路図上で指定された
一筆書き信号線の配線パターンを入力が完了したら、残
りの一般信号線の配線作業を行い、配置配線情報記憶域
18へ配線パターン情報を格納する。そして、つぎの処
理ステップ118で全ての信号線の配線パターン情報を
配置配線情報記憶域18から取出し、配線データファイ
ル20として外部へ出力する。図4は以上の処理にて作
成された一筆書き信号線の配線パターンの例である。
As described above, when the wiring pattern of the one-stroke writing signal line designated on the circuit diagram is input, the remaining general signal lines are wired, and the wiring pattern information is stored in the layout / wiring information storage area 18. To store. Then, in the next processing step 118, the wiring pattern information of all the signal lines is taken out from the placement / wiring information storage area 18 and output to the outside as a wiring data file 20. FIG. 4 is an example of the wiring pattern of the one-stroke writing signal line created by the above processing.

【0017】[0017]

【発明の効果】以上説明したように本発明は、一筆書き
信号線の接続順を配線パターン入力の際に画面上にラッ
ツネストを用いて案内することにより、操作者が指定さ
れた接続順以外の配線パターンを入力することを防止
し、さらに装置側から案内してくれるので操作者が予め
一筆書き信号線名やその接続順および部品ピンの位置を
予め調査しておく等の前準備の工数を不要にすることが
できる効果がある。
As described above, the present invention guides the connection order of the one-stroke writing signal line on the screen by using ratsnest when the wiring pattern is input, so that the connection order other than the connection order designated by the operator can be obtained. It prevents inputting of wiring patterns and guides from the device side, so the operator can check the number of signal lines written in one stroke, their connection order and the position of component pins in advance. There is an effect that can be made unnecessary.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】図1の動作説明に供する本発明による装置の処
理方式を示したフローチャートである。
FIG. 2 is a flowchart showing a processing method of the apparatus according to the present invention, which is used for explaining the operation of FIG.

【図3】図1の動作説明に供する本発明による装置の処
理方式を示したフローチャートである。
3 is a flowchart showing a processing method of the apparatus according to the present invention, which is used for explaining the operation of FIG.

【図4】図1の動作説明に供する一筆書き配線の例を示
す説明図である。
FIG. 4 is an explanatory diagram showing an example of one-stroke writing wiring used to explain the operation of FIG. 1;

【図5】図1における配線パターン入力部の画面表示の
例を示す説明図である。
5 is an explanatory diagram showing an example of a screen display of a wiring pattern input unit in FIG.

【符号の説明】[Explanation of symbols]

11 回路図入力部 12 論理接続情報抽出部 13 部品配置入力部 14 配線パターン入力部 15 配置配線データ制御部 16 部品ライブラリ 17 論理接続情報記憶域 18 配置配線情報記憶域 19 一筆書き信号線記憶域 20 配線データファイル 11 Circuit Diagram Input Section 12 Logical Connection Information Extraction Section 13 Component Placement Input Section 14 Wiring Pattern Input Section 15 Placement and Wiring Data Control Section 16 Component Library 17 Logical Connection Information Storage Area 18 Placement and Wiring Information Storage Area 19 One-stroke Writing Signal Line Storage Area 20 Wiring data file

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 プリント基板またはセラミック基板の配
線パターン設計において、回路図入力の際,一筆書き信
号線の指示とこの信号線の接続順の指示を行う指示手段
と、部品配置情報を入力させる情報入力手段と、配線パ
ターン入力の際,前記一筆書き信号線の指定された接続
順をラッツネストを用いて案内する案内手段と、前記情
報入力手段により入力された配線パターン情報を外部フ
ァイルへ出力する出力手段を備えてなることを特徴とす
る配線設計支援装置。
1. When designing a wiring pattern on a printed circuit board or a ceramic substrate, when a circuit diagram is input, an instruction means for instructing a one-stroke signal line and an instruction for connecting the signal line, and information for inputting component placement information. Input means, guide means for guiding the specified connection order of the one-stroke writing signal line using rat's nest when inputting the wiring pattern, and output for outputting the wiring pattern information input by the information input means to an external file A wiring design support device comprising means.
JP4075606A 1992-02-27 1992-02-27 Wiring design support device Pending JPH05242202A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4075606A JPH05242202A (en) 1992-02-27 1992-02-27 Wiring design support device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4075606A JPH05242202A (en) 1992-02-27 1992-02-27 Wiring design support device

Publications (1)

Publication Number Publication Date
JPH05242202A true JPH05242202A (en) 1993-09-21

Family

ID=13581041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4075606A Pending JPH05242202A (en) 1992-02-27 1992-02-27 Wiring design support device

Country Status (1)

Country Link
JP (1) JPH05242202A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6502228B1 (en) 1999-06-16 2002-12-31 Nec Toppan Circuit Solutions, Inc. Route determination support device, route determination support method and storage medium storing therein program for executing method thereof, and printed substrate wiring method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6502228B1 (en) 1999-06-16 2002-12-31 Nec Toppan Circuit Solutions, Inc. Route determination support device, route determination support method and storage medium storing therein program for executing method thereof, and printed substrate wiring method

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