JPH05235288A - Manufacture of bimos semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacture of a BiMOS semiconductor device capable of forming a silicide layer only in a required part without deteriorating high-frequency characteristics of a bipolar transistor and sacrificing the degree of integration and controlling a silicide reaction. CONSTITUTION:A manufacture of a BiMOS semiconductor device comprises the steps of an ion implantation to a contact region through a contact hole by a self-alignment, forming an oxide film 10 on the surface of the contact hole by a CVD method, a thermal treatment for activating an impurity of the contact region, forming an opening 143 for forming a Schottky diode, forming a high-melting metal film, a silicide reaction of the high-melting metal film with a substrate, removing the high-melting metal film unreacted, and removing the oxide film 10 on the surface of the contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a BiMOS semiconductor device having a polycide gate and a Schottky diode designed according to the submicron rule.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there were the following. Figure 3 is BiMO
In order to speed up the input / output circuit of the S gate array, TT
FIG. 3 is a schematic cross-sectional view of a circuit of a bipolar transistor with a Schottky clamp diode (hereinafter referred to as Schottky transistor) used as an L output buffer transistor.

As shown in this figure, a Schottky diode 1 generally comprises a base 3 of a bipolar transistor 2.
Since it is manufactured as an integrated structure connected to the collector 4 and the collector 4, the description will be given with this integrated structure. In addition, 5 is an emitter. 4 to 6 are cross-sectional views of manufacturing steps of a conventional BiMOS semiconductor device with a Schottky diode,
Each figure schematically shows a cross section of the structure obtained in the manufacturing stage.

(A) First, as shown in FIG.
An N ⁺ type buried layer 101 is buried in the type silicon substrate 100, and a P type epitaxial layer 102 is further provided on the substrate 100. Next, the P-type epitaxial layer 10
An N-type collector and a well region 103 are continuously provided on the upper side of the second buried layer 101. Next, a field oxide film 104 is formed by the LOCOS method to form a Schottky transistor area 105, a gate polycide film wiring extraction area 106, and a PMOS transistor area 1.
A wafer 108 on which No. 07 and No. 07 are formed is prepared.

(B) As shown in FIG. 4B, a gate oxide film 109 to be a gate insulating film of a MOS transistor is formed on this wafer 108. Next, the wafer 10
After forming a polysilicon film on the entire surface of 8 by a low pressure CVD method and forming a tungsten silicide film (hereinafter referred to as WSi _X ) by a sputtering method, a well-known photolithography
The gate polycide wiring 110 and the gate electrode 111 of the PMOS transistor are formed by using the etching technique. The gate polycide wiring 110 and the gate electrode 111 are each composed of a polysilicon layer 112 having phosphorus as an impurity added as a lower layer and a WSi _X film 113 as an upper layer. A film 114 having a film thickness of about 200 Å which acts as a protective film (protective film) at the time of ion implantation for forming a high concentration impurity region of a source / drain layer or a base layer in a later step. Is.

(C) As shown in FIG. 4C, a Schottky transistor area 105 of the wafer 108.
Then, as the base layer 115 of the bipolar NPN transistor, a P-type diffusion region having a surface impurity concentration of 1E18 / cm ³ is formed with a diffusion depth of 0.3 μm. (D) As shown in FIG. 4D, a well-known photolithographic film is formed on the oxide film 114 in the Schottky transistor area 105.
An etching technique is used to open a window 116 for forming an emitter diffusion region to expose the wafer surface. After that, a polysilicon film is grown to 2000 Å on the entire surface of the wafer 108 by a low pressure CVD method. In order to form a diffusion source for forming an emitter diffusion region, As (arsenic) ions are implanted into the film, and a well-known photolithographic etching technique is used to further form an emitter electrode / emitter diffusion region for a Schottky transistor. The diffusion source 117 for forming is patterned.

(E) As shown in FIG. 5A, a well-known photolithography technique is used to form a resist film 119 in which the collector extraction region 118 of the Schottky transistor area 105 is opened. 119 is used as a mask to implant As ions, and a collector extraction region 118 is formed.
To form. (F) The resist film 119 on the wafer 108 is removed, and as shown in FIG. 5B, a resist film 121 in which the base extraction region 118 of the Schottky transistor region 105 and the PMOS transistor region 107 are opened is formed. Then, BF ₂ ions are implanted using the resist film 121 as a mask to form the P-type high concentration impurity 122 and the base extraction region 120.

(G) As shown in FIG. 5C, a PSG film 123, for example, is formed as an interlayer insulating film on the upper surface of the wafer 108.
Is provided by the CVD method, and then heat treatment is performed at 900 to 950 ° C. for about 30 minutes in a wet oxygen atmosphere. By this heat treatment, the PSG film 123 flows and the surface is flattened. At the same time, activation of the implanter injection layer and each region containing impurities are diffused and expanded. Due to this expansion, the base diffusion region 115 (see FIG. 4C) is deeply diffused from the original 0.3 μm to 0.45 μm to become the base layer 124, and the base extraction region 120 (see FIG. 5).
[See (b)] serves as the base extraction layer 125, and the collector extraction region 118 [see FIGS. 5A and 5B] serves as the collector extraction layer 126. From the diffusion source 117 to the base diffusion region 115, that is, in the base layer 124. To As
Impurities are diffused to form emitter layer 127. Furthermore, the high-concentration impurity region 122 [FIG.
(See (b)] is a source or a drain (here,
128). Then, the wafer 10
In FIG. 8, contact holes are formed by using the well-known photolithographic etching technique. In the Schottky transistor area 105, the base contact hole 129, the emitter contact hole 130 and the collector contact hole 131 are taken out, and the gate polycide film wiring is taken out. The gate contact hole 132 is formed in the area 106 for the PMO.
Source / drain contact holes 133 are opened in the S-transistor area 107, respectively.

(H) Base contact hole 129 and P
Resist 1 in which MOS source / drain contact hole 133 and gate contact hole 132 are opened
Boron ions are implanted using the mask 34 as a mask, and as shown in FIG.
Base contact region 13 of higher concentration than drain 128
5 and a PMOS source / drain contact region 136 and a gate contact region 137 are formed.

(I) The resist 134 is removed, and FIG.
As shown in (a), the collector contact hole 131
After forming the resist 138 having an opening
Phosphorus ions are implanted using 8 as a mask, and collector extraction layer 1
A collector contact region 139 having a higher concentration than 26 is formed. (J) The resist 138 was removed, and as shown in FIG. 6B, heat treatment was performed at 850 ° C. for about 30 minutes in an inert atmosphere.
(See (d)) is on the base contact layer 140, collector contact region 139 (see FIG. 6A) is on the collector contact layer 141, and PMOS source / drain contact region 136 (see FIG. 6 (a)) is on the PMOS source layer.
Each is formed on the drain contact layer 142.

The reason why the contact region is made to have a high concentration (1E20 or more) by ion implantation is that the contact resistance Rc is likely to be large in a submicron contact, for example, a normal P ⁺ layer of 0.8 μm □. And R
c is 200 to 300Ω. Since Rc largely depends on the impurity concentration, ion implantation is performed in the contact region to increase the concentration. As a result, Rc is 50-60Ω
And will be improved.

These steps are important steps for forming submicron bipolar and MOS transistors.
Generally, it is called auxiliary diffusion method, contact depot, or contact implantation, and is often used. However, this contact implantation requires heat treatment to activate the impurities, and this heat treatment causes diffusion of the emitter layer and the base layer,
The emitter layer 127 has a thickness of 0.2 μm, and the base layer 124 has a thickness of 0.5 μm.

The contact ions are also implanted into the gate contact hole 132 because WSi _X used for the polycide gate is known to have a stress (internal residual stress) which is determined by the history of heat treatment after formation. After the film flow process, strong tensile stress remains in the gate electrode and gate wiring, and when heat treatment is performed after forming the contact hole, there is no CVD film that suppresses stress in the contact hole on the gate wiring, so thermal shock At W
Si _X peels off. In order to prevent this peeling, ions are also implanted into the gate contact hole 132 and WSi _X
Is reducing stress.

(K) Collector region 103 of Schottky transistor area 105 of wafer 108 [FIG.
(See (a)) and the base take-out layer 125 [FIG. 6].
An opening 143 for forming a Schottky diode is formed on a partial surface of [a] by a well-known photolithographic etching technique, and the wafer 108 is formed by a sputter deposition method.
A refractory metal such as a Pt film having a thickness of 300 to 10 is formed on the entire surface of
00 Å is generated, and then a heat treatment (500 to 600 ° C.) for silicidizing the Pt film with the underlying silicon is performed to generate platinum silicide, and Pt on the oxide film is removed with aqua regia at about 70 ° C. is there. A Schottky diode silicide layer 144 is provided in the opening 143, and an emitter silicide layer 1 is provided in the emitter contact hole 130.
45, a collector silicide layer 146 is formed in the collector contact hole 131, and a source / drain silicide layer 147 is formed in the source / drain contact hole 133.

(L) As shown in FIG. 6D, when aluminum wiring 148 is formed in each contact hole and the opening 140 of the Schottky diode (see FIG. 6B), a BiMOS structure with a Schottky diode is formed. it can.

[0016]

However, in the BiMOS semiconductor device manufactured by such a conventional method,
Due to the structure, the contact resistance of the polycide gate contact (hereinafter referred to as Rc) increases, and there is a problem that the manufacturing yield cannot be increased. Hereinafter, a brief description will be given using steps (H) to (L) of FIGS. Figure 5
(D), as described in the explanation of the conventional method, boron ions are implanted into the gate contact hole 132 for the purpose of preventing exfoliation of WSi _x on the polycide, and a high concentration of impurities (8E20 pieces / cm ³ or more) The gate contact region 137 containing is formed. Figure 6 (a)
Is a contact ion implantation into an N ⁺ region, for example, a collector extraction region. Even if phosphorus ions are implanted into the gate contact hole 132 instead of boron ions, WSi _x
Prevention of peeling is possible. In FIG. 5B, heat treatment is performed to activate impurities in each contact region where ion implantation is performed.
The impurity of (d)] has an impurity diffusion coefficient in WSi _x that is four orders of magnitude larger than that of Si. Therefore, the WSix film 113 of the polycide gate wiring 110 is formed in the contact hole 132.
Is diffused to the outer periphery of the film and contains a high concentration of impurities to form a WSi _X film 149 [see FIG. 6B]. In FIG. 6C, an opening for forming a Schottky diode is formed, and Pt is formed.
After the film is formed, a heat treatment for the silicide reaction is performed, and the WSi _X film 149 of the gate contact hole 132 is formed.
It is considered that Pt is diffused on the surface of FIG. 6B. However, the WSi _x film is etched by aqua regia etching to remove the residual Pt on the oxide film, and the gate contact hole 132 is a cross section in which the side etch 150 is formed. FIG. 6D shows the aluminum wiring 148. Although it is formed, the gate contact hole 132 has a very poor coverage due to the side etch 150 (FIG. 6C), resulting in an increase in Rc and, in the worst case, a contact cross-section line. Occurs.

Originally, the crystallized WSi _X is insoluble in aqua regia, and the clear cause of etching is unknown.
The following factors can be raised. Since the impurities implanted into the WSi _x by the contact implantation were high in concentration (8E20 / cm ³ or more), the crystallization of the WSi _x was incomplete in the heat treatment after the contact implantation, so that the impurities were etched.

It is presumed that Pt was diffused by the platinum silicide treatment on the surface of WSix and in it, and the Pt promoted the aqua regia etching by the local cell effect. As a countermeasure, (1) the temperature of the heat treatment after the contact implantation is increased, but the probability of occurrence of peeling of the WSi _x film increases. There is a point that it is difficult to form a high Ft bipolar transistor, and (2) low temperature silicide reaction (4)
It may be possible to suppress Pt diffusion due to (00 ° C. or less), but with the slowing of the silicide reaction, the influence of a natural oxide film (about twice as much as usual) formed on the surface of the polysilicon film having a high impurity concentration of the emitter electrode. Reproducibility of φB (barrier height) deteriorates due to unstable platinum silicide composition ratio.
There is a problem that the slowdown of the silicide reaction in the P-type (boron) high-concentration region becomes conspicuous, and therefore manufacturing technical measures cannot be adopted.

On the other hand, as a method that does not use aqua regia etching, there is an aluminum Schottky, but it is necessary to share it with the wiring material, and it is essential to use pure aluminum having poor electromigration and stress migration resistance.
There is a problem that the degree of integration of the wiring is lowered, and a technically satisfactory product cannot be obtained. Therefore, an object of the present invention is to provide a method for manufacturing a BiMOS semiconductor device in which a silicide layer is formed only in a necessary portion without deteriorating the high frequency characteristics of a bipolar transistor, sacrificing the degree of integration, or suppressing a silicide reaction. And

[0020]

In order to achieve the above object, the present invention has a BiMOS including a bipolar transistor with a Schottky diode and a polycide gate, which has a step of increasing the impurity concentration of a contact region by self-alignment from a contact hole. In the method of manufacturing a semiconductor device, a step of implanting ions into the contact region in a self-aligned manner from the contact hole, a step of forming an oxide film on the surface of the contact hole by a CVD method, and a heat treatment step of activating impurities in the contact region. A step of forming an opening for forming a Schottky diode, a step of forming a refractory metal film, a step of performing a silicide reaction between the refractory metal film and the substrate, and a step of removing an unreacted refractory metal film. And the step of removing the oxide film on the surface of the contact hole. It is obtained by the Suyo.

C is formed on the surface of the above-mentioned contact hole.
The order of the step of forming the oxide film by the VD method and the heat treatment step of activating the impurities in the contact region may be reversed.

[0022]

According to the present invention, in the method of manufacturing a BiMOS semiconductor device, an oxide film having a thickness capable of suppressing a silicide reaction is formed before forming an opening for forming a Schottky diode, and a silicide layer is formed in a contact hole. While preventing the formation, after forming the silicide layer only in the Schottky diode region, the oxide film in the contact hole is removed again. Therefore, since an oxide film is present on the surface of each contact hole and is much thicker than the oxide film thickness through which Pt can pass in the silicidation reaction, no silicide film is formed on the surface of each contact hole, and the aqua regia treatment thereafter is performed. This removes Pt and protects the WSi _x film.

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention B
FIG. 6 is a cross-sectional view of the main part manufacturing process of the iMOS semiconductor device. Note that description of steps (A) to (I) in FIGS. 4, 5, and 6, which are the same processes as in the conventional example, is omitted. The same parts as those in the conventional example are designated by the same reference numerals.

First, as in the conventional case, the resist 138 in FIG. 6 (a) is removed following the steps (A) to (H) of FIG. 4, FIG. 5 and FIG. 6 and is shown in FIG. 1 (a). As described above, the non-doped oxide film 10 is formed on the surface of the wafer 108 by the CVD technique to a thickness of 1000 to 1500 Å. After that, heat treatment was performed at 850 ° C. for about 30 minutes in an inert atmosphere.
5 [see FIG. 5 (d)] is the base contact layer 140,
The collector contact region 139 [see FIG. 6 (a)] is in the collector contact layer 141, and the PMOS source / drain contact region 136 [see FIG. 6 (a)] is in the PMOS.
Each of the source / drain contact layers 142 is formed.

Next, as shown in FIG. 1B, a well-known photolithographic etching technique is applied to the surface of the collector region 103 of the Schottky transistor area 105 of the wafer 108 and a part of the surface of the base take-out layer 125. make use of,
An opening 143 for forming a Schottky diode is formed, and a refractory metal, for example, a Pt film having a thickness of 300 to 1000 Å is formed on the entire surface of the wafer 108 by a sputter deposition method, and then a silicidation reaction between the Pt film and the underlying silicon is performed. Heat treatment (500 to 600 ° C.) is performed to generate platinum silicide, and Pt on the oxide film is formed with aqua regia at about 70 ° C.
Is removed. The silicide layer 144 for the Schottky diode is formed only in the opening 143.

Next, as shown in FIG. 1C, the base contact layer 140 and the emitter contact hole 130.
The resist pattern 11 in which each hole of each layer of the collector contact layer 141, the gate contact hole 128, and the source / drain contact layer 142 is opened is formed by the well-known photolithography technique, and the non-doped oxide film 10 is removed by etching. It is a thing.

Next, as shown in FIG. 1 (d), the resist pattern 11 is removed, and aluminum wiring 148 is formed in each contact hole and the opening of the Schottky diode, and a BiMOS structure with a Schottky diode is formed. it can. FIG. 2 is a diagram showing the relationship between the non-doped oxide film thickness and the polycide gate wiring resistance in the BiMOS semiconductor device of the present invention. In the case where there is no non-doped oxide film (conventional method), polysilicon which is the lower layer of the polycide gate wiring is shown. The resistance was 12 to 14 MΩ, but the oxide film thickness was 500 Å, 1000 Å, 1500 Å, and thus the low resistance value was exhibited, and if it was 1000 Å or more, it was almost the same value as 6000 Å which was sufficiently thick. The contact resistance Rc, which was 17 to 760Ω in the conventional method, is 0.8 μm □ in the present invention and 3.81 ± 1.2.
An improvement was also seen in the absolute value and variation with 3Ω (σ).

Further, in the case of manufacturing by the conventional method, a silicide film is formed also in the emitter contact hole,
Although there is a problem that residual stress is generated in the emitter electrode due to the silicidation reaction and the variation of the hfe value of the bipolar transistor increases, the silicidation reaction of the emitter contact hole can be prevented in the present invention. Reproduction is also improved.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0030]

As described above in detail, according to the present invention, before or after the contact ion implantation for reducing the contact resistance Rc, a non-doped oxide film is formed on the wafer surface by 1000 to 1500Å using the CVD technique. Since each contact hole has an oxide film on its surface and is much thicker than the oxide film that allows Pt to pass through in the silicide reaction, no silicide film is formed on each contact hole surface. The Pt is removed and the WSi _x film is protected by the subsequent aqua regia treatment.

With this structure, the Rc of the polycide gate contact is improved while maintaining the high frequency characteristics of the bipolar transistor and sacrificing the degree of integration, and maintaining the reproducibility of φB (barrier height). ..
If a non-doped oxide film is formed after contact ion implantation and heat treatment for activation of contact ion implantation is performed, the non-doped oxide film is densified, has the same film quality as the thermal oxide film, and can be further thinned.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an essential part manufacturing process of a BiMOS semiconductor device showing an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a non-doped oxide film thickness and a polycide gate wiring resistance in a BiMOS semiconductor device of the present invention.

FIG. 3 is a circuit and schematic sectional view of a conventional bipolar transistor with a Schottky clamp diode.

FIG. 4 Conventional BiMOS with Schottky diode
It is a manufacturing process sectional view (1) of a semiconductor device.

FIG. 5 Conventional BiMOS with Schottky diode
It is a manufacturing process sectional view of a semiconductor device (the 2).

FIG. 6 Conventional BiMOS with Schottky diode
It is a manufacturing process sectional view of a semiconductor device (the 3).

[Explanation of Codes] 10 Non-Doped Oxide Film 11 Resist Pattern in Which Each Hole in Each Layer is Opened 103 Collector Region 105 Schottky Transistor Area 108 Wafer 125 Base Extraction Layer 130 Emitter Contact Hole 132 Gate Contact Hole 135 Base Contact Region 136 PMOS Source -Drain contact region 139 Collector contact region 140 Base contact layer 141 Collector contact layer 142 PMOS source / drain contact layer 143 Opening for forming Schottky diode 144 Schottky diode silicide layer 148 Aluminum wiring

Claims (4)

[Claims] 1. A method for manufacturing a BiMOS semiconductor device including a bipolar transistor with a Schottky diode and a polycide gate, the method including a step of increasing an impurity concentration of a contact region by self-alignment from a contact hole, comprising: (a) self-alignment from the contact hole. And (b) forming an oxide film by a CVD method on the surface of the contact hole, (c) heat treating step of activating impurities in the contact area, and (d) Schottky A step of forming an opening for forming a diode; (e) a step of forming a refractory metal film; (f) a step of subjecting the refractory metal film and a substrate to a silicidation reaction; A step of removing the melting point metal film, and (h) a step of removing the oxide film on the surface of the contact hole Method of manufacturing a BiMOS semiconductor device characterized by subjecting. 2. The method of manufacturing a BiMOS semiconductor device according to claim 1, wherein the oxide film in the step (b) has a film thickness of 1000 Å or more.
S Semiconductor device manufacturing method. 3. A method for manufacturing a BiMOS semiconductor device including a bipolar transistor with a Schottky diode and a polycide gate, which comprises a step of increasing the impurity concentration of a contact region by self-alignment from a contact hole, wherein (a) self-alignment is performed from a contact hole. Ion implantation into the contact region, (b) heat treatment process to activate impurities in the contact region, (c) formation of an oxide film by CVD on the contact hole surface, and (d) formation of a Schottky diode A step of forming an opening for the purpose of: (e) a step of forming a refractory metal film; (f) a step of silicidizing the refractory metal film with the substrate; (g) an unreacted refractory metal film And (h) removing the oxide film on the surface of the contact hole. Method of manufacturing a BiMOS semiconductor device according to symptoms. 4. The BiMOS semiconductor device manufacturing method according to claim 3, wherein the film thickness of the oxide film in the step (c) is 1000 Å or more.
S Semiconductor device manufacturing method.