JPH05234005A - Write compensation circuit - Google Patents

Abstract

PURPOSE:To compensate a peak shift effectively by utilizing a serial data series whose peak shift corrected for the floppy disk drive of a floppy disk device. CONSTITUTION:A pulse interval between a noticing pulse in the serial data column and pulses neighboring it are discriminated by a pulse interval measurement circuit 2, a shift register 3 and a comparison circuit 4. In accordance with the result of this discrimination, each noticing pulse delayed by 0 to 2 times of a delaying amount alpha by delay circuits 5, 6 is selected by a selection switch 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write compensating circuit which is used, for example, in a so-called floppy disk device and which applies so-called peak shift compensation to a write serial data string to a floppy disk.

[0002]

[Prior Art]

A schematic configuration of a conventional floppy disk device is shown in FIG. In FIG. 5, the floppy disk device is simply a host computer 100.
, Floppy disk drive 110, and head 11
It is composed of 1 and 1. Further, the host computer 100 of the floppy disk device is the floppy disk 1
A floppy disk controller 10 including an encoder 103 for encoding write data for recording in 12 and a decoder 104 for decoding a read serial data string RD read from a floppy disk 112.
2 and a CPU (central processing unit) 101 that controls each unit and processes write and read data. In this floppy disk device, the write serial data string WD from the encoder 103 of the floppy disk controller 102 is sent to the head 111 via the floppy disk drive 110, and is written in the floppy disk 112. Further, the read serial data string RD read from the floppy disk 112 by the head 111 via the floppy disk drive 110 is decoded by the decoder 104 of the floppy disk controller 102 and sent to the CPU 101 in the subsequent stage.

Heretofore, when writing data to a floppy disk by the above-mentioned floppy disk device, for example, an FM (Frequency Modulati) is used.
on) recording method and MFM (Modified Frequency Modulat)
ion) recording method is generally used.

In the above-mentioned FM recording method, the data transfer rate of the serial data string recorded / reproduced on / from the floppy disk is, for example, 250 kbps, and the pulse intervals of the serial data string are of two types, 2 μs and 4 μs. There is. In the MFM recording method, the data transfer rate of the serial data string recorded / reproduced on / from the floppy disk is, for example, 500 kbps.
Then, each pulse interval of the serial data string is 2 μs, 3
There are three types, μs and 4 μs.

By the way, in recent years, it has been proposed to record data on the floppy disk at a higher density and a higher transfer rate. For example, in the MFM recording method, recording / recording on the floppy disk is performed.
The data transfer rate of the reproduced serial data string is 1 Mb
made in ps. In this case, there are three types of pulse intervals of the serial data string, 1 μs, 1.5 μs, and 2 μs.

[0007]

However, it is attempted to record / reproduce on / from a floppy disk at a high density and a high transfer rate as described above by using the head (head having a low resolution) of the conventional floppy disk device. Then, depending on the pattern of the serial data pulse train, so-called peak shift occurs, which causes a problem that an error is likely to occur during reading. That is, for example, as shown in FIG. 6, the pulse interval of, for example, 1 μs of the write serial data string WD (A in FIG. 6) is equal to the read serial data string RD.
In (B of FIG. 6), there occurs a problem of peak shift to a pulse interval of 1.2 μs, for example.

As shown in FIG. 7, when writing a write pulse WP consisting of two pulses at intervals of, for example, x μs to a floppy disk, the magnetization of the floppy disk is inverted according to the write pulse WP. It is considered that the isolated waveform is recorded in the opposite polarity by the write signal MR, and that when the floppy disk is played back, the isolated waveform interferes with each other and the composite waveform re shown by the solid line in the figure becomes the playback output. At this time, the position of the peak of the reproduction output deviates from the actually written position as indicated by the waveform im shown by the dotted line in the figure, and thus the reproduction pulse RP to be reproduced is displaced. .. This is called peak shift. Further, this peak shift is advanced peak shift ps _T and delayed peak shift ps
There is _D.

The maximum value of the peak shift is shown in FIG.
As shown in FIG. 6, for example, when a pulse group having a smaller pulse interval y among the three types of pulse intervals is sandwiched by the larger pulse interval Y. For example, the data transfer rate is 1 Mbps, and the pulse intervals are 1 μs and 1.5 μ.
In the case of three types of serial data strings of s and 2 μs, the maximum peak shift occurs when a pulse interval group of y = 1 μs as the pulse interval y is sandwiched by pulse intervals of Y = 2 μs as the pulse interval Y. Will occur. In FIG. 8, the same reference numerals as those in FIG. 7 are attached, and detailed description of each waveform is omitted.

Here, in the conventional floppy disk device, a peak shift compensating circuit for correcting the peak shift is provided in the floppy disk controller, and the peak shift compensating circuit predicts the pattern of the serial data pulse train. There are also those which are adapted to record on a floppy disk after compensating for the peak shift. That is, for example, as shown in FIG. 9, by performing peak shift correction on the pulse interval of the write serial data string WD (A in FIG. 9) to a pulse interval of 0.8 μs, for example, the read serial data string RD (FIG. 9). B)
Then, for example, data with a normal pulse interval of 1 μs is obtained.

However, when the conventional floppy disk drive as shown in FIG. 5 is manufactured, the floppy disk drive 110, which is separately manufactured, is usually mounted in the floppy disk drive. Disk device host computer 100 side (floppy disk controller 102 side)
Then, the resolution of the head 111 on the side of the floppy disk drive 110 cannot be managed. Therefore, the floppy disk controller 100 cannot judge whether or not the peak shift compensation should be applied to the serial data pulse train, and cannot set the optimum compensation amount, for example.

Therefore, the present invention has been proposed in view of the above situation, and the write compensation capable of effectively performing the peak shift compensation for the serial data string recorded on the floppy disk. The purpose is to provide a circuit.

[0013]

The write compensating circuit of the present invention is proposed in order to achieve the above-mentioned object, and a serial data string written in a recording medium is written in the recording medium. A write compensating circuit for compensating for shifting by a peak shift amount in a direction opposite to the peak shift direction occurring between the serial data sequence read from the recording medium and the serial data sequence read from the recording medium. A pulse relationship determining means for determining the relationship between the pulse of interest in the serial data string and the pulses before and after the pulse of interest, and each delayed pulse obtained by delaying the pulse of interest by 0 to n times the predetermined time. The delay means for outputting and the selecting means for selecting each delay pulse output of the delay means according to the judgment result of the pulse relation judging means.

Here, the pulse relationship determining means can determine the magnitude relationship of the pulse intervals between the pulse of interest in the serial data string and the pulses before and after the pulse of interest.

Further, the pulse relation judging means may judge whether or not the pulses before and after the pulse of interest in the serial data string are at predetermined positions.

Further, the write compensation circuit of the present invention is incorporated in the floppy disk drive of the floppy disk device. This makes it possible to compensate for the peak shift while ensuring the compatibility of the floppy disk drive as seen from the floppy disk controller and the compatibility of the medium (floppy disk) as seen from the floppy disk drive.

[0017]

According to the write compensating circuit of the present invention, the relationship between the pulse of interest in the serial data string and the pulses before and after it is determined, and the pulse of interest is determined for a predetermined time in accordance with the determination result. Each delay pulse delayed by 0 to n times is selected, and the selected serial data string is peak-shift corrected.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the write compensating circuit of the present embodiment is arranged such that, for a serial data string written on a recording medium such as a so-called floppy disk, the serial data string written on the floppy disk and the corresponding floppy disk are written. A write compensating circuit for compensating in the opposite direction of the peak shift generated between the serial data string read from the disk and the peak shift amount, and is supplied via an input terminal 1. Pulse relationship determination means for determining the relationship between a pulse of interest in a serial data string written to a floppy disk and pulses before and after the pulse of interest, and the pulse of interest is 0 to n times the predetermined time ( n is an integer, for example, n in this embodiment.
= 2), the delay circuits 5, 6 and 6 as delay means for outputting each delay pulse and the delay circuits 5, 6 and 7 described above.
And a selection switch 8 for selecting each delayed pulse output according to the judgment result of the pulse relation judging means (output of the comparison circuit 4).

Here, the pulse relationship determining means determines the magnitude relationship of the pulse intervals between the pulse of interest in the serial data string from the input terminal 1 and the pulses before and after the pulse of interest. For example, the pulse interval measuring circuit 2 for measuring the interval between each pulse of the serial data string, the pulse before and after the pulse of interest among the pulse interval values measured by the pulse interval measuring circuit 2, The shift register 3 stores the pulse interval value of the pulse to be generated and the comparison circuit 4 that compares the magnitudes of the two pulse interval values from the shift register 3 with each other.

In this embodiment, the input terminal 1 has a data transfer rate of 1 Mb according to the MFM recording method.
ps, 3 for each pulse interval of 1 μs, 1.5 μs, 2 μs
Suppose a type of serial data string is supplied.

In FIG. 1, the write serial data string via the input terminal 1 is supplied to the pulse interval measuring circuit 2. The pulse interval measuring circuit 2 measures the pulse interval of each pulse of the serial data string by counting the reference clock, for example. The pulse interval value (count value) is sent to the shift register 3.

The shift register 3 stores two pulse interval values supplied from the pulse interval measuring circuit 2. In other words, the shift register 3 concerned
In, the value of the pulse interval between the above-mentioned arbitrary pulse of interest and the pulses before and after it is stored. The pulse interval values stored in the shift register 3 are sent to the comparison circuit 4, respectively.

The comparison circuit 4 compares the magnitudes of the two pulse interval values (count values) supplied from the shift register 3 and outputs the comparison result as a selection control signal for the selection switch 8 in the subsequent stage.

On the other hand, the serial data string via the input terminal 1 is also sent to the delay circuits 5, 6, 7. The delay circuit 5 delays each pulse of the serial data string by a time (delay amount β) corresponding to the delay amount in the pulse interval measuring circuit 2, shift register 3, and comparison circuit 4. The delay circuit 6 delays each pulse of the serial data string by a time (delay amount α) corresponding to the delay amount β and a predetermined time (delay amount β +
α). The delay circuit 7 delays each pulse of the serial data string (delay amount β + 2α) by twice the delay amount β and a time (delay amount α) corresponding to a predetermined time (delay amount 2α). is there. In other words, each of the delay circuits 5, 6 and 7 delays the delay amount β, and the delay circuit 5 delays the delay amount α corresponding to the predetermined time by 0 times (only the delay amount β). The delay circuit 6 delays the delay amount α by 1 time (delay amount β + α), and the delay circuit 7 delays the delay amount α by 2 times (delay amount β + 2α).

In this embodiment, the delay amount α
Is about 0.08 for 1 μs, for example. In the case of a 4M floppy disk, the delay amount β is set to be, for example, more than 2 μs.

The delay pulses from the delay circuits 5, 6 and 7 are sent to the corresponding selected terminals a, b and c of the selection switch 8. The selection switch 8 selects each of the selected terminals a, b, c based on the output (selection control signal) of the comparison circuit 4.

More specifically, in the selection switch 8, the comparison result of the comparison circuit 4 indicates that, for example, one of the pulse intervals of the pulse of interest and the pulses before and after it is 1 μs and the other is 1.5μs or 2μs
If it indicates that the pulse interval is set to, the selection process is performed to select the output of the delay circuit in which the pulse of interest is shifted to the interval side of 1 μs by a certain amount. For example, if the other one has a pulse interval of 1.5 μs, the selection switch 8 selects the output of the delay circuit 6, and if the other one has a pulse interval of 2 μs, the selection switch 8 delays the delay. Select the output of circuit 7. If the other one also has a pulse interval of 1 μs, the output of the delay circuit 5 is selected.

That is, the delay amounts α and 2α in the delay circuits 6 and 7 become the peak shift correction amounts and are selected by the selection switch 8 in accordance with the pulse interval between the pulse of interest and the pulses before and after it. The above delay circuits 6 and 7
Output becomes a serial data string with peak shift correction. In addition, both the above-mentioned pulse interval and the other are 1 μm.
If the pulse interval is s, there is no need for peak shift correction, so the output of the delay circuit 5 is used as output data. The output of the selection switch 8 becomes the output of the writing correction circuit of this embodiment, and is output from the output terminal 9.

The write compensation circuit of the present invention can also be configured as shown in FIG. The configuration of FIG. 1 described above uses a counter (pulse interval measuring circuit 2) for pulse interval comparison, but in the example of FIG. 2, delay circuits 21, 2 of 1 μs and 2 μs are used for the pulse interval comparison.
2 is used. 2, the same components as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

That is, in the configuration of FIG. 2, a 1 μs delay circuit 21 and a 2 μs delay circuit 22 and a determination circuit 20 are provided as the pulse relationship determination means, and the pulse relationship determination means is used to determine the pulse data in the serial data string. It is determined whether or not the pulses before and after the above-mentioned pulse of interest are at a predetermined position.

More specifically, the serial data string via the input terminal 1 is directly sent to the determination circuit 20, and each pulse of the serial data string is delayed by 1 μs and delayed by 2 μs. 21 and is sent to the determination circuit 20. The output of the delay circuit 21 which delays by 1 μs is sent to each of the delay circuits 5, 6 and 7. In the determination circuit 20, for example, one position of a pulse before and after the pulse of interest is a position having a pulse interval of 1 μs with respect to the pulse of interest, and the other position is a position having a pulse interval of 1.5 μs or 2 μs. In this case, the output of the delay circuits 6 and 7 in which the pulse of interest is shifted to the interval side of 1 μs by a certain amount (peak-shift compensated) is selected by the selection switch 8.

That is, in the configuration shown in FIG. 2, the determination circuit 20 has, for example, the other position of 1.5 μs.
If it is at the pulse interval position of
Then, the output of the delay circuit 6 is selected, and if the other position is a position with a pulse interval of 2 μs, the output of the delay circuit 7 is selected by the selection switch 8. When the other position is also a position with a pulse interval of 1 μs, the output of the delay circuit 5 is selected by the selection switch 8. The delay circuits 5, 6 and 6 having the configuration of FIG.
The delay amount β in 7 corresponds to the delay amount in the determination circuit 20.

The selection process in the configuration of FIG. 2 will be described with reference to FIG. 3 showing a timing chart of each part of the configuration of FIG.

In FIG. 3, it is assumed that the serial data string WD supplied to the input terminal 1 is as shown in A of FIG. Note that FIG. 3 shows an inverted version of the serial data string WD. The output of the 1 μs delay circuit 21 is the serial data string WD as shown in FIG. 3B.
Becomes a data string (WD + 1 μs) delayed by 1 μs,
The output of the 2 μs delay circuit 22 becomes a data string (WD + 2 μs) obtained by delaying the serial data string WD by 2 μs, as shown in C of FIG. The output of the delay circuit 6 is 1 when the serial data string WD is 1 as shown in D of FIG.
μs and the data string delayed by the delay amount α (WD + 1 μs
+ Α), and the output of the delay circuit 7 becomes a data sequence (WD + 1 μs + α) obtained by delaying the serial data sequence WD by 1 μs and a delay amount 2α as shown in E of FIG.

That is, in FIG. 3, the determination circuit 20 having the configuration shown in FIG.
The output of the s delay circuit 21 (B in FIG. 3) has a pulse, the write serial data string WD (A in FIG. 3) directly supplied has a pulse, and the output of the 2 μs delay circuit 22 (C in FIG. 3). ), There is no pulse, the selection switch 8 is made to select the output of the delay circuit 7 (E in FIG. 3). Further, in the determination circuit 20 having the configuration shown in FIG. 2, the output of the 1 μs delay circuit 21 (B in FIG. 3) has a pulse, and the pulse is directly supplied to the write serial data string WD (A in FIG. 3). If there is a pulse in the output of the 2 μs delay circuit 22 (C in FIG. 3), the selection switch 8 is made to select the output of the delay circuit 5 (B in FIG. 3). Further, the determination circuit 2 having the configuration shown in FIG.
0 is the case other than the above, that is, the above 1 μs delay circuit 2
There is a pulse in the output of 1 (B in FIG. 3), there is no pulse in the write serial data string WD (A in FIG. 3) that is directly supplied, and there is a pulse in the output of the 2 μs delay circuit 22 (C in FIG. 3). Or if there is a pulse in the output of the 1 μs delay circuit 21 (B in FIG. 3) and there is a pulse in the write serial data string WD (A in FIG. 3) that is directly supplied,
If the output of the μs delay circuit 22 (C in FIG. 3) has a pulse, the selection switch 8 is made to select the output of the delay circuit 6 (D in FIG. 3).

Further, the write compensating circuit of each embodiment of the present invention as described above is incorporated in, for example, the floppy disk drive 10 of the floppy disk device as shown in FIG.

In FIG. 4, the host computer 1
00 and the head 111 are the same as those in FIG. 5 described above, and only the write serial data string WD is shown in the example of FIG. 4 to simplify the description. That is, the write serial data string WD from the host computer 100 is
It is sent to the control logic circuit 11 of the floppy disk drive 10. The control logic circuit 11 performs processing according to the specifications of the interface with the host computer 100. The output of the control logic circuit 11 is supplied to the write compensation circuit 12 of the above-described embodiment to which the present invention is applied. The serial data string subjected to the peak shift correction in the write compensation circuit 12 as described above is sent to the read / write circuit 13. The read / write circuit 13 generates a current according to the supplied serial data string, and this current becomes a drive current for writing to the head 111. In addition, the read / write circuit 13
Performs a process of converting a read current from the head 111 into a data string when reading the floppy disk.

By applying the write compensation circuit 12 of the present embodiment to the floppy disk drive 10 of such a floppy disk device, the floppy disk drive 10 seen from the floppy disk controller 100 is shown.
It is possible to compensate for the peak shift while ensuring the compatibility of the above and the compatibility of the medium (floppy disk) viewed from the floppy disk drive 10.

As described above, according to the present embodiment, it is possible to obtain the floppy disk drive in which the peak shift is compensated and the error is small. Further, it is not necessary for the host computer to judge whether or not the floppy disk drive to be used requires write compensation, and it is possible to use the floppy disk drive that performs the compensation and the floppy disk drive that does not perform the compensation in the same row. Furthermore, when manufacturing a floppy disk drive,
Since the presence / absence of compensation or the amount of compensation can be set according to the head to be used, it becomes possible to use a head having a wide range of resolution, and therefore the yield at the time of manufacturing the head is improved. Furthermore, since it becomes possible to perform compensation according to the writing resolution of the head, compatibility of the written medium is not lost.

[0041]

As described above, in the write compensating circuit of the present invention, the pulse interval between the pulse of interest in the serial data string and the pulses before and after it is determined, and attention is paid according to the result of this determination. Since each delayed pulse is selected by delaying the pulse by 0 to n times the predetermined time, it is possible to obtain a peak shift-corrected serial data string. Therefore, for example, in a floppy disk device (floppy disk drive). By applying it, it becomes possible to perform effective peak shift compensation for the serial data string recorded on the floppy disk.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of a write compensation circuit according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a schematic configuration of a write compensation circuit of another embodiment.

FIG. 3 is a timing chart of each part of a write compensation circuit according to another embodiment.

FIG. 4 is a diagram showing a floppy disk device in which the write compensation circuit of the present embodiment is incorporated in a floppy disk drive.

FIG. 5 is a diagram showing a schematic configuration of a conventional floppy disk device.

FIG. 6 is a waveform diagram for explaining a read serial data string having a peak shift with respect to a write serial data string.

FIG. 7 is a waveform diagram for explaining the principle of peak shift occurrence.

FIG. 8 is a waveform diagram for explaining the principle of occurrence of maximum peak shift.

FIG. 9 is a waveform diagram for explaining conventional peak shift compensation.

[Explanation of symbols]

 2 ... Pulse interval measurement circuit 3 ... Shift register 4 ... Comparison circuit 5, 6, 7, 21, 22 ... Delay circuit 8 ... Selection switch 10 ... ... Floppy disk drive 11 ... Control logic 12 ... Write compensation circuit 13 ... Read / write circuit 20 ... Judgment circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hideho Maeda 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (3)

[Claims] 1. A write compensation for compensating a difference between a serial data string written to the recording medium and the serial data string read from the recording medium, for a serial data string written to the recording medium. In the circuit, a pulse relationship determining means for determining a relationship between a pulse of interest in the serial data string and pulses before and after the pulse of interest, and the pulse of interest is delayed by 0 to n times a predetermined time. A write compensating circuit comprising: delay means for outputting each delay pulse; and selecting means for selecting each delay pulse output of the delay means according to the judgment result of the pulse relation judging means. .. 2. The pulse relationship determination means determines the magnitude relationship of the pulse intervals between the pulse of interest and the pulses before and after the pulse of interest in the serial data string. Write compensation circuit. 3. The write compensation according to claim 1, wherein the pulse relationship determination means determines whether or not the pulse before and after the pulse of interest in the serial data string is at a predetermined position. circuit.