JPH05227453A - Frequency automatic adjustment device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] AFC is realized by a digital circuit, and the circuit scale is reduced and stability and reliability are improved by making it an LSI. A means 22 for inputting an external synchronizing signal, a means 16 for generating an internal synchronizing signal, and a comparing means for sampling the external synchronizing signal at regular intervals to detect a synchronization difference with the internal synchronizing signal and measuring the degree thereof. Means 30 and 14 for gradually changing the synchronization of the internal synchronization signal based on the comparison result of 24;
When the cycles of both sync signals are the same, the cycle width of the internal sync signal is based on the comparison result of the means 28 for fixing the cycle of the internal sync signal and the comparison means 24 for detecting the phase difference between the sync signals and measuring the degree of the phase difference. When the phases of the synchronizing signals 30 and 14 for changing the sync signal and the synchronizing signals of both sync signals approach each other, and when the period and the phase match, the internal sync signal is continuously sampled while the external sync signal is continuously sampled. Means 30 and 14 for finely adjusting the cycle and phase of the synchronization signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency controller (AFC). In particular, the present invention relates to a frequency automatic adjustment device for a horizontal / vertical synchronizing signal which is a control signal for a display screen used in an image device such as a TV or VTR.

With the recent trend toward LSIs in electrical equipment, digitization of analog circuits is required. For this reason, it is necessary to digitize the automatic frequency adjustment circuit composed of analog circuits and integrate it in the LSI.

[0003]

2. Description of the Related Art Of the horizontal / vertical synchronizing signals for controlling a TV screen, a vertical synchronizing signal (hereinafter referred to as VSYNC #) generally produces a waveform in an integrated form, so that external noise is mixed. Even if it is removed by integration, the horizontal sync signal (hereinafter referred to as HSYNC #) is generated with a differentiated waveform, so it is vulnerable to noise and the like, and mixing of noise disturbs a part of the TV screen. Cause.

In order to suppress this disturbance, AFC is used as a means for balancing the synchronizing signals. The conventional AFC is shown in Fig. 2.
The phase detection unit 2 detects the phase difference between the synchronization signal (for example, a horizontal synchronization signal separated from the TV broadcast signal) SYNC # input from the outside and the synchronization signal SYNCX output from the oscillation circuit 1. And the detection result is integrated by the integrating unit 3 to convert the phase difference into a voltage.

The phase difference converted into a voltage is input to the oscillation circuit 1, and the oscillation characteristic of the oscillation circuit 1 is changed according to the level of the voltage to increase or decrease the oscillation frequency, thereby outputting the output synchronization signal SYNCX. Was controlling the frequency.

[0006]

In the above-mentioned conventional AFC, the differentiation / integration circuit 3 is constituted by a capacitor, a resistor and a coil.
And the oscillation circuit 1 and the phase detection circuit 2 are also configured by analog circuits such as transistors and crystal oscillators, and the frequency adjustment of oscillation is controlled by voltage difference or the like. ..

Therefore, the incorporation of AFC, which is an analog circuit, in an LSI in which a digital circuit is integrated cannot be realized in reality because of the guarantee of electrical characteristics and the difficulty in realizing the circuit.
The AFC is configured by an analog circuit separately from the LSI, which causes a problem that the circuit scale increases.

Therefore, an object of the present invention is to realize the AFC by a digital circuit and make it an LSI to reduce the circuit scale and improve the stability and reliability.

[0009]

The present invention comprises means (22) for inputting a synchronization signal (SYNC #) generated externally,
A means (1) for internally generating a synchronization signal (ISYNCX)
6) and a synchronization signal (SYNC #) input from the outside are sampled at regular intervals, and the external synchronization signal (SYNC #) is sampled.
#) And a means (24) for detecting a synchronization difference between the internal synchronization signal (ISYNCX), a comparing means (24) for measuring the degree of the period difference, and a comparison result by the period difference comparing means (24). Means (30, 14) for gradually changing the synchronization of the internal synchronization signal (ISYNCX) and the cycle of the internal synchronization signal (ISSYNCX) are the external synchronization signal (SYNC).
When it becomes the same as the cycle of C #, the internal synchronization signal (ISYN
CX) means for fixing the cycle and holding the cycle width (28)
And when the cycles of both sync signals (ISSYNCX, SYNC #) become the same, the internal sync signal (ISSYNCX)
Means (24) for detecting the phase difference between the external synchronization signal (SYNC #) and the external synchronization signal (SYNC #), a comparison means (24) for measuring the degree of the phase difference, and an internal means based on the comparison result by the phase difference comparison means (24). Means (30, 14) for changing the cycle width of the synchronization signal (ISSYNCX) and the internal synchronization signal (IS
When the phase of YSYNCX reaches near the phase of the external sync signal (SYNC #), the internal sync signal (ISSYNCX)
Means (30, 14) for gradually adjusting the phase of the internal synchronization signal (I) to the phase of the external synchronization signal (SYNC #).
When the cycle and the phase of the external synchronization signal (SYNC #) match with that of the external synchronization signal (SYNC #), the sampling of the external synchronization signal (SYNC #) is continued and the internal synchronization signal (ISSYNC)
Means (30, 14) for finely adjusting the cycle and phase of (X)
And are included.

FIG. 1 shows an automatic frequency adjusting device according to the principles of the present invention. The apparatus of FIG. 1 constitutes a circuit for performing frequency control on a horizontal synchronizing signal (hereinafter referred to as HSYNC #).

IHSYNCX is a horizontal synchronizing signal generated internally, and the IHSYNCX is a counter 10.
, A counter control unit 12 that controls the counter 10, a control decoder 14 that decodes the counter value, and a generation unit 16 that generates a signal from the decoder value.

The circuit 20 for adjusting the frequency and phase of the IHSYNCX is an H input from the outside via an input section 22.
A phase / cycle comparison control unit 24 that detects a phase difference and a cycle difference between the SYNC # and the internally generated IHSYNCX, and indicates whether the phase / cycle comparison control unit 24 compares the phase comparison or the cycle comparison. It comprises a switching unit 26, a latch unit 28 that holds the comparison result of the cycles, and a decoder control unit 30 that controls the decoder 14 from the held comparison result.

HSYNC, which is a balanced horizontal sync signal
The circuit 32 for generating the CX includes a phase / cycle comparison control unit 24.
HSYNC # and IHSYNCX based on the comparison result of
It is composed of the OUT control unit 34 for switching the signal of.

[0014]

Next, the operation of the automatic frequency adjusting device according to the principle of the present invention will be described with reference to FIGS. 3 (A), (B), (C) and (D).

First, when the signal of the external input HSYNC # is in a high state where it is not valid (hereinafter, negated), FIG.
As shown in (A), the internally generated synchronization signal IHSYNC
X is output as HSYNCX.

The frequency of HSYNCX at this time is determined by the control data of the decoder control unit 30 based on the comparison data of the period value latch unit 28 which is held in advance. Next, when HSYNC # becomes Low and becomes valid (hereinafter, asserted), HSYNC # and IHS are set as shown in FIG. 3B.
The comparison control unit 24 compares the period difference with YSYNC, and the frequency of IHSYNCX is varied according to the comparison result to determine HSY.
Bring it closer to the frequency of NC #.

At this time, instead of suddenly approaching the same frequency as HSYNC #, I within a certain upper and lower limit range is set.
The frequency of HSYNCX is changed so that the rate of change decreases as the frequency approaches.

The cycle is fixed when the cycles of HSYNC # and IHSYNCX become the same, and the cycle value latch unit 28
The period value is stored in. Next, the phases are adjusted, but if HSYNC # and IHSYNCX deviate from a certain phase, the period of IHSYNCX is given a certain length, and the period widths of HSYNC # and IHSYNCX are controlled to be different again. To do. (FIG. 3C) As a result, the phases of HSYNC # and IHSYNCX gradually approach each other, and when the phases are matched, the cycle width of IHSYNCX is returned to the same cycle as HSYNC # and phase matching is completed.

Even in phase matching, if the phases are synchronized within a constant phase matching range, the constant length given to IHSYNCX is reduced to gradually match the phases.

Once IHSYNCX and HSYNC # are synchronized, HSYNCX is continuously output while finely adjusting the phase / cycle synchronization with HSYNC # in fine units.
At this point, external noise may appear on HSYNC #,
Even if YNC # temporarily disappears, internal IHSYNCX
By outputting, the stable supply of HSYNCX is achieved. (Fig. 3
(D)) As described above, according to the frequency automatic adjustment device according to the principle of the present invention, the frequency (cycle) and phase of IHSYNCX can be adjusted separately. Even if HSYNC # suddenly changes or disappears temporarily, the internal I
Stable HSYNC that is always balanced by HSYNCX
X can be supplied.

Although the horizontal synchronizing signal has been taken up in the above description, the present invention can be applied to all those requiring the frequency adjustment of the vertical synchronizing signal and the like.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. This AFC is described as a controller for controlling the horizontal synchronizing signal HSYNC #, and its purpose is to correct the external input HSYNC # whose phase or frequency is disturbed by disturbance or the like and always output a stable synchronizing signal. Then, when the external HSYNC # is input, the IHSYNCX generated internally is automatically adjusted in frequency so as to be phase-synchronized with the external HSYNC # and output. Also, external HSYN
When C # stops, the internally generated IHSYNCX is output to supply a stable sync signal. More specifically, when the external HSYNC # is not input, the internally generated IHSYNCX is output.

When the external HSYNC # is input, the internal IHSYNCX is output in phase with the external HSYNC #. Even if the external HSYNC # stops, the internal IHSYNC
Output X and do not stop the supply of HSYNCX.

When the external and internal HSYNCs are synchronized, even if external noise or the like is placed on the external HSYNC #, the external HSYNC # s are masked within an allowable range. Next, FIG. 4 shows an automatic frequency adjusting device according to an embodiment of the present invention.

In FIG. 4, the counter 50 has 8 bits.
Is the counter. The counter control unit 52 uses the counter 5
Controls clearing of 0.

The decoder 54 decodes the count value of the counter 50 and outputs it. The pulse control unit 56 controls the decode value of the decoder 54 and outputs a control pulse.

The state control unit 58 controls the operation transition.
The HSYNC # input section 60 is an HSYNC input from the outside.
This is the input section of NC #. The HSYNC # controller 62
The externally input HSYNC # is controlled.

The phase control section 64 generates data for phase comparison. The phase comparator 66 uses the externally input HSYN
The C # is compared with the phase comparison data.

The operation control unit 68 processes the phase-compared data and controls the next operation. Data register 70
Is a data storage register for operation control. The phase lock controller 72 controls phase synchronization with the external HSYNC #.

The HSYNC generator 74 controls the output of HSYNCX. Next, an outline of operation will be described. As a clock serving as a reference for operation, 4fsc, which is a pulse having a frequency four times that of the color burst signal, is used as a clock.

The main operation is classified into three types: external input HSYNC # (hereinafter HSYNC #) sample operation, external input HSYNC # and internally generated IHSYNCX phase comparison operation, internally generated IHSYNCX (hereinafter IHSYNCX) phase / frequency control operation. I can.

Each operation is performed during the period shown in FIG.
To be more specific, the sample operation is always performed and H input from the outside
SYNC # is sampled as data for phase comparison.
HSYNC # samples are from Low level to High
This is done by detecting the rising edge to the level.

In the phase comparison, the sampled data is compared with the phase difference of the internal operation and the IHSYNC CYCLE width (frequency) to generate the phase difference data and the 1H width data.

In the phase control, the internal operation is controlled by the generated phase difference data and the IHSYNC CYCLE width data, and the internally generated ISYNC is supplied to the external input HSYNC #.
Bring the HSYNCX phase closer.

(1) Sample operation of externally input HSYNC # The sample of HSYNC # is classified into the following three types. HSYNC # and IHSYNCX are considered not to be synchronized at all ISYNCH of ISYNC # and IHSYNCX
YCLE width (hereinafter 1H width) synchronization period HSYNC # and IHSYNCX phase synchronization period Each sample period is as shown in FIG. More specifically, when HSYNC # is sampled during an asynchronous period in which HSYNC # and IHSYNCX are considered not to be synchronized at all, the 1H width data of IHSYNCX is sampled as the maximum (or minimum) value, and HSYNC # is 1H. Iterate until sampled within the width synchronization period.

When HSYNC # is sampled within the 1H width synchronization period, certain data defined within the period is sampled as 1H width data of IHSYNCX. As a result, the IH width of IHSYNCX is changed so that the 1H width of HSYNC # and IHSYNCX is ± (4 × 1 /
They are made identical within the error range of fsc) sec.

1H of HSYNC # and IHSYNCX
When the widths are equalized within an error range of ± (4 × 1 / fsc) sec, the 1H width of IHSYNCX is again increased (or decreased) by a certain amount, and HSYNC # is increased within the phase synchronization period.
Adjust to sample. HS during the phase synchronization period
When YNC # is sampled, the 1H width of IHSYNCX is made to be the same as HSYNC # again, and IHSYNCX is determined by a constant data sample defined within the phase synchronization period.
And the HSYNC # phase difference is corrected every raster in units of 1 / fsc sec and synchronization is performed.

(2) Generation of 1H-width synchronization data 1H-width synchronization data is generated according to the sampling position of the externally input HSYNC #.

The division of the sampled synchronization data is divided into two types. (See FIG. 7 (A)) H during the asynchronous period
When SYNC # is sampled, uniform synchronization data is generated, and positive or negative is determined depending on the level of ± DATA at the time of sampling.

During the synchronization adjustment period, synchronization data is generated depending on the sample position of HSYNC #. The synchronization data is assigned as PHASE DATA as follows, and the same PHASE DATA is applied to two rasters.
Is sampled, it is considered that the 1H widths of HSYNC # and IHSYNCX are synchronized.

When the 1H width is synchronized, the HSYNC #
And IHSYNCX are out of sync and the sampled data is fixed. PHASE DATA also comes with ± data. (See FIGS. 7B and 7C.) (3) Generation of phase synchronization data When the 1H widths of HSYNC # and IHSYNCX are synchronized,
Add or subtract a certain amount of value to PHASE DATA, and
The sample position of NC # is PHASE D during the synchronization adjustment period.
Repeat until ATA 0 period is reached.

PHASE DATA 0 period and HSYN
When C # is sampled, it becomes the phase LOCK period and LO
CK DATA is sampled. LOCK DATA
Is sampled as long as every raster HSYNC # is input. (See FIG. 8) (4) Phase control operation Increase or decrease the 1H width of IHSYNCX to change the HS of external input.
Synchronize with YNC #.

The operation can be classified into two types, that is, the 1H width adjusting operation and the phase adjusting operation. (See FIG. 9 (A)) 1H width adjustment is 5 × according to PHASE DATA.
The length of 1H is adjusted in the range of 0 to 16 in units of fsc, and when the adjustment value is 8, it becomes the standard, when 8 or less is the minus side and when 8 or more is the plus side, the length of IHSYNCX is adjusted.

PHASE DATA is from 0 to F,
This corresponds as shown in FIG. L for phase adjustment
In accordance with OCK DATA, the length is adjusted in the range of 0 to 10 in fsc unit, and the adjustment value of 5 becomes the standard value, and the length of IHSYNCX is adjusted with reference to 5.

Further, when PHASE DATA is a value indicating an asynchronous period and PHASE DATA after 1H width synchronization
During operation when sampling HSYNC # in 0 period,
The maximum value (10) becomes the minimum value (0).

LOCK DATA corresponds as shown in FIG. 9 (C). (5) Rising level synchronization of HSYNC # and HSYNCX When HSYNC # and IHSYNCX are synchronized in phase, H
The pulse rising timing of SYNCX is switched from internally generated IHSYNCX to externally input HSYNC # direct output.

As a result, HSYNC # and HSYNCX
Will be fully synchronized. (Fig. 10 (A)
Refer to IHSYNCX for the direct output range of HSYNC #.
Before and after the rise is about 4 x fsc range, about 1μs before and after
It has a range of ec. (See FIG. 10B.) (6) Switching between HSYNC # direct output and IHSYNCX output The phases of HSYNC # and IHSYNCX are synchronized, and H
When operating in a state where the rising edge of SYNC # is directly output to IHSYNCX, HS is provided before the rising point of IHSYNCX in preparation for the oscillation stop of HSYNC #.
YNC # is sampled, and if HSYNC # is low level, it is switched to the direct output of HSYNC #, and if it is high level, it is switched to the internally generated IHSYNCX rising output. (See FIGS. 11A and 11B) When the external input HSYNC # is stopped at the Low level,
HSYNC # Forcibly I at the final position of the direct output range
Launch HSYNCX. (See FIG. 11C.) (7) Falling Position of HSYNCX The falling position of HSYNCX is generated inside the AFC.

The assertion period of HSYNCX is (17 × f
sc) sec and always assert at a fixed position. (See FIG. 12 (A)) As a result, the rising edge of HSYNCX is set to HSYNC #.
The HSYNCX pulse width when switching to the direct output is in the range of 13 fsc to 22 fsc. (Fig. 12
(Refer to (B)) Next, the operation according to the situation will be described.

First, the operation when the externally input HSYNC # is stopped will be described. When the internal IHSYNCX is being generated while the external input HSYNC # is stopped, the IHSYNC # is sampled while the IHSYNC # is sampled.
CX is being generated.

The 1H width of the internally generated IHSYNCX is 227.5 × fsc in the initial state, and the operation is repeated. If the HSYNC # oscillation has just stopped halfway, H
The operation is performed with a 1H width at the time of SYNC # oscillation.

When the oscillation of HSYNC # is started, HSYNC # for three rasters is counted to remove noise, and then,
The phase synchronization operation of HSYNC # and IHSYNCX is started.
(Refer to FIG. 13) (1) External input HSYNC # and internally generated IHSYNCX
When the externally input HSYNC # and the internally generated IHSYNCX are in phase synchronization, HSYNC
The horizontal synchronization signal HSYNCX is output while finely adjusting the 1H width of IHSYNCX by the sample of C #.

At this time, the rising edge of HSYNCX is HS.
By directly outputting YNC #, HSYNC # and H
Synchronize the SYNCX phases. (Refer to FIG. 14) (2) External input HSYNC # and internally generated IHSYNCX
The operation when HSYNC # starts oscillating from the stopped state and the phase of IHSYNCX is synchronized will be described.

When HSYNC # is sampled in the asynchronous period, the 1H width of IHSYNCX is set to the maximum width or the minimum width by ± DATA, and the operation is repeated. The sample of HSYNC # is HSYNC # for noise removal of HSYNC #.
Start 3 rasters after oscillation. (See FIG. 15 (A)) When HSYNC # is sampled in the synchronization adjustment period, 1H of IHSYNCX is obtained according to the value determined within the synchronization adjustment period.
The width changes for each raster.

2 PHASE DATA sampled
If the data is the same across rasters, that data is used as 1H-width synchronous data (PHASE SAMPLE DATA: PSAMP DT). (Refer to FIG. 15B.) After the 1H width synchronization is completed, the sample position of HSYNC # is P
If it falls within the HASE DATA 0 period, LOCK D
Phase adjustment is performed by raster sampling each ATA. (Fig. 1
5 (C)) (3) Operation when HSYNC # of external input is stopped When oscillation of HSYNC # is stopped, PH before oscillation is stopped
ASE SAMPLE DATA and LOCK SAMPL
IHSYNCX generated with the value of EDATA is set to HSY
Output as NCX. (See FIG. 16 (A)) The determination to stop the oscillation of HSYNC # is made 5 fsc before the rise of IHSYNCX.

At this time, if HSYNC # is not at the Low level, it is considered that there is a synchronism deviation, and the internally generated IHSYNCX is switched on. (See FIG. 16B.) (4) The 1H width of the external input HSYNC # is (227.5).
Synchronous operation when longer than × fsc) sec 1H width of HSYNC # is a standard value (227.5 × fsc)
If the length exceeds 4 x fsc, PHASE DA
The value of TA is set longer than the standard value.

If the same PHASE DATA is sampled over two rasters within the synchronization period of 1H width, the PHA
SE DATA to PHASE SAMPLE DATA
Set as. (Refer to FIG. 17 (A)) When PHASE SAMPLE DATA is set, L
OCK DATA is set to the maximum value, and the 1H width is increased by (5 × fsc) sec from HASNC #.

HSYNC # is PHASE DATA 0
It operates in this state until it is possible to sample within the phase LOCK period which is the period. (Refer to FIG. 17B.) When HSYNC # is sampled within the phase LOCK period, LOCK SAMPLE DATA sets the original phase control data for each raster. (See FIG. 17C.) (5) The 1H width of the external input HSYNC # is (227.5).
Synchronous operation when shorter than × fsc) sec 1H width of HSYNC # is a standard value (227.5 × fsc)
When 4 × fsc or more, the value of PHASE DATA is set shorter than the standard value.

If the same PHASE DATA is sampled over two rasters within the synchronization period of 1H width, the PHA
SE DATA to PHASE SAMPLE DATA
Set as. (See FIG. 18A.) When PHASE SAMPLE DATA is set,
LOCK DATA is set to the minimum value, and the 1H width is reduced by (5 × fsc) sec from HSYNC #.

HSYNC # is PHASE DATA 0
It operates in this state until it is possible to sample within the phase LOCK period which is the period. (See FIG. 18B.) When HSYNC # is sampled within the phase LOCK period, LOCK SAMPLE DATA sets the original phase control data for each raster. (See FIG. 18 (C)) (6) Operation when HSYNC # of external input is out of synchronization HSYNC # in the middle of operation in the phase synchronized state
If the phase shift occurs, the phase correction operation starts after one raster. (See FIG. 19 (A)) When entering the phase correction operation, LOCK SAMPLE DA
TA (L SAMPDT) is set to a value of -0, and PHA
SE SAMPLE DATA is set to a sample value of HSYNC #.

After that, the normal synchronization operation is performed, and the 1H width synchronization and the phase synchronization are performed. (See FIG. 19B.) (17) Operation when external input HSYNC # is stopped by one raster When external input HSYNC # is stopped by one raster and oscillation is started again, one raster whose oscillation is stopped H only for a while
Switch the output of SYNCX to the internally generated IHSYNCX,
After the oscillation starts, it operates in synchronization with HSYNC #.

During the stop period of one raster, the 1H width synchronization and the phase synchronization are not released. If the oscillation stop exceeds 1 raster, it is considered that the external input HSYNC # has stopped, and 1
It starts from the H-width synchronous operation. (Refer to FIG. 20) (8) Operation when noise is applied to HSYNC # during synchronous operation HSYNC # and HSYNCX during synchronous operation HSYNC
If pulse noise appears in #, it is considered invalid because it is masked.

The mask period is outside the phase LOCK period, and even if HSYNC # is asserted during that period, it becomes invalid. (See FIG. 21) (9) Operation when 1H width of HSYNC # fluctuates after 1H synchronization When 1H width of HSYNC # fluctuates after 1H width synchronization, phase synchronization may not be performed. Therefore, even after 16 rasters after 1H width synchronization, HSYNC is performed during the phase LOCK period.
If # is not sampled, 1H wide synchronization is performed again.
(See FIG. 22) Next, the frequency automatic adjustment device of the present invention will be described more specifically.

On the display screen of the background TV or TV-integrated VTR, a super screen
Characters / graphics such as channel and date are displayed on screen by imposing.

The characters / graphics displayed on the screen are OSDC (On S) which is a dedicated LSI.
It is generally controlled by creen Display Controller).

However, in a TV, VTR, etc., when the received electric wave is weak (weak electric field) or when there is no signal, during special reproduction in the VTR (fast forward, rewind, reproduction of non-recording portion, etc.), tape extension, etc. Under the above condition, a normal video signal may not be supplied to the OSDC, and the characters / graphics displayed on the screen may fluctuate up and down or may fluctuate left and right.

Therefore, AFC is used for the purpose of correcting the video signal and always supplying a stable display screen. AFC
Is the Automatic Frequency Controll
er) is an abbreviation for er) and is mainly used for correction of the horizontal synchronizing signal included in the video signal.

In the conventional AFC, the period / phase of the horizontal synchronizing signal is linearly adjusted by the potential difference or the like, and is composed of an analog circuit. Therefore, it is not suitable for incorporation into OSDC or the like manufactured with a CMOS structure. Therefore, the display system LSI, OSDC (On Scr
een Display Controller)
A fully digital AFC circuit was prototyped.

When the AFC function is incorporated, there are advantages such as a low system price, a reduction in the number of parts / simplification of the circuit, and an improvement in reliability. TV images Currently, the video signal systems of TVs used in various countries around the world can be roughly divided into three types, NTSC, PAL, and SECAM.

TV images used in Japan are NTS
It is broadcast in a method based on the C (National Television System Committee) standard (an outline of the NTSC standard is shown in FIG. 23).

According to the NTSC standard, the vertical direction of the display screen is 52.
It is composed of five scanning lines, and one scanning line (referred to as one tester) is composed of a mixed signal (composite video signal: composite signal) of a luminance signal, a color signal, a color burst signal, and a synchronization signal.

Necessity of AFC In FIG. 23, the brightness signal L controls the brightness of the screen according to the signal level.

The color burst B and the color signal C are signals for controlling the display color, and the color signal C is transmitted on a carrier having the same frequency as the color burst signal B called a color subcarrier (fs). (The phase is different.) Then, the hue of the color burst signal B and the color signal C is displayed on the screen, and the amplitude intensity of the color signal C determines the density of the display color.

The horizontal synchronizing signal is HSYNC (Horizontal S
It is called "synchronization" and controls the display position in the horizontal direction of the screen. When these signals are received by the receiver (TV), they are separated into a luminance signal L, a color signal C, and a synchronization signal HSYNC, and an image is reproduced on the display screen.

At this time, since the horizontal synchronizing signal HSYNC is generally generated separately by the differentiating circuit, it is easily affected by a disturbance such as noise, and when it is affected, the screen is wavy. A phenomenon or a phenomenon that an image locally flows laterally occurs. (See FIG. 24) AFC is used to remove these phenomena.

AFC Principle 1 The horizontal sync signal HSYNC consisting of 525 screens is affected by phase shift and noise to some extent, but if the horizontal sync signals HSYNC of each raster are averaged, the , The local phase disturbance is averaged and removed. By controlling the display screen using this averaged horizontal synchronizing signal HSYNC, it is possible to obtain a stable image.

FIG. 25 shows the principle configuration. HS in FIG. 25
YNC # is a horizontal synchronizing signal separated and generated from the composite signal Signal by the HSYNC separating unit 80.

The HSYNC signal is a pulse wave generated by the oscillation circuit 82 and is used for screen control of the display device CRT. The oscillation frequency of the HSYNC signal is adjusted so as to generate a pulse compliant with the standard of the horizontal synchronizing signal.

The phase detection circuit 84 receives the HSYNC # signal and H
The phase difference with the SYNC signal is detected, and a signal matching the level of the phase difference is output. The detected phase difference signal is smoothed by the integration circuit 86 and becomes a frequency control signal of the oscillation circuit 82.

The oscillator circuit 82 is one which can control the high and low of the frequency by the oscillation control signal, and uses HSYNC # and HS.
Frequency adjustment is performed until the YNC phase difference disappears.
In this way, the feedback is repeated and the horizontal synchronization signal HS
Since YNC is averaged, even if the cycle / phase of HSYNC # changes sharply, the horizontal sync signal corrected by AFC is gradually adjusted, and the cycle / phase relationship of the adjacent raster changes rapidly. There is nothing.

Configuration of AFC As the AFC, there are a method of controlling a vertical synchronizing signal and a method of controlling a horizontal synchronizing signal. This time, an AFC for controlling a horizontal synchronizing signal as described below was prototyped.

No horizontal sync signal HSYNC # → When the horizontal sync signal generated by the AFC circuit is reached, the signal HSYNCX is output. When the horizontal synchronization signal HSYNC # is supplied → When the horizontal synchronization signal generated by the AFC circuit is being supplied The signal HSNCX is synchronized in phase and cycle with the external horizontal synchronization signal HSYNC #.

When the horizontal synchronizing signal HSYNC # is middle → When the horizontal synchronizing signal generated by the AFC circuit is interrupted, the signal HSYNCX is output. Measures against noise → Mask the input for a specified period to remove noise.

Horizontal sync signal HSYNC # → NTSC standard sync signal ± 10 μ Follow-up range Within sec. FIG. 26 shows the entire block of AFC.

In FIG. 26, HSYNC # is a horizontal synchronizing signal from the outside. HSYNC: Horizontal sync signal after frequency adjustment.

HSYNCX: A horizontal synchronization signal generated by the AFC circuit. fsc: An operation reference clock of this circuit, which has a frequency equivalent to that of the color burst signal (about 3.58 MHz).

The horizontal sync signal generator 90 generates the color subcarrier f
s clock fsc is input and the horizontal synchronization signal HSYNC is input.
A block that generates X, and includes a counter 90, a counter control unit 92, a counter control decoder 94, a decoder control unit 96, and an HSYNCX generation unit 98. Here, the counter 90 is an 8-bit counter, the counter control unit 92 controls clearing of the counter 90, the counter control decoder 94 decodes and outputs the count value of the counter 90, and the decoder control unit 96. Controls the decode value of the counter control decoder 94 and outputs a control pulse, and the HSYNCX generating unit 98 generates and outputs HSYNCX.

The cycle / phase detector 100 is a block for comparing the horizontal sync signal HSYNC # from the outside with the horizontal sync signal HSYNCX generated internally. The phase / cycle comparison controller 102 and the phase / cycle switching control. The unit 104, the period value holding register 106, and the phase value holding register 108 are included. Here, the phase / cycle comparison control unit 102 compares the phase / cycle of the horizontal synchronization signal HSYNC # from the outside with the internally generated horizontal synchronization signal HSYNCX, and the phase / cycle switching control unit 104 uses the comparison control unit. 102 switches between phase comparison and period comparison, and the cycle value holding register 106 and the phase value holding register 108
The period value and the phase value are held respectively.

The HSYNC # input control section 110 is
HSYNC # is input and the HSYNC output control unit 112
Outputs HSYNC. Further, fsc is supplied to each block of AFC.

Horizontal Sync Signal Generator 90 The horizontal sync signal generator 90 receives the clock (fsc) of the color subcarrier (fs) and inputs the horizontal sync signal (HSYNC).
X) is generated.

Since the relation between fsc and HSYNCX is fsc = HSYNCX / (2 × 455) (Hz), HSYNCX = fsc / 227.5 (Hz).

As can be seen from the above equation, fsc (about 3.5
8MHz) to obtain the HSYNCX signal from the clock, fsc can be counted 227.5 times.
All you have to do is prepare a counter.

FIG. 27 shows the horizontal synchronizing signal generator, and FIGS. 27A and 27B show the circuit configuration and the waveform, respectively. In the functional specifications, if the period variation of the horizontal synchronizing signal is set to ± 10 μsec of the NTSC standard signal, NTSC standard 227.5 + 10 μsec · fs
Since c = 264, a 9-bit counter capable of counting fsc by 264 is required, but in the trial production this time, it could be realized by a 7-bit counter due to the entanglement with the decoder and the phase detection circuit.

Cycle / Phase Detecting Unit 100 As for the cycle / phase detecting unit 100, there are two schemes: a method using an arithmetic unit having a built-in ALU and a method using a counter & decoder & comparator.

In the method using the arithmetic unit, the period can be followed progressively, and the phase synchronization is fast. In the method using the comparator, the circuit is relatively small in scale and the test circuit can be easily incorporated.

This time, this AFC circuit will be OSDC in the future.
Considering that it is built in, we decided to use a method that uses a comparator, which is advantageous in terms of circuit scale and testing. In the control by the comparator, first, one cycle of HSYNC is set as shown in FIG.
It is divided into a period adjustment period and a phase adjustment period, and each control is performed.

Description of Operation in Each Period The operation of each period will be described below. Phase difference detection period In the phase difference detection period, the cycle adjustment value and the phase adjustment value are shown in FIG.
They are assigned as shown in (A) and (B), and HSYN
Each data is read by using C # as a trigger.

The read period adjustment value and phase adjustment value are used for controlling the decoder in the period / phase adjustment period described later. No-work period During the no-work period, the specified value of 93.5 is counted.

Cycle adjustment period The horizontal synchronizing signal of NTSC standard is 15.75 KHz and 2
27.5 / fsc μsec.

In the period adjustment period, it is possible to adjust the period variation of the reference horizontal synchronizing signal up to ± 10 μsec. It has a counter of 0 to 80 for the period adjustment, and the period can be adjusted in units of 5 / fsc μsec.

Therefore, the period which can follow the horizontal synchronizing signal HSYNC is 187.5 to 267.5 / fsc μse.
It becomes the range of c. Phase adjustment period Even when the cycle and the phase are synchronized, the phase slightly shifts for each raster. Since this deviation is accumulated, adjustment is required for each raster. This adjustment is performed during the phase adjustment period.

For the phase adjustment, it has a counter of 0 to 10 and can be adjusted in the unit of 1 / fsc. FIG. 30 shows the above operations.

The timing realization circuit has a structure as shown in FIG. Note that it is necessary to count 9 bits to generate the horizontal synchronization signal, but a counter capable of counting up to 93.5 is sufficient by controlling the entire period by dividing it into four periods (see FIG. 30). Therefore, it can be realized with a 7-bit counter instead of 9 bits.

Description of AFC Operation FIG. 32 shows a transition diagram of the AFC operation state. (A) Initial operation As the initial operation, the decode value of the counter is controlled by the initial values of the “cycle adjustment value register” and the “phase adjustment value register”, HSYNCX is generated, and HSYNCX is output as HSYNC. HSYNC at this time is
The signal complies with the NTSC standard. (Fig. 33
(B) Period adjustment of HSYNC # and HSYNCX When HSYNC # is input, the period adjustment operation is started, and H
The period difference between SYNC # and HSYNCX is adjusted to be within the range of ± 5 / fsc.

As an adjusting method, the period adjustment value at the rising time of HSYNC # is read, and it is determined whether the period adjustment is necessary or not by the difference from the period adjustment value at the rising time of the next HSYNC #.

When the same cycle adjustment value is read by two readings, it is judged that the cycles are synchronized. Fig. 34
(A) shows the timing when adjusting the cycles of HSYNCX and HSYNC #.

When the period adjustment of HSYNCX is completed, the phases of HSYNC # and HSYNCX are next adjusted.
First, move the phase of HSYNCX in units of 5 / fsc,
HSYNC until the phase of the HSYNC # and HSYNCX signals (the rising edge of the signal) falls within the range of ± 4 / fsc.
Move the NCX. (See FIG. 34B) Next, the phase difference between HSYNC # and HSYNCX is ± 4 /
When it falls within fsc, the phase adjustment value at the time of rising of HSYNC # is read, and the HS is adjusted in units of 1 / fsc for each raster.
Increase or decrease the pulse width of YNCX to change HSYNC # and HSYNC.
The operation of synchronizing the phase with CX is repeated.

When the phases of HSYNC # and HSYNCX are synchronized within ± 4 / fsc, the rising edge of the HSYNC signal is switched to output the rising edge of HSYNC #. (See FIG. 34 (C)) (c) Noise removal When HSYNC # and HSYNCX are operating in phase synchronization, the input circuit of HSYNC # is masked to prevent disturbance of HSYNC # due to external noise NOISE. ..

4 before and after the rising edge of HSYNCX
The mask setting period is other than / fsc. (Refer to FIG. 35) (d) Stopping HSYNC # Even if HSYNC # stops, the cycle before stopping
Generate HSYNCX in phase and continue to supply HSYNC.

Whether or not HSYNC # is present is determined by HS.
HSYNC 5 / fsc before the rising edge of YNCX
C # is sampled, and if HSYNC # is Low, the rising edge of HSYNC is synchronized with HSYNC #.

If it is High, the rising edge of HSYNC is synchronized with HSYNCX.

[0111]

As described above, according to the present invention,
Since the automatic frequency adjustment device (AFC) is composed of a digital circuit, the AFC can be easily integrated in an integrated circuit such as a peripheral LSI, the circuit scale can be reduced, and the circuit stability, reliability, and It greatly contributes to performance improvement.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an automatic frequency adjustment device according to the principles of the present invention.

FIG. 2 is a block circuit diagram of a conventional frequency automatic adjustment device.

FIG. 3 is an operation explanatory view of the frequency automatic adjustment device according to the principle of the present invention.

FIG. 4 is a block circuit diagram of an automatic frequency adjustment device according to an embodiment of the present invention.

FIG. 5 is an explanatory diagram of a period during which each operation is performed.

FIG. 6 is an explanatory diagram of a sampling operation of an external input HSYNC #.

FIG. 7 is an explanatory diagram of generation of 1H width synchronization data.

FIG. 8 is an explanatory diagram of generation of phase synchronization data.

FIG. 9 is an explanatory diagram of a phase control operation.

FIG. 10 is an explanatory diagram of rising level synchronization of HSYNC # and HSYNCX.

FIG. 11: HSYNC # direct output and IHSYNC
It is explanatory drawing of switching of X output.

FIG. 12 is an explanatory diagram of a falling position of HSYNCX.

FIG. 13 is an operation explanatory diagram when the externally input HSYNC # is stopped.

FIG. 14 shows an external input HSYNC # and an internally generated IHSYNC.
It is an operation explanatory view in the state where CX synchronized.

FIG. 15: Internally generated IHSYNC to external input HSYNC #
It is operation | movement explanatory drawing at the time of synchronizing CX.

FIG. 16 is an operation explanatory diagram when the externally input HSYNC # is stopped.

FIG. 17 shows that the 1H width of the external input HSYNC # is (22
It is explanatory drawing of a synchronous operation when it is longer than 7.5 * fsc) sec.

FIG. 18 shows the 1H width of the external input HSYNC # is (22
It is explanatory drawing of a synchronous operation when it is shorter than 7.5 * fsc) sec.

FIG. 19 is an operation explanatory diagram when the synchronization of the external input HSYNC # is lost.

FIG. 20 is an operation explanatory diagram when the externally input HSYNC # is stopped by one raster.

FIG. 21 is an explanatory diagram of an operation when noise is added to HSYNC # during the synchronous operation.

FIG. 22 is an explanatory diagram of an operation when the 1H width of HSYNC # changes after 1H synchronization.

FIG. 23 is a schematic diagram of the NTSC standard.

FIG. 24 is an explanatory diagram of an image affected by noise.

FIG. 25 is a principle configuration diagram of AFC.

FIG. 26 is an overall block circuit diagram of AFC.

FIG. 27 is an explanatory diagram of a horizontal synchronization signal generator.

FIG. 28 is an explanatory diagram of division of HSYNC for one cycle.

FIG. 29 is an explanatory diagram of operations during a phase difference detection period.

FIG. 30 is an explanatory diagram of operations in each period.

FIG. 31 is an explanatory diagram of a timing realization circuit.

FIG. 32 is a transition diagram of AFC operation states.

FIG. 33 is a waveform diagram of an initial operation.

FIG. 34 is an explanatory diagram of cycle adjustment of HSYNC # and HSYNCX.

FIG. 35 is an explanatory diagram of an operation when removing noise.

FIG. 36 is an explanatory diagram of an operation when HSYNC # is stopped.

[Explanation of symbols]

 HSYNC # ... Horizontal sync signal from the outside HSYNCX ... Horizontal sync signal after frequency adjustment IHSYNCX ... Horizontal sync signal generated by AFC circuit 16 ... IHSYNCX generator 24 ... Phase / cycle comparison controller 22 ... HSYNC # input unit 34 ... HSYNCXOUT controller

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/06 Z 9070-5C

Claims (3)

[Claims] 1. A synchronization signal (SYNC #) generated externally.
Means for inputting a sync signal (22), and means for internally generating a sync signal (ISSYNCX) (1)
6), and means (24) for sampling a synchronization signal (SYNC #) input from the outside at a constant interval and detecting a synchronization difference between the external synchronization signal (SYNC #) and the internal synchronization signal (ISSYNCX). Comparing means (24) for measuring the degree of the period difference, means (30, 14) for gradually changing the synchronization of the internal synchronization signal (ISSYNCX) based on the comparison result by the period difference comparing means (24), When the cycle of the internal sync signal (ISYNCX) becomes the same as the cycle of the external sync signal (SYNC #), a means (28) for fixing the cycle of the internal sync signal (ISSYNCX) and holding the cycle width; A means (24) for detecting a phase difference between the internal synchronization signal (ISYNCX) and the external synchronization signal (SYNC #) when the periods of the signals (ISYNCX, SYNC #) become the same. A comparison means (24) for measuring the degree of the phase difference, a means (30, 14) for changing the cycle width of the internal synchronization signal (ISSYNCX) based on the comparison result by the phase difference comparison means (24), When the phase of the internal sync signal (ISYNCX) reaches near the phase of the external sync signal (SYNC #), the phase of the internal sync signal (ISSYNCX) is changed to the external sync signal (SYNC).
Means (30, 14) for gradually adjusting to the phase of C #)
When the cycle and phase of the internal sync signal (ISSYNCX) and the external sync signal (SYNC #) match, the cycle and phase of the internal sync signal (ISSYNCX) are maintained while sampling of the external sync signal (SYNC #) continues. And a means (30, 14) for finely adjusting. 2. The apparatus according to claim 1, wherein the external synchronization signal (SYNC #) or the internal synchronization signal (I
SYNCX) is selected and output as an output synchronizing signal (SYNCX), including means (34) for outputting the external synchronizing signal (SYNC #).
And one of the synchronization signals (SYNC #, ISYNC) is selected based on the degree of the cycle difference and the degree of the phase difference of the internal synchronization signal (ISSYNCX).
When the synchronization and phase of (X) are the same, an external synchronization signal (SYNC #) is output as an output synchronization signal (SYNCX). 3. The apparatus according to claim 2, wherein the output means (34) outputs the external synchronization signal (SYNC #) as an output synchronization signal (SYNCX) while the external synchronization signal (SYNC #) is being output. And internal sync signal (ISSYNCX)
When there is a change in the cycle or the phase with the output sync signal (SYNCX), the internal sync signal (ISSYNCX)
The automatic frequency adjustment device is characterized by outputting as.