JPH05225777A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a leak current having capacity required to monitor refresh- timing with a memory cell MC for monitoring of comparatively few numbers, in a semiconductor memory device which sets refresh-timing of a memory cell for storing information by a refresh control circuit incorporated. CONSTITUTION:This device is provided with a memory cell for storing information (not illustrated) and a memory cell MC for monitoring in the same semiconductor substrate 1, also provided with a detector AMP which detects potential variation by a leak current of a capacitor C composing the memory cell MC for monitoring. The memory cell MC for monitoring is provided in a region 10 in the semiconductor substrate 1 where impurity concentration is higher than that in a region in which the above mentioned memory cell for storing information is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a memory cell comprising a capacitor for holding information as accumulated charge and a transistor for controlling the transfer of the charge and having a built-in refresh circuit. Dynamic random access memory (pseudo SRAM).

[0002]

2. Description of the Related Art Generally, a dynamic random access memory (pseudo SRA) having a built-in refresh circuit is used.
The refresh timing of M) is determined at a fixed time interval at the design stage based on the leakage current of the memory cell evaluated in advance. That is, the temperature dependence of the leakage current after the completion of the chip and the fluctuation of the manufacturing process.
It is set in consideration of (the worst condition). For this reason, the time interval is set to be extremely shorter than the actually required refresh interval, and as a result, there is a problem that the standby current cannot be reduced.

Therefore, recently, a method has been proposed in which refresh timing is given according to the actual value of the leak current for each chip (IEEE (Institute of Electrical and Electronics Engineers) ISSC).
C (International Solid State Circuit Conference) 1991, p268). In this method, as shown in FIG. 3, 1024 of the memory cells MC (including the capacitor C) in one chip (semiconductor substrate 1) are connected in parallel for monitoring, and each memory cell MC for monitoring is connected.
And the potential at the connection point between the precharge transistor TRPC and the precharge transistor TRPC is input to the differential amplifier AMP. Then, the differential amplifier AMP detects the difference from the reference potential Vref, that is, the potential fluctuation of the storage electrode SE due to the leak current, and the refresh control circuit 100 determines the refresh timing. As a result, the refresh control circuit 1 responds to variations in the leak current due to process variations.
00, the refresh timing can be determined for each chip, and the refresh timing can be determined according to the temperature environment during use.

[0004]

By the way, in the system shown in FIG. 3, the reason for connecting 1024 memory cells MC for monitoring in parallel is to some extent in accordance with the sensitivity of the differential amplifier AMP. This is because the leak current must be obtained. Therefore, in the above method,
There is a problem that the area occupied by the monitor memory cell MC in the chip is large.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device capable of obtaining a leak current of a magnitude necessary for monitoring with a relatively small number of monitor memory cells.

[0006]

In order to achieve the above object, a semiconductor memory device of the present invention has an information storage memory cell and a monitor memory cell each comprising a capacitor for holding electric charge and a transistor for controlling the transfer of electric charge. And a detector for detecting a potential change due to a leak current of a capacitor that constitutes the monitoring memory cell, and a refresh timing is set based on the output of the detector for storing the information. In a semiconductor memory device having a refresh control circuit for refreshing memory cells, the monitor memory cell is provided in a region of the semiconductor substrate having a higher impurity concentration than a region in which the information storage memory cell is provided. It is characterized by

[0007]

The monitor memory cell is provided in a region having a higher impurity concentration than the region in which the information storage memory cell is provided. As a result, the depletion layer width is narrowed at the junction of the transistors forming the monitor memory cell and the electric field is increased, and the leakage current at the junction is significantly increased as compared with that of the information storage memory cell. (As illustrated in FIG. 2, if the impurity concentration Nsub on the substrate side increases by one digit,
The leak current I at the junction also increases by about one digit. ). Therefore, with a relatively small number of monitor memory cells,
The leak current of the magnitude required for the monitor can be obtained.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor memory device of the present invention will be described in detail below with reference to the embodiments shown in the drawings.

As shown in FIG. 1, this semiconductor memory device is provided with a memory cell (not shown) for storing information and a plurality of monitor memory cells MC connected in parallel in the same semiconductor substrate 1. ing. The monitor memory cell MC includes at least a storage electrode SE and a common electrode PL, and a capacitor C that holds electric charges. Monitor memory cell M
C is provided in a region 10 of the substrate 1 having a higher impurity concentration than the region in which the information storage memory cell is provided. A connection point between each monitor memory cell MC and the precharge transistor TRPC is connected to one input terminal (−) of the differential amplifier AMP. Differential amplifier AM
A predetermined reference potential Vref is supplied to the other input terminal (+) of P. During operation, the control signal φp temporarily turns on the precharge transistor TRPC,
A power supply potential Vcc is applied to the storage electrode SE side. On the other hand, the common electrode PL side is kept at the precharge potential HVcc (= Vcc / 2). In this state, the differential amplifier AMP detects the difference between the potential of the storage electrodes SE connected in parallel and the reference potential Vref, that is, the potential fluctuation of the storage electrodes SE due to the leak current. Then, the refresh timing is determined by the refresh control circuit 100 based on this potential fluctuation. Thus, the refresh timing can be determined for each chip by the refresh control circuit 100 according to the variation of the leak current due to the process variation, and the refresh timing can be determined according to the temperature environment during use.

Here, the monitor memory cell MC is
It is provided in the region 10 having a higher impurity concentration than the region in which the memory cell for storing information is provided. As a result, the leak current at the junction of the transistors forming the monitor memory cell MC is significantly increased as compared with that of the information storage memory cell. As illustrated in FIG. 2, the leakage current I at the junction is determined by the impurity concentration N of the region 10.
Although it increases with increasing sub, the impurity concentration Nsub can be increased by one digit to 1.5 digits compared to other regions at the actual level. Therefore, the leakage current I should be increased by one digit to 1.5 digits. You can Therefore, with a relatively small number of monitor memory cells, it is possible to obtain a leak current of a magnitude required for monitoring.

[0011]

As is apparent from the above, in the semiconductor memory device of the present invention, the monitor memory cell is provided in the region having a higher impurity concentration than the region in which the information storage memory cell is provided. It is possible to increase the leak current at the junction of the transistors that form the memory cell for use. Therefore, with a relatively small number of monitor memory cells, it is possible to obtain a leak current of a magnitude required for monitoring.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an impurity concentration on a substrate side and a leak current at a junction.

FIG. 3 is a diagram showing a conventional semiconductor memory device.

[Explanation of symbols]

 1 semiconductor substrate 10 high impurity concentration region 100 refresh control circuit AMP differential amplifier C capacitor MC memory cell PL common electrode SE storage electrode TRPC precharge transistor

Claims (1)

[Claims] 1. A memory cell for information storage and a memory cell for monitoring which are composed of a capacitor for holding electric charge and a transistor for controlling the input / output of the electric charge are provided in the same semiconductor substrate, and a capacitor for the memory cell for monitoring is formed. A semiconductor memory device having a detector for detecting a potential change due to a leak current and a refresh control circuit for refreshing the information storage memory cell by setting refresh timing based on the output of the detector, comprising: A semiconductor memory device, wherein the memory cell is provided in a region of the semiconductor substrate having a higher impurity concentration than a region in which the information storage memory cell is provided.