JPH05225147A - Multiprocessor type data processing system - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to reduce the frequency of use of the system bus and increase the number of connectable processors without using a large capacity cache memory. To provide a system. A bus interface 13a compares an address of an access request with an address stored in an address local memory 15a when a cache miss occurs at the time of an access request from a CPU 12a to a cache memory 17a. When the comparison result does not match and at the time of instruction read, the access request data is transferred from the other data local memory 14b to the CPU 12a, or when the comparison result does not match and at the time of data read or data write The data in another data local memory 15b and the data in another data local memory 15a are exchanged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system composed of a tightly coupled multiprocessor.

[0002]

2. Description of the Related Art Conventionally, in a data processing system including a tightly coupled multiprocessor, a plurality of processors are coupled through a system bus and share a single OS and a main memory. The main memory is fixedly connected to the system bus. Each processor accesses the main memory through the system bus and reads / writes data.
Perform a write.

In such a system, there is a system in which each processor has a cache memory in order to speed up access to the main memory. In this method, when the processor reads data from the main memory, it copies the read data and the corresponding address to the cache memory. When accessing the data of the same address next time, the processor will access the cache memory. This makes it possible to speed up access to the main memory. Further, there is an advantage that the frequency of use of the system bus of each processor is reduced and the number of connectable processors is increased.

[0004]

In the multiprocessor system, the access to the main memory can be speeded up by the method of using the cache memory. However, in recent years, processors have become faster,
The frequency of use of the system bus tends to increase relatively. Therefore, in order to further reduce the frequency of use of the system bus and increase the number of connectable processors, it is necessary to increase the capacity of the cache memory. However, increasing the capacity of the cache memory together with the main memory leads to an increase in system scale and cost.

It is an object of the present invention to provide a multiprocessor type data processing system which can reduce the frequency of use of the system bus and increase the number of connectable processors without using a large capacity cache memory. is there.

[0006]

The present invention is a tightly coupled multiprocessor type data processing system in which a plurality of processors are coupled by a system bus, and the data processing system is provided corresponding to each processor and shared by each processor. A plurality of data local memory means for configuring the main memory in a distributed manner; a plurality of address local memory means provided corresponding to each processor and storing an address corresponding to the data stored in each data local memory means,
System having cache memory means provided corresponding to each processor, address local memory means provided corresponding to each processor, and interface means provided corresponding to each processor to configure an interface with a system bus Is.

[0007]

According to the present invention, the interface means compares the address of the access request with the address stored in the address local memory means when a cache miss occurs at the time of the access request to the cache memory from the corresponding processor, and this comparison is made. When the result does not match and the instruction read mode, the access request data is transferred from the data local memory means corresponding to another processor to the corresponding processor, or when the comparison result does not match and the data read or data write mode is set. The data stored in the access request address of the data local memory means corresponding to the processor different from the access requesting processor and the data of the data local memory means corresponding to the access requesting processor are exchanged. That.

With such a configuration in which the main memories are arranged in a distributed manner, the system bus usage frequency of each processor is reduced without using a large capacity cache memory,
The number of connectable processors can be increased.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data processing system according to the embodiment. In this system, multiple processors that make up a tightly coupled multiprocessor are
Modules 10a and 10b are coupled via a system bus 11.

Each processor module 10a, 10b includes a processor (CPU) 12a, 12b, a bus interface 13a, 13b, a data local memory 14a, 14b.
, Address local memories 15a and 15b, status local memories 16a and 16b, and cache memory 17a
, 17b are provided. Local memory for data 14a
, 14b respectively constitute a part of the main memory 20 and store the data necessary for the data processing of the CPUs 12a, 12b. Local memory for address 15
Reference numerals a and 15b are memories that store addresses corresponding to the data local memories 14a and 14b.

The bus interfaces 13a and 13b constitute an interface with the system bus 11, and each CP
Access control to the data local memories 14a and 14b is executed in response to the access request from the U12a and 12b. The status local memories 16a and 16b are CPUs.
Data local memories 14a and 14 corresponding to 12a and 12b
This is a memory for storing a status S for maintaining the consistency of data between the cache memories 17a and 17b and the main memory when writing data to b.

Further, in this system, the I / O module 18 and the address initializer 19 are connected to the system bus.
Connected to 11. The I / O module 18 is an interface with various input / output devices necessary for the system.
The address initializer 19 is a circuit for initializing the contents stored in the address local memories 15a and 15b when the system power is turned on. In the initial operation, first, the X part of the address specifies that the initialization is performed, the Y part of the address selects the processor module, and the Y and Z parts of the address are sequentially incremented from the value “0” for the address. Local memory 15a, 15
This is done by writing the value of the Y portion of the address to b (see FIG. 2). Next, the operation of the embodiment will be described.

Each of the CPUs 12a and 12b has a main memory 20.
When accessing, the address as shown in FIG. 2 is output. The X part of the address is used for selecting the I / O, the memory and the address initializer. The Y portion of the address is used to determine whether or not the access request data from the CPUs 12a and 12b exists in the data local memories 14a and 14b. The Z portion of the address is used as an address input to the data local memories 14a and 14b and the address local memories 15a and 15b.

As shown in step S1 of FIG. 10, for example, the CPU 12a issues an access request to the main memory 20. The bus interface 13a accesses the cache memory 17a in response to the access request from the CPU 12a (step S2). If the address to be accessed exists in the cache memory 17a (NO in step S3), the CPU 12a will access the cache memory 17a and read out the necessary data (step S3).
4).

If a cache miss occurs (YES in step S3), the bus interface 13
a compares the address to be accessed output from the CPU 12a with the address stored in the address local memory 15a (step S5). Specifically, the CPU
Y part of address output from 12a and local memory 15
Compare with the address stored in a. Here, as shown in FIG. 3, the address L is stored in the address M of the address local memory 15a. Meanwhile, memory 15
Data local memory 14a corresponding to address M of a
Data N is stored in the address of.

When the CPU 12a outputs an address of "L" for the Y section and "M" for the Z section, the bus interface 13a causes the address M of the address local memory 15a.
The address L read from the CPU and the Y portion (L) from the CPU 12a are compared. If the comparison results match (YES in step S6) and the read mode is selected (NO in step S10 in FIG. 11), the bus interface 13a
The address of the data local memory 14a corresponding to the address M is accessed, that is, the bus interface 13a transfers the data N read from the data local memory 14a to the CPU 12a (step S1).
5, S16).

On the other hand, in the write mode (YES in step S10), the bus interface 13a writes the data from the CPU 12a to the address of the data local memory 14a corresponding to the address M and updates the stored data. (Step S11). Here, if the status S is set in the status local memory 16a, the bus interface 13a (step S1
2), the other module 10b is notified that the data update has been executed (step S13). That is, after the completion of the data update, if the set of the status S indicates that the updated storage data has moved between the processor modules 10a and 10b, the bus interface 13a executes a dummy write operation, The data update of this time is notified to the other module 10b through the system bus 11. This is to maintain the data consistency between the cache memory 17b of the other processor module 10b and the main memory 20 because the stored content of the main memory 20 is also updated by updating the data. Further, the bus interface 13a resets the status S of the status local memory 16a (step S14).

Next, when the comparison result does not match and the access content is the instruction read mode (YES in step S7), the bus interface 13a causes the data local memory 14 corresponding to another module 10b.
The address (M) requested by b is accessed and its memory
The target data stored in 14b is transferred to the CPU 12a (step S8).

Specifically, the CPU 12a of the module 10a
Address 0F55 (X = 0, Y = F, Z = 5
In the case of instruction read of 5), before access, as shown in FIG. 4, the local memories 14a, 15a, 16a of the module 10a are in the state as shown in FIG. It is assumed that the corresponding local memories 14b, 15b, 16b are in the state shown in FIG. That is, the local memory for each status 16
The status of a and 16b is indefinite (1/0), and the data local memories 14a and 14b store different data. After the access, as shown in FIG. 5, the status (1) is set in the status local memory 16b of the module 10b, but the status of the status local memory 16a of the module 10a does not change.

On the other hand, when the comparison result does not match and the access content is the data read mode (YES in step S17 of FIG. 12), the bus interface 13a stores the address M of the address local memory 15a of the module 10a. The contents and the stored contents of the address M of the local memory 15b for the address of the other module 10b are exchanged,
The stored contents of the address M of the data local memory 14a of the module 10a and the stored contents of the address M of the data local memory 14b of the other module 10b are exchanged (step S18). The bus interface 13a transfers the target data to be accessed to the CPU 12a (step S19). The bus interface 13a sets the status S in the status local memory 16a when the data moves between the modules 10a and 10b (step S20).

Specifically, the CPU 12a of the module 10a
Address 0F55 (X = 0, Y = F, Z = 5
5) When data is read, before access, as shown in FIG. 6, each local memory 14 of the module 10a is read.
a, 15a, 16a are in the state as shown in FIG.
In addition, each local memory 14b corresponding to the module 10b,
It is assumed that 15b and 16b are in a state as shown in FIG. That is, the status of each status local memory 16a, 16b is indefinite (1/0), and each data local memory 14a, 14b stores different data.

After the access, as shown in FIG. 7, the data in the data local memory 14b of the module 10b is moved to the data local memory 14a of the module 10a, and vice versa. Data moves. Further, the address of the address local memory 15b of the module 10b moves to the address local memory 15a of the module 10a, and vice versa. In addition, local memory for each status 16a, 16b
Is set to status (1).

When the comparison result does not match and the access content is the data write mode (N in step S17)
O), the bus interface 13a is the same module 10a
Contents of the address M of the local memory 15a of the other module and the local memory of the address of the other module 10b
Replace the stored contents of address M of 15b,
10a data local memory 14a memory contents of address M and other module 10b data local memory
The stored contents of the address M of 14b are exchanged (step S
21). The bus interface 13a updates the address in the address local memory 15a and the data stored in the data local memory 14a to the target data (step S22).

Specifically, the CPU 12a of the module 10a
Address 0F55 (X = 0, Y = F, Z = 5
When the data “1234” is written to the data 5) before access, as shown in FIG.
The local memories 14a, 15a, 16a of a are in the state as shown in FIG. 7A, and the local memories 14b, 15b, 16b corresponding to the module 10b are in the state as shown in FIG. Suppose there is. That is, the status of each status local memory 16a, 16b is indefinite (1/0), and each data local memory 14a, 14b stores different data.

After the access, as shown in FIG. 9, the data "1234" is stored in the data local memory 14a of the module 10a, and conversely, the data of the memory 14a is moved to the local memory 14b. Also, the address of the address local memory 15b of the module 10b moves to the address local memory 15a of the module 10a, and vice versa.
The address of a moves. Further, the status of the status local memory 16a is reset, and the status (1) is set in the status local memory 16b.

Next, as shown in step S23 of FIG. 13, the bus interface 13a is connected to the module 10a.
This is a case where access control is executed in response to an access request from the CPU 12b of the other module 10b via the system bus 11 instead of the CPU 12a. Even in this case,
The bus interface 13a compares the access target address transferred via the system bus 11 with the address stored in the address local memory 15a (step S24).

That is, Y of the address from the system bus 11
And the address L stored in the address M of the local memory 15a are compared. If the comparison result is a match (YES in step S25), the bus interface 13a
Access to the address corresponding to the address M of the data local memory 14a is permitted (step S2).
6). That is, the bus interface 13a sends an access permission signal to another module 10b through the system bus 11.
Forward to. Thus, in the read mode, the data N read from the data local memory 14a is transferred to the other module 10b via the system bus 11 by the bus interface 13a. Also,
In the write mode, the write data transferred from the other module 10b via the system bus 11 is written to the address corresponding to the address M of the data local memory 14a.

On the other hand, if the comparison results do not match (NO in step S25), the bus interface 13a does not respond to an access request made from another module 10b via the system bus 11 (step S2).
7). As a result, access to the data local memory 14a is disabled, and the other module 10b makes an access request to another module.

As described above, in the present system, the main memory is distributed and configured as the data local memories 14a and 14b of the processor modules 10a and 10b. The addresses corresponding to the stored contents of the local memories 14a and 14b are stored in the address local memories 15a and 15b. The bus interfaces 13a and 13b are C
When an access request is issued from the PUs 12a and 12b, it is determined whether or not the address to be accessed is stored in the address local memories 15a and 15b of the module.
Based on this judgment result, the bus interface 13a,
13b executes access control such as exchange of storage contents between the same module and another module, output of access permission, or no response to access request.

With such a configuration, each CPU can be provided without providing a main memory and a large capacity cache memory.
Can make necessary access to the main memory as needed for data processing. Therefore, high-speed access to the main memory can be realized. Further, the access operation in the module can reduce the frequency of use of the CPU system bus.

In addition, the status local memory 16a,
By providing 16b, it becomes possible to maintain the consistency of data between the cache memories 17a and 17b and the main memory when moving between the modules 10a and 10b.

[0033]

As described above in detail, according to the present invention, in the data processing system of the tightly coupled multiprocessor system, by realizing the distributed configuration of the main memory, the high speed access of the main memory by each processor and the relative access are realized. It is possible to reduce the frequency of use of various system buses. Therefore, the number of connectable processors to the system bus can be increased. Further, since it is possible to eliminate the need for a large capacity cache memory, it is possible to reduce the size of the entire system and reduce the cost associated with the system configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a data processing system according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram showing an address configuration according to the embodiment.

FIG. 3 is a conceptual diagram for explaining stored contents of a memory according to the embodiment.

FIG. 4 is a conceptual diagram for explaining stored contents of a memory according to the embodiment.

FIG. 5 is a conceptual diagram for explaining stored contents of a memory according to the embodiment.

FIG. 6 is a conceptual diagram for explaining stored contents of a memory according to the embodiment.

FIG. 7 is a conceptual diagram for explaining stored contents of a memory according to the embodiment.

FIG. 8 is a conceptual diagram for explaining stored contents of a memory according to the embodiment.

FIG. 9 is a conceptual diagram for explaining stored contents of a memory according to the embodiment.

FIG. 10 is a flowchart for explaining the operation of the embodiment.

FIG. 11 is a flowchart for explaining the operation of the embodiment.

FIG. 12 is a flowchart for explaining the operation of the embodiment.

FIG. 13 is a flowchart for explaining the operation of the embodiment.

[Explanation of symbols]

11 ... System bus, 12a, 12b ... CPU, 13a, 13b ...
Bus interface, 14a, 14b ... Local memory for data, 15a, 15b ... Local memory for address, 16a
, 16b… Local memory for status, 17a, 17b…
Cache memory.

Claims (1)

[Claims] 1. A distributed configuration of a plurality of processors, a system bus for exchanging data and addresses between the respective processors, and a main memory provided corresponding to the respective processors and shared by the respective processors. A plurality of data local memory means, a plurality of address local memory means provided corresponding to each processor for storing an address corresponding to the data stored in each data local memory means, Cache memory means provided corresponding to each processor for holding a part of data stored in the main memory; and local memory means for address and data local provided for each processor. When exchanging each data of the memory means between each processor, Status local memory means for storing memory information and an interface with the system bus provided corresponding to each processor, and when a cache miss occurs when an access request is made from the corresponding processor to the cache memory. And comparing the address of the access request with the address stored in the local memory means for addresses, and when the comparison result is inconsistent and in the instruction read mode, the local memory means for data corresponding to another processor is used. The data of the access request is transferred to the corresponding processor, or the data local memory corresponding to the processor different from the processor requesting the access when the comparison result does not match and each mode of the data read or the data write. Multiprocessor data, characterized in that it comprises interface means for exchanging the data stored at the address of the access request of the memory means and the data of the data local memory means corresponding to the processor requesting the access. Processing system.