JPH05224919A - Program execution system for microprocessor - Google Patents

Abstract

PURPOSE:To exclude duplication of a repeat frequency portion of a memory access time by providing a shift register group in place of a cache memory and a shift register control part, and controlling the number of times of read-out of a program from the shift register group. CONSTITUTION:In the case of executing a program used repeatedly such as a cache mode, etc., the program read out of a program memory 10 is inputted to a program decoder 50, and simultaneously, stored in a shift register group 30. The program stored in the shift register group 30 is stored in shift registers 31, 32,... at every word. A repetition of execution of a second time and thereafter is executed by reading out the program in order of registers 34, 33, 32 and 31, and receiving it through a program decoder 50 by a fact that a program executing part 60 drives a shift register control part 40 by the number of words set in advance and a constant determined from this number of times of repeat.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program execution system for a program-controlled microprocessor, and more particularly to a program execution system for frequently and repeatedly executing the same program.

[0002]

2. Description of the Related Art Conventionally, this type of microprocessor program execution system stores a program read from a program memory storing the program in a small-capacity cache memory and selects either the program memory or the cache memory. Then, the stored program was read and executed.

That is, a program read from a large-capacity program memory is temporarily stored in a cache memory in order to shorten a search time when reading a frequently used program.

[0004]

This conventional microprocessor program execution method has a configuration in which a frequently used program is read by selecting either a program memory or a cache memory. There is a problem in that it takes a long time to perform the memory access processing for, and particularly when the iterative processing such as the product / sum operation continues, the memory access processing time for the number of times of the iterating is required.

An object of the present invention is to provide a shift register (group) instead of a cache memory and a shift register control section for controlling this shift register (group), and store the shift register (group) from an execution program. It is an object of the present invention to provide a program execution method of a microprocessor which solves the above-mentioned problems by setting the size of a program and the number of repetitions and controlling the number of times the program is read out from the shift register (group) by the number of settings. ..

[0006]

The basic configuration of the program execution system of the microprocessor according to the present invention is such that the program-controlled microprocessor generates a program address and a multi-bit content read from the program memory. A shift register group having a plurality of shift registers for storing the codes, and a shift register control unit for instructing the number of times of repeating the program stored in the shift register group are repeatedly provided. Of the program memory and the shift register group to read and execute the program.

In one specific configuration of the shift register control described in this basic configuration, the number of times of repeating the program stored in the shift register group and the number of shift registers are set in the shift register control unit, The shift register control unit instructs the shift register group to read the stored program by designating the number of times of repetition and the number of times determined from the number of shift registers as the number of times of reading.

[0008]

According to the program execution method of the microprocessor by the above means, the size and the number of repetitions of the program to be repeatedly executed are extracted from the program executed by the execution unit of the microprocessor, and the number and the number of shift registers for this program are repeated. By notifying the shift register control unit of the number of times and setting the number of times, it is possible to read a predetermined number of repeated reads directly from the shift register group without the memory access processing time of retrieving and fetching the read program from the memory area.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

The microprocessor shown in FIG. 1 has a program memory 10, a program counter 20, a shift register group 30, a shift register control section 40, a program decoder 50 and a program execution section 60.

The program memory 10 stores a program to be executed.

The program counter 20 generates an execution address of a program read from the program memory 10 according to an instruction from the program execution unit 60.

The shift register group 30 includes registers 31, 32, ... Which sequentially store the program read from the program memory 10 to the program decoder 50 word by word.
Have.

The shift register control unit 40 sets the number of registers 41 and the number of repetitions 42 designated by the program execution unit 60, and instructs the shift register group 30 to read out the program to be stored.

The program decoder 50 converts the program read from the program memory 10 and the shift register group 30 into a code that can be executed by the program execution unit 60, and outputs the code.

The program execution unit 60 receives an input instruction from the outside and reads and executes the corresponding program. The program to be read is stored in the program memory 10 in advance.

Next, an example of a main procedure centering on the program execution unit 60 will be described with reference to FIG.

When the program execution unit 60 receives an instruction to execute the program stored in the program memory 10,
The program counter 20 is instructed to cause the predetermined program to generate an execution address for each read cycle.

The program memory 10 reads the program located at the execution address generated by the program counter 20, and sends this program to the program decoder 50. This program is code-converted by the program decoder 50 and read by the program execution unit 60.

In the case of program execution with repeated use such as the cache mode, the program read from the program memory 10 is input to the program decoder 50 and simultaneously stored in the shift register group 30.

Programs stored in the shift register group 30 are stored in the shift registers 31, 32, ... For each word. The shift register control unit 40 sends a read control signal to the shift register group 30 according to a preset number of words and a constant determined from the number of repetitions from the program execution unit 60 to program a program to be stored in the shift registers 31, 32, .... It is repeatedly sent to the decoder 50.

For example, when the program has four words and the number of executions is three, the first word program sent from the program memory 10 is input to the program decoder 50 and simultaneously stored in the register 31 of the shift register group 30. Next, when the program of the second word is input to the program decoder 50, the program stored in the register 31 is simultaneously transferred to the register 32, and then the program of the second word is stored in the register 31. Similarly, the third and fourth words are the program decoder 5.
At the same time as being input to 0, it is stored in the shift register group 30. In this way, the program execution unit 6 in which the first-time program group is input via the program decoder 50
Executed by 0.

For the next and subsequent repetition of execution, the program execution unit 60 drives the shift register control unit 40 to execute the program from the shift register group 30 to the registers 34, 33, 32, 31 in this order. It is executed by reading and receiving it through the program decoder 50.

Therefore, by repeatedly reading from the shift register group 30 twice, a total of three times of execution are performed. In this case, the number of registers 41 to the shift register control unit 40 is set to the numerical value 4, and the number of repetitions 42 is set to the numerical value 2.

Although the functional blocks are shown and described in this embodiment, the functions may be provided outside the microprocessor,
The above description does not limit the present invention because it can be separated and merged freely.

[0026]

As described above, according to the present invention, the program read from the program memory is stored in the shift register (group), and the program of the repetitive processing is read by only directly driving the shift register (group). Thus, there is an effect that the duplication of the memory access time due to the iterative process can be omitted.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 10 program memory 20 program counter 30 shift register group 31, 32 shift register 40 shift register control unit 50 program decoder 60 program execution unit

Claims (2)

[Claims] 1. A program control microprocessor for generating an address of a program to be read from a program memory for storing a program, and a plurality of shift registers for storing the contents read from the program memory in a multi-bit code. And a shift register control section for instructing the number of repetitions for repeatedly reading the program stored in the shift register group, and selecting one of the program counter and the shift register control section A program execution method for a microprocessor, which reads and executes a program from one of a program memory and a shift register group. 2. The number of repetitions and the number of shift registers for reading the program stored in the shift register group are set in the shift register control unit, and the shift register control unit determines the number of repetitions and the number of shift registers. 2. The program execution method of the microprocessor according to claim 1, wherein the stored program is read by instructing the shift register group with the number of times as the number of times of reading.