JPH0522403A - STM-ATM mutual conversion control method - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an STM-ATM mutual conversion control system that enables an economical network configuration that takes advantage of the features of ATM. [Structure] A memory 59 for storing a header value including VPI and VCI of an ATM cell is a rewritable memory, includes a timing circuit 60 and an empty cell pattern generation circuit 69, and includes an STM time slot and an ATM VPI.
The VCI and VCI are associated with each other by the control of a central processing unit (not shown) via the control line 156, and a time slot used at the end of the call is associated with an empty cell. To do.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a synchronous transfer mode (ST
M) is used in the STM-ATM interconversion control method for performing mutual conversion between STM information and ATM information when the path is transferred in the asynchronous transfer mode (ATM) virtual path.
An economical network configuration that makes use of the characteristics of ATM is possible.
The present invention relates to a TM-ATM mutual conversion method.

[0002]

2. Description of the Related Art The lines that make up a communication channel are usually
Although multiplexed on a physical transmission line (transmission line medium), time division multiplexing is generally used in digital transmission. The time division multiplexing method includes a method of multiplexing by identifying a position on the time axis and a method of multiplexing by identifying a label. The method of multiplexing by identifying the position on the time axis is time position multiplexing, or synchronous transfer mode (Synchron
ous Transfer Mode, hereinafter referred to as STM. ), A channel is assigned to a time position (time slot) in a frame as is well known, and a switching service is realized by exchanging time slots. On the other hand, as a label multiplex system, there is a packet system in which the length of an information field is variable and has been used.
A method of multiplexing using fixed-length packets (called cells) (asynchronous transfer mode (Asynchronous)
Transfer Mode, hereinafter referred to as ATM. )
Has been proposed (see CCITT (International Telegraph and Telephone Consultative Committee) Recommendation I.311 etc.). In ATM, information is transmitted only when information transfer is requested, so intermittent or continuous communication is possible according to the frequency, and it is possible to support any transfer rate from low speed to high speed. When there is no information, empty cells are inserted, so cells appear at fixed timings, and there is a feature that identification and exchange of cell heads can be performed at high speed by hardware.
It is considered to be a promising method as a transfer mode in future broadband communication networks.

FIG. 6 shows an international standard ATM cell structure. 11 is a cell, 12 is a header, 13 is information, 14 is a virtual path identification (hereinafter referred to as VPI), and 15 is a virtual circuit identification (hereinafter referred to as VPI). VCI), 16 is control information such as an error correction code, 17 is a sequence number, 18 is sequence number protection, and 19 is user information. Header 1
2 includes control information necessary for multiplexing, cell switching, traffic control, and the like. VPI and VCI correspond to the labels described above, and the cell can be identified by VPI and VCI.

In the node, the header 12 is usually analyzed by hardware to perform multiplexing, cell switching, and traffic control at high speed. Here, a channel (cell) identified by VPI + VCI is referred to as a virtual line (hereinafter referred to as VC), and a channel (cell) identified only by VPI without referring to VCI is referred to as a virtual path (hereinafter referred to as VP). Call. That is, considering the correspondence with the STM, the VC is each line, and the VP is a path that bundles the lines (for example, 24 lines of 1.5 Mbps). This state is shown in FIG. In FIG. 7, 21 is a VC, 22 is a VP, and 23 is a transmission line (transmission medium). In addition, the information 13 is divided into four classes according to service classes, and class 1 is used for services related to the present invention. The class 1 is composed of three of a sequence number 17, a sequence number protection 18, and user information 19. The sequence number 17 is a 4-bit structure and represents the sequence of the user information 19 by a cyclic number, and the sequence number protection 18 is a 4-bit error detection code of the sequence number 17. The sequence number 17 and the sequence number protection 18 are the ATM adaptation layer (AA
L) This is called control information, and information from the user is transferred as user information 19.

As with the STM, there are two nodes in the ATM network.
There is a kind of exchange (switching) function. That is, S
In the TM network, there are an exchange that exchanges on a line basis and a path switching device (also known as a cross connector) that exchanges (switches) on a path basis. Corresponding to these, the ATM network identifies VPI + VCI to identify VC units. ATM exchanges to be exchanged with each other, and a VP handler that identifies (identifies only VPI) and exchanges (switches) in VP units (hereinafter referred to as VPH).
Say. ) Exists. Just as the STM switch connects and disconnects a line when a call occurs and disappears, the ATM switch also connects and disconnects a VC when a call occurs and disappears. The path switching device of the STM does not switch for each call, and the connection state does not change unless the connection pattern is changed, and the connection state does not change even in the VPH unless the connection pattern is changed. That is, the ATM switch originates a call,
Although the connection status changes as it disappears, VPH connects according to a pattern determined by network design, etc.
In the normal operation method, the connection is changed only on the order of at most time. Further, similar to the STM switch, the ATM switch is provided with high functions such as a service control function and a billing function, but the VPH is not provided with these functions.

In the age when the whole communication network became ATM, information from subscribers can be transmitted and received in the form of cells.
In the transition process to all ATMs including subscribers, S
TM networks and ATM networks coexist, and these networks must be connected to each other, and mutual conversion of STM information and ATM information is required. The present invention relates to a mode of transferring an STM path using an ATM VP. Further, it is also possible to use the characteristics of ATM positively and use the VP of ATM as the STM path.

FIG. 4 shows an example of interconnection between an STM network and an ATM network. 150 is an STM network, 151 is an STM switch, 152 is a time division switch of the STM switch 151, 1
53 is the central processing unit of the STM switch 151, and 154 is S
TM-ATM converters, 155 and 156 are control lines,
157 is an STM highway, 158 is a transmission line, 160 is an ATM network, 161 is VPH, 162, 163 and 16
4 is an ATM switch, 165, 166 and 167 are transmission lines, 171, 172 and 173 are signal lines, and 174 is a signal network. Signal line 171 and signal network 17
Reference numeral 4 is, for example, a common line signal system.

Information from the STM switch 151 is sent to a specific time slot of the STM highway 151,
-The ATM converter 154 makes cells into time slots. At this time, VPI is added to the AAL control information and header.
And VCI are added. On the other hand, the cells from the ATM switch 162 are sent to the STM-ATM converter 154 for header or AA.
The L is removed, and the user information is output to the specific time slot of the STM highway 157. For example, for the AC traffic between the STM switch 151 and the ATM switch 162, it is necessary to set a certain number of communication channels between the STM switch 151 and the ATM switch 162. Therefore, conventionally, it has been considered that the STM highway 157 is generally configured to convert the STM information of a fixed number of time slots of the STM highway 157 into ATM information.

[0009]

However, if the STM information is simply fixedly converted into ATM information as described above, A
There is a problem that the TM feature cannot be fully utilized.

It is an object of the present invention to provide an STM-ATM mutual conversion control system which can realize an economical network configuration utilizing the characteristics of ATM by solving the above problems.

[0011]

The present invention comprises a conversion means for performing mutual conversion between STM information and ATM information by associating an STM time slot with a virtual path identification and virtual circuit identification of an ATM cell. In the STM-ATM mutual conversion control method, the conversion means performs correspondence between the time slot and the virtual path identification and the virtual circuit identification each time a call to be converted occurs, and the time slot used at the end of the call is vacant. It is characterized in that it includes variable association means for associating with a cell.

Further, in the present invention, the variable associating means predetermines a maximum number n of the number of time slots to be converted, and sets the number of available time slots according to time as m (n ≧ m). , (N−m) unused minimum time slots can be used as means for associating empty cells.

[0013]

In the process of converting the information on the STM time slot and the information into the ATM cell, the variable associating means generates the time slot, VPI and VC every time a call occurs.
By associating with I, and by associating the time slot used at the end of the call with an empty cell, the correspondence relationship between the time slot and VPI and VCI is dynamically controlled.

Therefore, the time slot and VPI and V
Since the allocation to the CI is dynamically controlled, it is possible to flexibly operate the network in response to traffic fluctuations and the like, and it is possible to make the communication network as a whole economical.

When the number of time slots to be converted differs depending on time such as daytime and nighttime, the maximum number n of time slots to be converted is set in advance and the number of available time slots is changed according to the time. The number is m
With (n ≧ m), empty cells can be associated with (n−m) unused time slots.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an STM-as an embodiment of the present invention.
It is a block configuration diagram showing a conversion unit from the STM information of the ATM conversion device to ATM information.

In FIG. 1, 157 is an STM highway, 52 is a frame synchronization circuit, 53 is a counter, 54 is a decoder, 55 and 56 are AND circuits, 57 and 5
8 is a first-in first-out (FIFO) format memory, 59 is a memory for storing header values, 60 is a timing circuit, 61, 62 and 63 are AND circuits,
64 is an OR circuit, 65 is an ATM highway, 66 and 67 are sequence number adding circuits which create a sequence number and sequence number protection and add it to user information, 68 is an AND circuit, and 69 is an empty cell pattern generation The circuit, 70 is SDH (Synchronous Digital Hierar)
chy) circuit (Special feature: "New synchronous interface")
NTT R & D. Vol. 39, NO. 4, 1990), 71 is an SDH interface, 73 is a transmission line terminating circuit, 74 is an interface circuit with a central control unit, 1
Reference numeral 56 is a control line with the central processing unit 153, 158 is a transmission line, and 101 to 124 are information lines.

Information is byte-multiplexed on the STM highway 157, and the number of multiplexed information is n.

The frame synchronization circuit 52 inputs the STM signal from the STM highway 157 via the information line 101, synchronizes the STM frame by a well-known technique, and resets the counter 53 at the frame position via the information line 102. . The value of the counter 53 is input to the decoder 54 via the information line 103, the counter value is decoded, the timing pulse is output to the information lines 104 and 105 for each time slot, and the STM information is output via the AND circuits 55 and 56. Memory 57 corresponding to the minimum path unit
And 58 are selectively input. Therefore, although omitted in FIG. 1, normally n memory 57 or the like, which corresponds to the number of multiplexed STMs, is prepared. Here, it is assumed that the memory 57 corresponds to the time slot 1 and the memory 58 corresponds to the time slot n. Thereafter, similarly, the information of each time slot is periodically written in the memories 57 and 58. Information of each time slot of STM is accumulated in the memories 57 and 58, and when 47 bytes are accumulated, it is read out to the ATM highway 65.

The memory 59 is a memory for storing a header,
For example, the address corresponds to the time slot number, and VCI, VPI, and other control information are transmitted from the central processing unit 153 to the control line 156 at the address corresponding to the time slot number.
It has already been written via the interface circuit 74 and the information line 118. The timing circuit 60 is a circuit for reading the contents of the sequence number adding circuits 66 and 67 and the memory 59 to the ATM highway 65 and generating a timing pulse for forming a cell. For example, at the timing of converting the information in time slot 1 into cells, the information in time slot 1 is transferred to the information line 11.
7, the memory 59 reads out the header written in the address 1 corresponding to the time slot 1 to the information line 110. This information is ANDed with the timing pulse output to the information line 113 by the AND circuit 63, and the OR circuit 64
Is output to the ATM highway 65 via. Next, a timing pulse is output to the information line 111, and the memory 57
47 bytes of information are read out to the information line 108 and input to the sequence number adding circuit 66. The sequence number adding circuit 66 adds the sequence number and the sequence number protection which are AAL control information and assembles them into 48 bytes of information. And is output to the ATM highway 65 via the information line 119, the AND circuit 61 and the OR circuit 64. By the above operation, 5 bytes of the header and 48 bytes of information (including the sequence number and sequence number protection as AAL control information) are combined to form one cell. Similarly, at the timing of converting the information of the timing pulse n into a cell, the information of the timing pulse n is given to the information line 117, and the information lines 113 and 1
A timing pulse is subsequently output to 12 and a 5-byte header and 48-byte information of the time slot n are made into cells.

The speed of the ATM highway 65 depends, of course, on the speed of the standardized SDH interface 71, although at least 53/47 times the speed of the STM highway 157 is required. For example, the speed of the SDH interface 71 is called STM-1 15
In the case of 5.52 Mbps, the payload speed of the information area carried by STM-1 is 150.336 Mbps. When there is no valid cell in the ATM highway 65, it is necessary to insert a vacant cell. When the STM information cell is not transmitted, a timing pulse for transmitting the vacant cell to the information line 122 is generated, and a vacant cell pattern generation circuit is generated. 69
The vacant cells from the above are sent to the ATM highway 65 via the AND circuit 68 and the OR circuit 64. An empty cell is represented by a specific VPI and VCI value,
For example, a case where VPI and VCI are all 0 is defined as an empty cell here. Therefore, the empty cell pattern generation circuit 69 generates a pattern in which VPI and VCI are all 0s. If VPI and VCI are all 0,
Whatever the other information 13 (see FIG. 6) is, it is determined to be an empty cell. In this way, the ATM highway 65 will be filled with cells without gaps. Timing circuit 6
The generation pattern of the timing pulse from 0 is the control line 1
56, the interface circuit 74, and the information line 121, and preset from the central processing unit 153.

The ATM information on the ATM highway 65 is S
It is input to the DH creation circuit 70, where SOH (Sect
Ion Overhead) is added and converted to SDH, and output to the SDH interface 71. In addition,
S that adds SOH to payload information and configures SDH
Since the DH creating circuit 70 is a well-known technique, its explanation is omitted (special feature "new synchronous interface" NTT
R & D Vol. 39, NO. 4, 1990).
The ATM information on the SDH interface 71 is sent to the transmission line 151 via the transmission line terminating circuit 73.

In the above description, the user information is converted into cells when 47 bytes are accumulated. However, for the purpose of reducing the transmission delay due to the conversion into cells due to voice information or the like, cells are converted into M bytes of less than 47 bytes and transferred. Is also possible. In this case, a timing pulse is generated in the information line 111 at a time interval for accumulating M bytes, and cells are formed at that timing. The pattern of this timing pulse is also the control line 15.
6, preset in the timing circuit 60 via the interface circuit 74 and the information line 121.

FIG. 2 shows an STM-as an embodiment of the present invention.
FIG. 3 is a block configuration diagram showing a conversion unit from ATM information to STM information of an ATM conversion device.

In FIG. 2, 201 is an ATM highway, 202 is a cell synchronization circuit, and 203 is VPI and VC.
A memory for converting I and the minimum path unit number, 204 is a decoder, 205 and 206 are AND circuits, 207, 20
8, 209 and 210 are FIFO type memories, 21
1, 212 and 213 are AND circuits, 214 is an OR circuit, 216 is a frame pattern circuit, 217 is a timing circuit, 218 is a cell analysis circuit, 219 is an AND circuit,
220 and 221 are sequence number check circuits and 222
Is an error monitoring circuit, 223 is an SDH decomposition circuit, 224 is an SDH interface, 225 is a transmission line terminating circuit, 15
7 is an STM highway, 431 is a transmission line, 74 is an interface circuit, 156 is a control line, and 301 to 329 are information lines.

Here, it is assumed that memories 207 and 209 and sequence number checking circuit 220 correspond to time slot No. 1, and memories 208 and 210 and sequence number checking circuit 221 correspond to time slot No. n. Therefore, although not shown, the memories 207 and 209 and the sequence number checking circuit 2
As for 20 and the like, n pieces corresponding to the required STM multiplexing number are prepared.

The transmission line 431 is terminated by the transmission line terminating device 225, and the information from the SDH interface 224 is SD.
The H decomposition circuit 223 removes the SOH, and the ATM information corresponding to the payload is output to the ATM highway 201.
By the way, the speed of SDH interface 224 is set to STM.
If it is -1 (155.520 Mbps), the speed of the ATM highway 201 will be 150.336 Mbps. A
The cell information from the TM highway 201 is input to the cell synchronization circuit 202 via the information line 301, and the cell synchronization circuit 2
02 generates a timing pulse on the information line 302, and the header is input to the cell analysis circuit 218 via the AND circuit 219. The cell analysis circuit 218 analyzes the header,
Information lines 304 are extracted by extracting valid VPI and VCI by performing header error check, empty cell detection, and the like.
Output to.

The memory 203 is a memory for storing the relationship between the VPI and VCI and the time slot.
Addresses are VPI and VCI, and a time slot number is written in the address. The time slot number stored in the memory 203 is usually rewritten for each call connection from the central processing unit 153 (see FIG. 4) via the control line 156, the interface circuit 74 and the information line 326. For example, assuming that the arriving cell is the information corresponding to the time slot No. 1, the memory 203 stores VPI and V
When the CI is read as the address, No. 1 is read as the time slot number, and the No. 1 time slot is input to the decoder 204 via the information line 305. Decoder 20
4 decodes the time slot No. 1, outputs a timing pulse to the information line 306, and inputs the 48 bytes of the information portion of the cell to the sequence number inspection circuit 220 via the AND circuit 205.

The sequence number check circuit 220 receives the 48-byte information, checks the sequence number which is the AAL control information, and reports the result to the error monitor circuit 222 via the information line 312. The error monitoring circuit 222 manages the error status of each time slot, and the information line 32
5, can be read by the central processing unit 153 via the interface circuit 74 and the control line 156. The 47-byte information obtained by removing the sequence number and the sequence number protection information (AAL control information) from the 48-byte information input to the sequence number inspection circuit 220 is input to the memory 207 via the information line 310. Memory 20
Numeral 7 is a memory of a FIFO format in which one word consists of 47 bytes, which is a memory for absorbing fluctuations in cell arrival time.
This prevents omission and duplication of information when converted to STM information. In the case of a cell having VPI and CVI not defined in the memory 203, for example, a stray cell or an empty cell, the time slot number is 0, for example, at the address corresponding to the VPI and VCI of the memory 203. Since no timing pulse is generated in the information line of the decoder 204, the information of that cell is ignored and does not adversely affect others.

The timing circuit 217 is a circuit for generating a timing pulse for outputting STM information to the STM highway 157. 4 from memory 207 periodically
The timing pulse for reading 7 bytes of information is the information line 3
When it occurs at 27, 47-byte information of the first-out of the memory 207 is input to the memory 209. At the timing of sending the first time slot, the information line 31
9, a timing pulse is generated, and 1-byte information is sent to the STM via the AND circuit 211 and the OR circuit 214.
It is output to the highway 157. Here, the information line 319
And the timing pulse generated on the information line 327 has a relationship of 1:47,
When the transfer of 47 bytes of information in the memory 209 is completed,
A timing pulse is generated on the information line 327 and the memory 2
First out information 07 is transferred to the memory 209. At the time of frame timing, a timing pulse is generated on the information line 321, and 1
The byte frame pattern is output to the STM highway 157 via the AND circuit 213 and the OR circuit 214.

By the above operation, the ATM information is converted into the STM information. The timing circuit 21
The timing pulse pattern of No. 7 is written in advance from the central processing unit 153 via the control line 156, the interface circuit 74 and the information line 329.

In the above description, it is assumed that the user information is made into cells when 47 bytes are accumulated. However, as described with reference to FIG. 1, in order to shorten the transmission delay due to the cells, M bytes less than 47 bytes are used. When the cells are transferred in the form of cells at, a timing pulse is generated in the information line 327 at a time interval at which M bytes are transferred to the STM highway 157, and 47 bytes are transferred from the memory 207 to the memory 209 at that timing. The first M bytes stored in the above are output to the STM highway 157. The patterns of these timing pulses are also preset in the timing circuit 217 via the control line 156, the interface circuit 74 and the information line 329.

FIG. 3 is an explanatory diagram showing the structures of the memory 59 for storing the header and the memory 203 for storing the relationship between the VPI and VCI and the time slot. In FIG. 3, 81 is the address of the memory 59, 82 is VPI, 83 is VCI, 84 is control information such as header error code, 241
Is the address of the memory 203, and 242 is the time slot number. The address 81 of the memory 59 corresponds to the time slot number, the header is written in the corresponding address 81, and the address 241 of the memory 203 is VPI and V.
The time slot number is written in the corresponding address 241 corresponding to the CI. At these addresses, values at the time of call connection, etc. from the central processing unit 153 to the control line 156, the interface circuit 74, and the information lines 118 and 32.
Written via 6.

In the above example, the memory 59 and the memory 203 are installed separately, but the time slot, VPI and VCI are set.
Since it is only necessary to take the correspondence with, it is possible to merge the pair into one memory. In this case, in order to obtain the VCI and VPI from the time slot, it is sufficient to search the time slot field in the memory and find the VCI and VPI of the address of the matching time slot, but compared with the configuration of FIG. High-speed memory is required because search time is required.

The feature of the present invention is that the correspondence between the time slot and the virtual path identification and the virtual circuit identification is performed every time a call to be converted occurs, and the time slot used at the end of the call is associated with an empty cell. As a means
The STM-ATM conversion unit of FIG. 1 is provided with a rewritable memory 59, a timing circuit 60, an empty cell pattern generation circuit 69, AND circuits 61 to 63, an OR circuit 64, and an interface circuit 74. In the STM converter, the rewritable memory 203, the timing generation circuit 217, the AND circuits 211 to 213, the OR circuit 2
14 and the interface circuit 74 so that they can be controlled by the central processing unit 153.

Next, an example of a call connection operation will be described with reference to FIG.

It is assumed that a call arrives at the STM switch 151 and the called number of the call is toward the ATM switch 162. The central processing unit 153 analyzes the called number of the call, selects the STM highway 157 which is the outgoing route, selects an empty time slot #k therein, and selects the ATM switch 16
VPI # i and empty VCI # j (V
The number of CIs is limited to 12 in advance, for example). Note that empty time slots and VCIs
If there is no call, the call is lost. The central processing unit 153 sets the VPI to the address corresponding to the time slot #k of the memory 59.
#I, VCI # j, and other control information are written via the control line 156, and VPI # i, VCI # of the memory 203 are written.
The time slot #k is assigned to the address corresponding to j by the control line 156.
Write through. The central processing unit 153 uses the signal line 17
1, connection information including the called number of the call, VPI # i, VCI # j, etc. is sent to the ATM switch 162 via the signal network 174 and the signal line 172. The subsequent connection operation is similar to that of the conventional STM network.

Therefore, the communication information of the call enters the time slot #k of the STM highway 157 through the time division switch 152, and the address corresponding to the time slot #k of the memory 59 of the STM-ATM converter 154 is accessed. , VPI # i, and VCI # j are assembled into a cell to which a header is added, and the cell is transmitted through the transmission path 158. Here, it is assumed that the cell having VPI # i is routed to the ATM switch 162 by the well-known technique in the VPH 161. Since the cell of the call has VPI # i, V
At the PH 161, the ATM exchange 162 is routed to
The cell arrives at the TM switch 162. In addition, VPI
Is a locally defined number between VPHs, so VPH161
Then, VPI # i is converted into VPI # p. Also, VP
Since H does not participate in VCI, VCI # j is stored as it is and transmitted to the ATM exchange 162.

Communication information of the call from the ATM switch 162 to the STM switch 151 is VPI # p and VCI #.
Transferred in the cell to which j is added, and STM in VPH 161
It is routed to the exchange 151. At this time, VPI # p
Is converted to VPI # i. Therefore, on the transmission path 158, the cell is a cell having the converted VPI # i and VCI # j. The cell is from ATM to ST in FIG.
The conversion section to M is entered, the header is extracted, and the memory 20
SPI to the time slot #k of the STM highway 157 via the sequence number check circuit 220 corresponding to the VPI #i and VCI #j of No. 3 and the memories 207 and 209.
It is output as TM information. As described above, the bidirectional communication of the communication information of the call is performed.

Next, it is assumed that the call arriving at the STM switch 151 is directed to the ATM switch 163. In this case, the VPI value is basically the same except that it is different from the above. That is, in the above case, since the call was to the ATM switch 162, the value of VPI is set to VPI # i.
In this case, VPI # h is set. However, it is assumed that the cell of VPI # h is set to be routed to the ATM switch 163 in the VPH 161. Also, VC
It is obvious that the values may be different from the above, because I and the time slot are selected as empty values.

Next, it is assumed that the call arriving at the ATM switch 162 is directed to the STM switch 151. The ATM exchange 162 analyzes the called number of the call, and the STM exchange 1
VPI # p connected to 51 and an empty VCI # r are selected, and connection information including VPI # p, VCI # r, incoming call number and the like is sent via the signal line 172, the signal network 174 and the signal line 171 to the STM. Transfer to the exchange 151. The central processing unit 153 receives the connection information and sets VPI # p to VPI #.
Convert to i. This is as described above for VPH1
This is because the conversion from VPI # p to VPI # i is performed at 61, and this relationship is held as data in the central processing unit 153. Also, an empty timeslot #
v and selects VPI # i and VCI to the address corresponding to the time slot #v of the memory 59 via the control line 156.
#R and VPI # i and VCI # of the memory 203
Write the time slot #v to the address corresponding to r. As described above, the information of the call is the time slot #v in the STM highway 157 and the VPI # in the ATM highway 65.
i and VCI # r cells will be transferred. Since the STM switch 151 and the ATM switch 162 select VCIs independently of each other, double capture of VCI occurs due to signal transmission delay, but double capture occurs similarly to the well-known bidirectional line capture. In such a case, it is possible to solve the problem by giving priority to selection of one of the exchanges. When the ATM switch 162 selects VCI and arrives at the STM switch 151, it is treated as a call loss when all the time slots are in use.

When the call is completed, the control line 156, the interface circuit 74 and the information line 1 are transmitted from the central processing unit 153.
The VPI and VCI of the address corresponding to the time slot #k (the above-mentioned example) assigned to the call in the memory 59 via 18 are set to 0, which indicates an empty cell, and the call via the information line 326. The time slot # 0 is set at the address of the memory 203 corresponding to the VPI #i and VCI #j assigned to the. By this operation, the cell corresponding to the time slot #k assigned to this call in the SDH interface 71 in FIG. 1 becomes an empty cell. In addition, the ATM switch 162 also has VPI #
Since p and VCI # k are released, cells of VPI # i and VCI # j do not arrive at the ATM highway 201 in FIG. Even if the release of the VPI and VCI in the ATM switch 162 is delayed, the memory 203
Since the time slot of the address corresponding to the relevant VPI # i and VCI # j is already # 0, ST of FIG.
The information of the cell is not output to the M highway 157, and the so-called line is disconnected. The released VPI #i, VCI #j and time slot #k are used for the next new call.

In the above connection operation, it is not necessary to change the correspondence between the time slot number, the VPI number, and the VCI number each time a call occurs.
The contents of 03 may be fixed, for example, the memories 59 and 203 may be read only memories. In this case,
VPI and VCI automatically when time slots are decided
Is decided. For example, the lines between the STM switch 151 and the ATM switch 162 are timeslots # 1 to # 20, ST
The lines between the M switch 151 and the ATM switch 163 are time slots # 21 to # 60, and the corresponding VP.
I and VCI are also decided, for example, STM switch 1
The call from 51 to ATM switch 162 is timeslot #
Select an empty time slot from 1 to # 20. For a call from the ATM switch 162 to the STM switch 151, the ATM switch 162 may select the VPI corresponding to the time slots # 1 to # 20 and the empty VCI.
Need not be rewritten for each call. However, by configuring the contents of the memory 59 and the memory 203 so that they can be rewritten at an arbitrary point in time such as the origination and termination of a call as in this embodiment, the effects described below can be obtained.

For example, referring to FIG. 4, the STM switch 15
The exchange traffic between 1 and the ATM switch 162 is 29 erlangs in the daytime, 12 erlangs in the nighttime, and 15 STM switches.
1 and ATM exchange 163 have 1 AC traffic during the day
2 erlangs and 29 erlangs at night. As described above, assuming that the time slot, VPI, and VPI are fixed as in the conventional method, assuming a call loss rate of 1/100, ST
The M switch 151 and the ATM switch 162 have 40 time slots (for example, time slot # 1 to time slot # 4 for a maximum value of 29 erlangs during the daytime and nighttime).
0) is required, and the STM switch 151 and ATM are required.
Similarly to the exchange 163, 40 time slots (for example, time slot # 41 to time slot # 80) are required, and a total of 80 time slots are required. As a result, the memory 57, the sequence number adding circuit 66, the sequence number checking circuit 220, and the memories 207 and 2 necessary for the time slot correspondence shown in FIGS.
There will be 80 of each 09.

On the other hand, according to this embodiment, the required time slots can be reduced. That is, the total traffic for both daytime and nighttime is 41 erlangs, and the required time slot is 54. As a result,
The required number of memories 57, sequence number adding circuit 66, sequence number checking circuit 220 and memories 207 and 209 are 54, respectively.
There is an effect that the hardware of the TM converter 154 can be made economical. In addition, the STM switch 151 and the ATM switch 16
Transmission line 15 required for traffic with 2 and 163
The transmission band of 8 can also be reduced.

Further, for example, the STM switch 151 and the AT
The exchange traffic with the M switch 162 is mostly during the daytime and less at night, and the ATM switch 164 and the ATM switch 1
It is assumed that the exchange traffic with 62 is low in the daytime and high in the nighttime. At this time, the transmission band required for the transmission line 165 is S
50 Mbps in the daytime and 10 Mbps in the nighttime for the AC traffic between the ATM switch 151 and the ATM switch 162.
s, 10 Mbps in the daytime and 60 M in the night, for AC traffic between the ATM switch 164 and the ATM switch 162.
bps. If the VPI, VCI, and time slot are fixed in the conventional method, the ST in the transmission line 165
The transmission band required for the AC traffic between the M switch 151 and the ATM switch 162 is 50 Mbps, which is the maximum value during the daytime and the nighttime, and the maximum value during the daytime and the nighttime required for the AC traffic between the ATM switch 164 and the ATM switch 162. It is necessary to prepare 60 Mbps for each of them and a total capacity of 110 Mbps is required.

On the other hand, according to this embodiment, the transmission line 1
The required transmission bandwidth of 65 can be reduced. In other words, the daytime needs a total of 60 Mbps of both daytime, and the nighttime requires a total of 70 Mbps of both nighttime, which is the maximum value of 70 Mbps of the total daytime and nighttime.
It is sufficient to prepare a capacity of s, and in this example, an economic effect of 40 Mbps is produced. AC traffic between STM switch 151 and ATM switch 163, ATM switch 164 and AT
With respect to the AC traffic with the M switch 163, the same effect can be obtained if the tendency of the AC traffic is similar.

To capture the explanation that the above effects occur, V
The fixed PI, VCI, and time slots mean that non-empty cells required for maximum daytime and nighttime traffic are always transferred between the STM switch 151 and the ATM switch 162. This is because the required transmission band is required for the transmission line 165. On the other hand, as in the present embodiment, the VPI and VCI are set for each call, and when the call ends, the VPI corresponding to the used time slot.
For VCI and VCI, the empty cell of # 0 is transferred. V
Since the empty cell is not routed in the PH 161, that is, the empty cell is not transferred to the transmission line 165,
When the traffic between the STM switch 151 and the ATM switch 162 decreases, the transmission band occupied by the traffic on the transmission path 165 decreases, and the decreased transmission band is used as the traffic between the ATM switch 164 and the ATM switch 162. This is because it can be accommodated. Similarly, A
When the traffic between the TM switch 164 and the ATM switch 162 decreases, the transmission band required by the traffic for the transmission path 165 also decreases. Therefore, the decrease is necessary for the traffic between the STM switch 151 and the ATM switch 162. It is possible to accommodate various transmission bands, and due to this mutual accommodation, the above-mentioned economic effect is produced.

In the above example, in order to ensure the quality (call loss rate, cell loss rate) between the STM switch 151 and the ATM switch 162, and between the ATM switch 164 and the ATM switch 162, the STM switch 151 and the ATM switch 162 are connected to each other. It is desirable to change the number of available VPIs, VCIs, and timeslots of, such as 30 available in the daytime and 7 available at night.
VPI # 0 and VCI # 0 indicating empty cells are written in VPI and VCI at addresses of the memory 59 corresponding to unused time slots.

Further, in the above case, since the STM information is converted into ATM information on a channel-by-channel basis, when changing the number of VPI, VCI and time slots at the time of switching between daytime and nighttime, the group relay conversion method in STM is used. There are no complications such as disconnecting existing calls, moving existing calls to other time slots, and waiting for the end of a certain group of calls (Shimazaki et al. Suggestion "
IEICE, IEICE Technical Report, SE74-63, 197
4).

Next, the effect of the present embodiment in the connection form shown in FIG. 5 different from that of FIG. 4 will be described.

In FIG. 5, 401 and 402 are STs.
M network, 403 is ATM network, 411, 412, 413 and 414 are STM exchanges, 421, 422 and 423.
VHP, 431, 432, 433, 434, 435 and 436 are transmission lines, and 441 and 442 are ATM exchanges. In order to simplify the drawing, the STM-ATM converter 154 installed in the STM switch is the STM switch 4.
11 and the like, and also omits signal lines and the like.

In FIG. 6, for example, the STM switch 411 is A
Inter-connects with the TM switch 441 and also STM
The exchange 411 is an AT with the STM exchanges 413 and 414.
It has a direct path through only the VHP 421 and the like without passing through the M switch 441 and the like. That is, ATM network 4
The VP of No. 03 is used to construct the STM path. Since the connection between the STM switch 411 and the ATM switch 441 and the like has been made in the above description of FIG. 4, here, the STM switch 411 and the STM switches 413 and 4 are used.
The connection with 14 will be described.

It will be described that the economic effect of this embodiment is produced even in this connection form. For example, the AC traffic between the STM switch 411 and the STM switch 413 is 50 erlangs in the daytime and 20 erlangs in the nighttime, and the STM switch 4 is
The exchange traffic between 12 and the STM switch 414 is assumed to be 10 erlangs during the day and 50 erlangs during the night. VP
In the case of the conventional method in which I, VCI and time slots are fixed, the STM switch 411 and the STM switch 41
It is necessary to consider 50 erlang, which is the maximum value during daytime and nighttime, as traffic with 3, and 50 erlang, which is maximum value during daytime and nighttime, as traffic between STM switch 412 and STM switch 414. is there. Therefore, the transmission band to be secured in the transmission lines 433 and 434 needs to be a band corresponding to 100 erlangs, which is the sum of the two. On the other hand, according to the present embodiment, the transmission band to be secured in the transmission lines 433 and 434 is the maximum value of 60 erlangs of the sum of both daytime and 70 erlangs of the sum of both night. A transmission band corresponding to 70 erlangs is sufficient, and an economic effect is produced as compared with the case where the VPI, VCI and time slot are fixed. Also, in order to ensure quality, VP that can be used
The same applies to changing the number of I, VCI, and the number of time slots between daytime and nighttime, and making cells corresponding to unused time slots empty cells.

[0056]

As described above, according to the present invention,
Only the STM information actually used for each call is converted into ATM information, and unused time slots are assigned empty cells. Therefore, in the case of a plurality of AC traffics, the time slot corresponding to the maximum number of traffics among them is allocated. It suffices to prepare them, and an economical communication network can be constructed in the connection between the STM network and the ATM network, and the effect is great.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an STM-ATM conversion unit of an STM-ATM conversion device according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing an ATM-STM conversion unit of an STM-ATM conversion device according to an embodiment of the present invention.

3 is an explanatory diagram showing a configuration of a memory 59 of FIG. 1 and a memory 203 of FIG.

FIG. 4 is a block diagram showing an example of interconnection between an STM network and an ATM network.

FIG. 5 is a block diagram showing another example of interconnection between an STM network and an ATM network.

FIG. 6 is an explanatory diagram showing an ATM cell configuration.

FIG. 7 is an explanatory diagram of a transmission line in an ATM network.

[Explanation of symbols]

11 cells 12 header 13 Information 14 Virtual path identification (VPI) 15 Virtual Circuit Identification (VCI) 16 Control information 17 Sequence number 18 Sequence number protection 19 User information 21 Virtual circuit (VC) 22 Virtual path (VP) 23 Transmission line 52 frame synchronization circuit 53 counter 54 decoder 55, 56 AND circuit 57-59 memory 60 timing circuit 61-63 AND circuit 64 OR circuit 65 ATM Highway 66, 67 Sequence number addition circuit 68 AND circuit 69 Empty cell pattern generation circuit 70 SHD creation circuit 71 SDH interface 73 Transmission line termination circuit 74 Interface circuit 81 82 VPI 83 VCI 84 Control information 101-124 information line 150 STM network 151 STM exchange 152 time division switch 153 Central processing unit 154 STM-ATM converter 155, 156 control line 157 STM Highway 158 transmission line 160 ATM network 161 VPH 162-164 ATM converter 165-167 transmission line 171 to 173 signal lines 174 Signal network 201 ATM Highway 202 Cell synchronization circuit 203 memory 204 decoder 205, 206 AND circuit 207-210 memory 211-213 AND circuit 214 OR circuit 216 frame pattern circuit 217 Timing circuit 218 cell analysis circuit 219 AND Circuit 220,221 Sequence number inspection circuit 222 Error monitoring circuit 223 SDH decomposition circuit 224 SDH interface 225 Transmission line termination circuit No. 241 242 time slot number 301-329 Information line 401, 402 STM network 403 ATM network 411-414 STM exchange 421-423 VPH 431-436 transmission path 441, 442 ATM switch

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location 9076-5K H04Q 11/04 P 9076-5K R

Claims (2)

[Claims] 1. An ST is provided by associating an STM time slot with an ATM cell virtual path identification and virtual circuit identification.
In the STM-ATM interconversion control system including a conversion means for performing mutual conversion between M information and ATM information, the conversion means generates a call for which correspondence between a time slot and a virtual path identification and a virtual circuit identification is to be converted. Every time,
An STM-ATM interconversion control system comprising variable association means for associating a time slot used at the end of the call with an empty cell. 2. The variable associating unit predetermines a maximum number n of the number of time slots to be converted, and m (n ≧ n) the number of time slots that can be used according to time.
2. The STM-ATM interconversion control method according to claim 1, further comprising means for associating an empty cell with (n−m) unused minimum time slots.