JPH05218834A - Reset circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunctions and also to surely restart a normal operation when the power voltage is restored by detecting the stop of en oscillation circuit end resetting a logic circuit part. CONSTITUTION:When the power voltage is applied to an entire system by a battery, etc., an oscillation circuit OSC part 1 starts to oscillate and at the same time a reset generating part 4 produces a reset signal RESET 8. When the battery voltage drops down to the lowest operating voltage of a logic circuit, the OSC part 1 stops its oscillation end the supply of a clock 6 is stopped to each block. An OS stop detecting part 2 decides an oscillation stop state end activates the detection output RESCK 7 to output it when the oscillation of the part 1 is stopped and for a period equivalent to several pulses after the start of the oscillation, i.e., while the integrated voltage value 9 is smaller than the comparing voltage 11 or larger than the comparing voltage 10. Under such conditions, 8 SYSRES 12 is activated via an OR element 5 and a logic circuit part 3 is reset. Thus the malfunctions of the part 3 can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit, and more particularly to a reset circuit for resetting a device to a logic circuit.

[0002]

2. Description of the Related Art Conventionally, a system reset circuit that generates a reset signal when power is turned on and a circuit are formed on an LSI chip by utilizing a time constant of an externally added capacitor and resistor for a logic circuit. A system reset circuit using a power supply voltage detection circuit is used as a system reset circuit of a logic circuit.

[0003]

In such a conventional reset circuit, when a battery or the like is used as the power supply applied to the logic circuit, the power supply voltage is lower than the minimum operating voltage of the logic circuit due to the decrease of the battery voltage. Then, there is a problem that malfunction occurs due to factors such as variations in the detection of the voltage detection circuit.

Further, there is a problem in that a reliable system reset cannot be generated when the power supply voltage is restored from the remaining power supply voltage due to the electric charge remaining in the power supply system capacity of the system when the battery is replaced, and a malfunction may occur.

An object of the present invention is to provide a reset circuit which solves the above-mentioned problems, can prevent malfunction, and can surely resume normal operation when the power supply voltage is restored.

[0006]

According to the present invention, there is provided a reset circuit comprising an oscillation circuit, a reset signal generation circuit for generating a reset signal for resetting a device when power is applied, and a logic circuit. And an element for logically adding the reset signal output of the reset signal generation circuit and the oscillation stop detection output of the oscillation stop detection circuit.

[0007]

1 is a block diagram showing a reset circuit according to a first embodiment of the present invention.

As shown in FIG. 1, the reset circuit of this embodiment includes an oscillation circuit 1 (hereinafter referred to as an OSC unit 1), an oscillation stop detection unit 2, a logic circuit 3, and a RESET generation for generating a reset signal. The unit 4 and the OR element 5 that outputs the logical sum of the reset signal output from the RESET generation unit 4 and the reset signal output from the oscillation stop detection unit 7.

Here, the OSC unit 1 is connected to a crystal oscillator externally. The OSC stop detection unit 2 includes an integrating circuit including a resistor and a capacitor, two differential amplifiers, and a NAND gate. The reset generation unit 4 has an inverter.

That is, the oscillation stop detecting section 2 includes an integrating circuit for converting the pulse signal voltage of the clock 6 output from the OSC section 1 into an integrated voltage value 9, and a voltage dividing circuit for generating the comparison voltages 10 and 11. When the integrated voltage value 9 is a voltage between the comparison voltage 10 and the comparison voltage 11, the reset signal RESCK7 is made non-active.

Next, the operation of FIG. 1 will be described with reference to FIG.

In FIG. 2, the power supply voltage VDD, the output clock 6 of the OSC unit 1, the integrated voltage value 9, the output RESCK7 of the OSC stop detection unit 2 and the output RESE of the reset generation unit.
Each waveform of the output SYSRES12 of the T8 and OR element 5 is shown. In FIG. 2, VL is the level indicating the lowest operating voltage, VT1 is the level of the comparison voltage 10, and VZ2 is the level of the comparison voltage 11.

First, when the power supply voltage VDD is applied to the entire system by a battery or the like, the OSC section 1 starts oscillating,
At the same time, the RESET generation unit 4 resets the reset signal RESET8.
To occur. By this RESET8, the logic circuit section 3 becomes S
YSRES 12 becomes active and a system reset is performed.

Next, as shown by voltage 9, RESET8 becomes active after a lapse of time corresponding to a predetermined time constant determined by the resistor and the capacitor, and logic circuit unit 3 becomes inactive by making SYSRES 12 inactive. Is released and the normal operation state is entered.

Here, a case where the battery voltage drops with the passage of time and becomes equal to or lower than the minimum operating voltage of the logic circuit will be described.

In this case, the OSC section 1 first stops the oscillation. When the OSC unit 1 is stopped, the supply of the clock 6 is stopped for each block.

The OSC stop detection unit 2 detects that the oscillation is stopped during the oscillation stop and during several pulses after the start of the oscillation, that is, when the integrated voltage value 9 is lower than the comparison voltage 11 or higher than the comparison voltage 10. The output RESCK7 is activated and output.

At this time, through the OR element 5, the SYSRES
12 is activated and the logic circuit unit 3 is reset. As a result, malfunction of the logic circuit section can be prevented.

The power supply voltage VDD can be changed by changing the battery.
Is restored, the OSC unit 1 regenerates the clock (CK) 6. By this clock 6, the integrated voltage value 9 of the OSC stop detection unit 2 becomes between the comparison voltage 10 and the comparison voltage 11, and the reset signal RESCK7 becomes non-active. As a result, the SYSRES 12 signal is made inactive, the reset state of the logic circuit section 3 is released, and the normal operation is restored.

FIG. 3 is a circuit diagram showing resetting according to the second embodiment of the present invention. In FIG. 3, this embodiment is similar to the first embodiment, but the detection circuit of the OSC stop detection unit 2 is different, so only the OSC stop detection unit 21 of that part will be described.

In the oscillation stop detector 21 of the second embodiment, a clock 22 is input, and a differential circuit consisting of a capacitor and a resistor converts it into a differential voltage value 24. When the potential is higher than the comparison voltage 25, RESCK23 The oscillation state is detected when the output of becomes inactive.

When the oscillation is stopped, the signal of the clock 22 becomes a constant potential, so that the differential voltage value 24 becomes the comparison voltage 25.
The potential becomes lower, the RESCK23 output becomes active, and the logic circuit is reset.

[0023]

As described above, according to the present invention, by detecting the stoppage of the oscillation circuit that occurs when the power supply voltage drops due to the use of the battery, the logic circuit unit is pulled into the reset state, and the logic circuit unit is reset. It is possible to prevent the erroneous operation, and it is possible to reliably restart the normal operation when the oscillation circuit enters the oscillation state.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a reset circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing the operation of the circuit shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 1 Oscillation circuit part 2,21 Oscillation stop detection part 3 Logic circuit part 4 Reset generation part 5 OR element 6,22 Clock 7,23 RESCK 8 RESET 9 Integrated voltage value 10, 11, 25 Comparison voltage 12 SYSRES 24 24 Differential voltage

Claims (1)

[Claims] 1. A reset circuit including an oscillation circuit, a reset signal generation circuit for generating a reset signal for resetting a device when power is applied, and a logic circuit, and an oscillation stop detection for detecting stop of oscillation in the oscillation circuit. A reset circuit comprising: a circuit; and an element for performing a logical sum of a reset signal output of the reset signal generation circuit and an oscillation stop detection output of the oscillation stop detection circuit.