JPH05218814A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To obtain a compact flip-flop circuit which works at a high spied and with the small power consumption by transferring the input information accumulated in a capacitor via an inverter consisting of a direct coupled field effect transistor logic circuit. CONSTITUTION:A master latch circuit 41 transfers the new input data D1 to a capacitor C1 via a field effect transistor TR Q41 in the rising timing of a clock signal CK. At the same time, the circuit 41 outputs the newly stored latch data D2 to a slave via an inverter 141. Similarly, a slave latch circuit 42 transfers the data D2 inputted from the circuit 41 to a capacitor C2 in the rising timing of a clock signal ICK. At the same time, the circuit 42 outputs the data D2 as the latch data D3 via an inverter 142.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIGS. 6 and 7) Problem to be Solved by the Invention (FIGS. 8 to 12) Means for Solving the Problem (FIG. 1) Action (FIG. 5) Example (FIG. 1) ~ Fig. 5) Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit, and is suitable for application to, for example, a master / slave flip-flop circuit incorporated in an integrated circuit and operating at high speed.

[0003]

2. Description of the Related Art Conventionally, semiconductor integrated circuits have been further increased in size and speed, and reduction of the chip area and reduction of power consumption have been important issues. For example, in mobile communication devices such as mobile phones, signal modulation circuit ICs (integr
There is a demand for miniaturization and low power consumption of the ated circuit (Fig. 6).

In the case of a mobile phone, since a digital signal normally transmitted with a bandwidth of about 300 [KHz] with respect to a carrier frequency of 2 [GHz] is transmitted and received, π / 4 phase shift modulation for transmitting and receiving the digital signal is performed. It is desired to further reduce the size of the circuit 1 and reduce the power consumption.

When the carrier signal S1 is input to the frequency doubling mixer 2, the π / 4 phase shift modulating circuit 1 converts the carrier signal S1 into the doubling carrier signals S2 and S3 which are different in phase by 180 °, and at the same time the doubling frequency is multiplied. The frequencies of the carrier signals S2 and S3 are doubled with respect to the carrier frequency f and output.

After that, the 1/2 divider circuits 3 and 4 divide the phase of the double-multiplied carrier signals S2 and S3 into 1/2, and at the same time, the phase-modulated intermediate frequency signal S4 (0 °).
Phase), S5 (180 ° phase), S6 (90 ° phase) and S
7 (270 ° phase) is supplied to the mixers 5 and 6, superposed on the high frequency signals S8 and S9, and output as an intermediate frequency output.

Also in the case of a phase locked loop (PLL) circuit which is generally widely used in signal processing circuits, it is desirable that it is small and has low power consumption, like the π / 4 phase shift modulation circuit 1 (FIG. 7). ).

Incidentally, the PLL circuit 10 uses the local oscillation signal S
When 10 is input to the phase comparator 11, the loop filter 1
2 compares the phase of the oscillation output S11 of the voltage controlled oscillation circuit 13 and the phase of the local oscillation signal S10, and outputs the comparison output to the M-ary programmable counter 14 and the 1 / N frequency dividing circuit 15 sequentially. The frequency-divided output S12 obtained by frequency-dividing the local oscillation signal S10 into an integral multiple (N × M multiples) is output via the local oscillation signal S10.

[0009]

By the way, the 1/2 divider circuits 3 and 4 and 1 / N components used for frequency modulation and synchronization of data with the clock in the π / 4 phase shift modulator circuit 1 and the PLL circuit 10, respectively. As the circuit 15, conventionally, a master / slave flip-flop circuit as shown in FIG. 8 is generally used.

The master-slave flip-flop circuit 20 is composed of a master flip-flop circuit 21 composed of 2-input NOR gates N1 to N4 and a slave flip-flop circuit 22 composed of 2-input NOR gates N5 to N8. There is. Incidentally, each of the two-input NOR gates N1 to N8 is configured by connecting a load resistor R1 to the drains of the field effect transistors Q1 and Q2 connected in parallel, as shown in FIG.

However, in the master / slave flip-flop circuit 20, the maximum operating frequency is 4 with respect to the signal propagation delay time [tpd] per NOR gate.
Delay time of four stages (that is, NOR gates N1-N3-N5-N7 and NOR gates N2-N4-N6-N8) 4
Since it is the reciprocal of [tpd], it has been an obstacle to speeding up.

Therefore, as a flip-flop circuit which can operate at a higher speed, a memory cell type master-slave flip-flop circuit 25 as shown in FIG. 10 has been proposed.

Here, each flip-flop circuit 26 and 2 is provided.
7 is a field effect transistor Q by inputting the clock signal CK and the inverted clock signal ICK to the gate.
ON / OFF control of 5, Q6 and Q7, Q8, DCFL
(Direct Coupled Field Effect Transistor Logic) circuit inverters I1, I2 and I3, I4, the latched data is latched by the inverter circuit I5, I
6 and I7 and I8 are transferred to the subsequent stages, respectively.

Incidentally, each of the inverters I1 to I8 is shown in FIG.
As shown in, the load resistance R2 is connected to the drain of the field effect transistor Q3. In the case of the flip-flop circuit 25, the maximum operating frequency is the reciprocal of the delay time 2 [tpd] of two stages (that is, I5-I7 and I6-I8 minutes), and therefore is twice as large as that of the flip-flop circuit 20. Although it can be operated, the power consumption could not be sufficiently reduced because eight inverters had to be connected.

Therefore, as a flip-flop circuit capable of further reducing power consumption, a resistance feedback type master / slave flip-flop circuit 30 as shown in FIG. 12 has been proposed.

Here, each flip-flop circuit 31 and 3 is provided.
2 receives the clock signal CK and the inverted clock signal ICK at its gate to input the field effect transistor Q.
ON / OFF control of 5, Q6 and Q7, Q8, DCFL
The output signal transferred to the subsequent stage via the inverters I5, I6 and I7, I8 of the circuit is transferred to the resistors R3, R4 and R5, R.
It is configured to feed back to the input side of the inverters I6, I5 and I8, I7 via 6.

In the flip-flop circuit 30, since the number of inverters required is four, the power consumption can be halved as compared with the flip-flop circuits 20 and 25. However, in order to develop a small-sized integrated circuit with high speed and low power consumption, a flip-flop circuit with lower power consumption, a smaller number of elements used, and a smaller circuit scale is desired.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a flip-flop circuit which is much smaller and consumes less power than conventional ones.

[0019]

In order to solve such a problem, in the present invention, the input information D is read into the first flip-flop circuit 41 at the timing when the clock pulse CK rises, and the first information is read at the timing when the following clock pulse CK falls. The input information D stored in the flip-flop circuit 41 is transferred to the second flip-flop circuit 4 in the subsequent stage.
In the master-slave flip-flop circuit 40 for transferring data to the first and second flip-flop circuits 40 and 41, the first and second flip-flop circuits 41 and 42 are the first and second transfer gates Q41 and Q42, which are field effect transistors, and the transfer gate Q4.
1, the first and second capacitors C1 and C2 for accumulating the input information D read via Q42, and a direct-coupled field effect transistor logic circuit (DCFL: Direct Coupled).
Field effect transistor Logic), and is provided with first and second inverters I41 and I42 for inverting and outputting the input information D stored in the first and second capacitors C1 and C2 in the subsequent stage. ..

[0020]

The first and second transfer gates Q41 and Q42 and the first and second capacitors C which are field effect transistors.
1 and C2, the latch portions of the first and second flip-flop circuits are composed of dynamic random memory cells, and the input information D stored in the latch portions is used for the direct connection field effect transistor logic circuit (DCFL: Direct Coupled).
By outputting through the first and second inverters I41 and I42 formed of field effect transistor logic, the flip-flop circuit can be operated in a high frequency with a further smaller size and lower power consumption than the conventional one.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, a master-slave flip-flop circuit 40 is composed of a field-effect transistor Q41, a capacitor C1 and an inverter I41 of a DCFL circuit, and a master-flip-flop circuit 41 and a field-effect transistor Q42, a capacitor C2 and an inverter of the DCFL circuit. It is configured by a slave flip-flop circuit 42 configured by I42.

The field effect transistors Q41 and Q42 for the transfer gates are capacitors C1 and C2, respectively.
In this way, a memory cell of a DRAM (Dynamic Random Access Memory) is configured, and a clock signal CK and an inverted clock signal ICK supplied to each gate.
The data D1 and D2 to the capacitors C1 and C2.
It is designed to latch.

That is, the master flip-flop circuit 4
1 transfers new input data D1 to the capacitor C1 via the field effect transistor Q41 at the timing of rising of the clock signal CK, and newly stored latch data D2 is newly latched by the slave via the inverter I41. Output latch data D2.
Further, the master flip-flop circuit 41 is adapted to turn off the field effect transistor Q41 at the timing when the clock signal CK falls to transfer the latch data D2 held in the capacitor C1 to the slave side.

Similarly, the slave flip-flop circuit 4
2 is the timing when the clock signal ICK rises,
The latch data D2 input from the master flip-flop circuit 41 is transferred to the capacitor C2, and the latch data D2 is output as the latch data D3 via the inverter I42. Further, the slave flip-flop circuit 42 uses a clock signal IC
At the timing when K falls, the field effect transistor Q
42 is turned off, and the latch data D3 held in the capacitor C2 is transferred to the subsequent stage.

In the above construction, the data output D3 of the flip-flop circuit 40 is fed back to the input side of the master flip-flop 41 via the inverter I43 (FIG. 2), so that the flip-flop circuit operates as a 1/2 divider circuit. -Simulating the logical operation of the flopping circuit 40.

Here, the field effect transistors Q41 and Q
42 are enhancement type gallium arsenide junction type field effect transistors (J-FETs), and have a gate width of 8 [μm] and a threshold voltage V _TH of 0.26.
[V] and mutual inductance g _m are set to 400 [mS / mm].

The capacitors C1 and C2 have a capacitance of 20.
As shown in FIG. 3 (A), each of the inverters I41 and I42 has an enhancement type gallium arsenide J-FET with a gate width of 40 [μm] and a resistance value of
The load resistance R41 is 40 [Ω].

Further, inverters I44 and I45 for supplying the clock signal CK to the master flip-flop 41, inverters I46 and I47 for supplying the inverted clock signal ICK to the slave flip-flop 42, and an inverter I43 for feeding back the output of the slave side to the master side. As shown in FIG. 3B, each has a gate width of 8 [μ
[m] enhancement type gallium arsenide J-FET
And a load resistor R42 having a resistance value of 1 [kΩ].

Here, the flip-flop circuit 40 is set to 2 [G
Hz] and the inverted clock signal ICK with a phase difference of 180 ° (FIG. 4 (A)), the clock signal CK is set to 1 from the output end as shown in FIG. 4 (B).
It can be seen that the frequency-divided output divided by / 2 is output and operates as a 1/2 frequency-dividing circuit in a high frequency band of 2 [GHz].

Further, the power consumption of the flip-flop circuit 40 can be reduced to about 1/4 of the power consumption of the conventional flip-flop circuit 20 (FIG. 8) because it requires only two inverters I41 and I42 of the DCFL circuit. Further, the power consumption of the flip-flop circuit 30 (FIG. 12) can be reduced to about 1/2.

By the way, even if the power consumption of the inverters I41 and I42 is set small, the flip-flop circuit 40 is concerned.
Operates normally, and the total power consumption of the flip-flop circuit 40 is about 0.3 [mW], which can be reduced by about one digit compared with the conventional one.

As for the power consumption by the master and slave flip-flop circuits, as shown by the black circles in FIG. 5, the power consumption of the conventional master flip-flop circuit having the same operating frequency (shown by white circles in FIG. 5).
It is much smaller than.

According to the above configuration, the master flip-flop circuit 41 and the slave flip-flop circuit 42.
Each is composed of a DRAM memory cell and a DCFL circuit inverter, and the gate of each field effect transistor is controlled to be turned on / off by a clock signal CK and an inverted clock signal ICK, so that the number of elements is smaller than in the past, and thus the size is small. Thus, it is possible to obtain a flip-flop circuit with much lower power consumption.

In the above embodiment, the case where the input signal is latched to the capacitors C1 and C2 connected to the sources of the transistors Q41 and Q42 for the transfer gates of the master and slave flip-flop circuits 41 and 42 has been described. However, the present invention is not limited to this, and the input signal may be latched using the capacitance parasitic on the transmission line. By doing so, the number of elements can be further reduced.

Further, in the above embodiment, the master / slave flip-flop circuit 40 is divided into 1/2 frequency dividing circuit 4.
However, the present invention is not limited to this and can be widely applied to other frequency dividing circuits, synchronizing circuits, and the like.

[0037]

As described above, according to the present invention, the latch sections of the first and second flip-flop circuits are composed of transfer gates and capacitors which are field effect transistors, and the input information stored in the capacitors is directly connected. A flip-flop circuit that operates at high speed with low power consumption can be realized with a much smaller number of elements than in the conventional case by transferring data through an inverter formed of a field effect transistor logic circuit.

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of a master / slave type flip-flop circuit configured by a flip-flop circuit according to the present invention.

FIG. 2 is a connection diagram showing a 1/2 frequency dividing circuit configured by a flip-flop circuit according to the present invention.

FIG. 3 is a connection diagram for explaining an inverter that constitutes a flip-flop circuit according to the present invention.

FIG. 4 is an input / output characteristic curve diagram for explaining the operation characteristic of the 1/2 frequency dividing circuit.

FIG. 5 is a characteristic curve diagram for explaining operating characteristics of the flip-flop circuit according to the present invention.

FIG. 6 is a connection diagram showing a configuration of a π / 4 phase shift shift modulation circuit.

FIG. 7 is a connection diagram showing a configuration of a PLL circuit.

FIG. 8 is a connection diagram showing a conventional master-slave flip-flop circuit.

FIG. 9 is a connection diagram showing a configuration of a NOR gate.

FIG. 10 is a connection diagram showing a conventional master / slave flip-flop circuit for high-speed operation.

FIG. 11 is a connection diagram showing a configuration of the inverter circuit.

FIG. 12 is a connection diagram showing a conventional master / slave type flip-flop circuit for low power consumption.

[Explanation of reference numerals] 40 ... Master / slave flip-flop circuit, 4
1, 42 ... Flip-flop circuit, 43 ... 1/2 divider circuit, Q41, Q42 ... Field-effect transistor, C
1, C2 ... Capacitor, I41, I42 ... Inverter.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] April 17, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

The master-slave flip-flop circuit 20 comprises a master latch circuit 21 composed of 2-input NOR gates N1 to N4 and a 2-input NOR gate N5.
.About.N8 in the slave latch circuit 22. Incidentally, each of the two-input NOR gates N1 to N8 is configured by connecting a load resistor R1 to the drains of the field effect transistors Q1 and Q2 connected in parallel, as shown in FIG.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

Here, each latch circuit 31 and 32 controls ON / OFF of the field effect transistors Q5, Q6 and Q7, Q8 by inputting the clock signal CK and the inverted clock signal ICK to the gates thereof, and the inverter I5 of the DCFL circuit. , I6 and I7 and I8, the output signal transferred to the subsequent stage is fed back to the input side of the inverters I6, I5 and I8 and I7 via the resistors R3, R4 and R5 and R6.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0019

[Correction method] Change

[Correction content]

[0019]

In order to solve such a problem, according to the present invention, the input information D is read into the first latch circuit 41 at the timing when the clock pulse CK rises, and the first information is read at the timing when the following clock pulse CK falls. In the master-slave flip-flop circuit 40 that transfers the input information D stored in the latch circuit 41 to the second latch circuit 42 in the subsequent stage, the first and second latch circuits 41 and 42 are field effect transistors. First and second transfer gates Q41 and Q42, first and second capacitors C1 and C2 for accumulating the input information D read through the transfer gates Q41 and Q42, and a direct connection field effect transistor logic circuit ( DCFL: Dir
ectCoupled Field effect t
input information D stored in the first and second capacitors C1 and C2.
And a second inverter I for inverting and outputting
41 and I42.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

[0020]

The first and second transfer gates Q41 and Q42 and the first and second capacitors C which are field effect transistors.
1 and C2 provide the first and second flip-flop circuits.
The latch section of No. 2 is composed of a memory cell of a dynamic random access memory, and the input information D stored in the latch section is used as a direct connection field effect transistor logic circuit (DCF).
L: Direct Coupled Field ef
By outputting through the first and second inverters I41 and I42 composed of a correct transistor Logc), the flip-flop circuit can be operated in a higher frequency with a smaller size and lower power consumption than the conventional flip-flop circuit.

[Procedure correction 6]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

In FIG. 1, a master-slave flip-flop circuit 40 comprises a master latch circuit 41 composed of a field effect transistor Q41, a capacitor C1 and an inverter I41 of a DCFL circuit and a field effect transistor Q42, a capacitor C2 and an inverter of a DCFL circuit. It is configured by a slave latch circuit 42 configured by I42.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction content]

That is, the master latch circuit 41 transfers new input data D1 to the capacitor C1 via the field effect transistor Q41 at the timing when the clock signal CK rises, and at the same time stores the newly stored latch data D2 in the inverter I41. The latched latch data D2 is newly output to the slave via the slave. Further, the master latch circuit 41 turns off the field effect transistor Q41 at the timing when the clock signal CK falls, and the latch data D2 held in the capacitor C1.
Is transferred to the slave side.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

[0025] Similarly slave latch circuit 42 at the timing when the clock signal ICK rises, the master-La
The latch data D2 input from the latch circuit 41 is transferred to the capacitor C2, and the latch data D2 is output as the latch data D3 via the inverter I42. The slave latch circuit 42
Turns off the field effect transistor Q42 at the timing when the clock signal ICK falls, and the capacitor C
The latch data D3 held in No. 2 is transferred to the subsequent stage.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

In the above construction, the data output D3 of the flip-flop circuit 40 is fed back to the input side of the master latch 41 via the inverter I43 (FIG. 2), thereby operating as a 1/2 frequency divider circuit. -Simulating the logical operation of the flopping circuit 40.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction content]

The capacitors C1 and C2 have a capacitance of 20.
As shown in FIG. 3A, each of the inverters I41 and I42 has an enhancement type gallium arsenide J-FET having a gate width of 40 [μm] and a load resistance of 4 [kΩ] . It consists of R41.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction content]

Further power consumption by the flip-flop circuit, as shown by black dots in FIG. 5, in the power consumption (Figure 5 of a conventional master-slave type Furitsupufuro <br/> flop circuit having an operating frequency of comparable white circles Markedly smaller than

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction content]

According to the above construction, the master latch circuit 41 and the slave latch circuit 42 are respectively constituted by the memory cell of the DRAM and the inverter of the DCFL circuit, and the gate of each field effect transistor is provided with the clock signal CK and the inverted clock signal. By performing on / off control with the ICK, the number of elements is smaller than in the conventional case, so that a flip-flop circuit that is small and consumes much less power can be obtained.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

In the above embodiment, the case where the input signal is latched to the capacitors C1 and C2 connected to the sources of the transistors Q41 and Q42 for the transfer gates of the master and slave latch circuits 41 and 42 has been described. However, the present invention is not limited to this, and the input signal may be latched using the capacitance parasitic on the transmission line. By doing so, the number of elements can be further reduced.

[Procedure Amendment 14]

[Document name to be amended] Statement

[Name of item to be corrected] 0037

[Correction method] Change

[Correction content]

[0037]

As described above, according to the present invention, the master
The latch part of the slave flip-flop circuit is composed of a transfer gate consisting of a field effect transistor and a capacitor.
A flip-flop circuit that operates at high speed with low power consumption can be realized with a much smaller number of elements than before by transferring the input information accumulated in the capacitor via an inverter composed of a direct-coupled field effect transistor logic circuit. You can

[Procedure Amendment 15]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a connection diagram showing an embodiment of a master-slave flip-flop circuit configured by a latch circuit according to the present invention.

FIG. 2 is a connection diagram showing a 1/2 frequency dividing circuit configured by a flip-flop circuit according to the present invention.

FIG. 3 is a connection diagram for explaining an inverter that constitutes a flip-flop circuit according to the present invention.

FIG. 4 is an input / output characteristic curve diagram for explaining the operation characteristic of the 1/2 frequency dividing circuit.

FIG. 5 is a characteristic curve diagram for explaining operating characteristics of the flip-flop circuit according to the present invention.

FIG. 6 is a connection diagram showing a configuration of a π / 4 phase shift shift modulation circuit.

FIG. 7 is a connection diagram showing a configuration of a PLL circuit.

FIG. 8 is a connection diagram showing a conventional master-slave flip-flop circuit.

FIG. 9 is a connection diagram showing a configuration of a NOR gate.

FIG. 10 is a connection diagram showing a conventional master / slave flip-flop circuit for high-speed operation.

FIG. 11 is a connection diagram showing a configuration of the inverter circuit.

FIG. 12 is a connection diagram showing a conventional master / slave type flip-flop circuit for low power consumption.

[Explanation of reference numerals] 40 ... Master / slave flip-flop circuit, 4
1,42 ...... latch circuit, 43 ...... 1/2 frequency divider, Q
41, Q42 ... Field effect transistor, C1, C2 ...
… Capacitors, I41, I42… Inverters,

Claims (1)

[Claims] 1. The input information is read into a first flip-flop circuit at the timing when a clock pulse rises, and the input information accumulated in the first flip-flop circuit is transferred to a second flip-flop circuit at a subsequent stage at the timing when a subsequent clock pulse falls. In the master-slave flip-flop circuit, the first and second flip-flop circuits store the first and second transfer gates, which are field effect transistors, and the input information read through the transfer gate. A first and a second capacitor which are connected to each other, and a direct connection type field effect transistor logic circuit, and the first and second outputs which invert the input information accumulated in the first and the second capacitors to a later stage and output the inverted information. A flip-flop circuit characterized by comprising an inverter.