JPH05218226A - Multilayer interconnection board - Google Patents
Multilayer interconnection boardInfo
- Publication number
- JPH05218226A JPH05218226A JP4047504A JP4750492A JPH05218226A JP H05218226 A JPH05218226 A JP H05218226A JP 4047504 A JP4047504 A JP 4047504A JP 4750492 A JP4750492 A JP 4750492A JP H05218226 A JPH05218226 A JP H05218226A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- heat dissipation
- multilayer wiring
- semiconductor chip
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 230000017525 heat dissipation Effects 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 18
- 239000011229 interlayer Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 8
- 230000005855 radiation Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は多層配線基板に関し、特
に、フリップチップ・ボンディング方法によって半導体
チップを搭載する多層配線基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board, and more particularly to a multilayer wiring board on which a semiconductor chip is mounted by a flip chip bonding method.
【０００２】[0002]
【従来の技術】半導体装置においては、半導体チップに
おいて発生する熱を発散する種々の方法が採られてい
る。代表的な例としては、半導体チップに直接放熱板を
接合する方法と、多層配線基板の半導体チップの下部に
ヴィアホールを形成するとともに、基板の裏面にヴィア
ホールとつながる放熱板を接合する２つの方法とがあ
る。一般的に、ワイヤーボンディングによって半導体チ
ップを実装する場合には前者の方法が採られる。一方、
フリップチップボンディングによる場合には後者の方法
（１９８７年１２月発行の「ＩＥＥＥ Transactions o
n Components, Hybrids, and Manufacturing Technolog
y 」の６４７頁に掲載）が採られている。2. Description of the Related Art In a semiconductor device, various methods for radiating heat generated in a semiconductor chip are adopted. As a typical example, there is a method of directly joining a heat sink to a semiconductor chip, and a method of forming a via hole under a semiconductor chip of a multilayer wiring board and joining a heat sink connected to the via hole to the back surface of the board. There is a method. Generally, in the case of mounting a semiconductor chip by wire bonding, the former method is adopted. on the other hand,
In the case of flip chip bonding, the latter method (see "IEEE Transactions" issued in December 1987) is used.
n Components, Hybrids, and Manufacturing Technolog
y ”on page 647).
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記の
ように多層配線基板の裏面に放熱板を接合する方法で
は、熱抵抗が大きく放熱効率が低いという問題点があっ
た。このような問題点は、配線層の数が増える程、顕著
になる。However, the method of joining the heat radiation plate to the back surface of the multilayer wiring board as described above has a problem that the heat resistance is large and the heat radiation efficiency is low. Such a problem becomes more remarkable as the number of wiring layers increases.
【０００４】[0004]
【発明の目的】本発明の目的は、放熱効率に優れた多層
配線基板を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a multilayer wiring board having excellent heat dissipation efficiency.
【０００５】[0005]
【課題を解決するための手段】本発明に係る多層配線基
板は、上記目的を達成するために、層間絶縁膜によって
各々絶縁された複数の配線層から成り、下面に放熱部材
を備え、表面に半導体チップをフリップチップ・ボンデ
ィングによって搭載する多層配線基板において、層間絶
縁膜中に放熱用ヴィアホールを形成するとともに、ヴィ
アホールと接続された金属プレートを、当該多層配線基
板表面及び配線層内に配置している。In order to achieve the above-mentioned object, a multilayer wiring board according to the present invention comprises a plurality of wiring layers each insulated by an interlayer insulating film, has a heat dissipation member on the lower surface, and has a heat dissipation member on the surface. In a multilayer wiring board on which a semiconductor chip is mounted by flip chip bonding, a heat dissipation via hole is formed in an interlayer insulating film, and a metal plate connected to the via hole is arranged on the surface of the multilayer wiring board and in the wiring layer. is doing.
【０００６】[0006]
【作用】本発明は上記のように構成しているため、半導
体チップで発生した熱はヴィアホールと金属板を伝播し
て放熱部材に達する。Since the present invention is configured as described above, the heat generated in the semiconductor chip propagates through the via hole and the metal plate and reaches the heat dissipation member.
【０００７】[0007]
【実施例】以下、本発明の実施例を添付図面を参照しつ
つ説明する。図１には、実施例に係る２層の配線基板の
構造が示されている。配線基板は、配線層１６ａ，１６
ｂと、２つの配線層１６ａ，１６ｂを絶縁する層間絶縁
層１２ａ，１２ｂと、Ｉ／Ｏピン１９と、ＡｌまたはＣ
ｕ製のフィン状放熱部材１８とから構成され、上面に半
導体チップ１１が半田バンプ２０によって実装されるよ
うになっている。Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows the structure of a two-layer wiring board according to an embodiment. The wiring board includes wiring layers 16a, 16
b, the interlayer insulating layers 12a and 12b for insulating the two wiring layers 16a and 16b, the I / O pin 19, and Al or C
It is composed of a fin-shaped heat dissipation member 18 made of u, and the semiconductor chip 11 is mounted on the upper surface by solder bumps 20.
【０００８】半導体チップ１１と配線層１６ａ、配線層
１６ａと１６ｂ間とは、各々配線用ヴィアホール１７
ａ，１７ｂによって電気的に接続されている。半導体チ
ップ１１の下部には金属プレート１３、配線層１６ａの
間には金属プレート１４ａ、配線層１６ｂの間には金属
プレート１４ｂがそれぞれ配置されている。そして、こ
れらの金属プレート１３，１４ａ，１４ｂは放熱用のヴ
ィアホール１５ａ，１５ｂによって接続されている。A wiring via hole 17 is provided between the semiconductor chip 11 and the wiring layer 16a and between the wiring layers 16a and 16b.
It is electrically connected by a and 17b. A metal plate 13 is disposed below the semiconductor chip 11, a metal plate 14a is disposed between the wiring layers 16a, and a metal plate 14b is disposed between the wiring layers 16b. The metal plates 13, 14a, 14b are connected by heat radiation via holes 15a, 15b.
【０００９】金属プレート１３，１４ａ，１４ｂは、厚
さ１〜１５μｍのＣｕ，Ａｌ，Ａｕ等若しくはこれらの
複合層である。ヴィアホール１５ａ，１５ｂは、径が１
０μｍ〜１５μｍの矩形または円形状に成形されてい
る。The metal plates 13, 14a, 14b are Cu, Al, Au or the like having a thickness of 1 to 15 μm or a composite layer thereof. The via holes 15a and 15b have a diameter of 1
It is formed in a rectangular or circular shape of 0 μm to 15 μm.
【００１０】以上のような構造の多層配線基板におい
て、半導体チップ１１で発生した熱は、放射作用によっ
て金属プレート１３に伝わる。金属プレート１３に吸収
された熱は、ヴィアホール１５ａ→金属プレート１４ａ
→ヴィアホール１５ｂ→金属プレート１４ｂ→放熱部材
１８という経路で外部に放熱される。In the multilayer wiring board having the above structure, the heat generated in the semiconductor chip 11 is transferred to the metal plate 13 by the radiation effect. The heat absorbed by the metal plate 13 is changed from the via hole 15a to the metal plate 14a.
-> Via hole 15b-> Metal plate 14b-> Heat dissipation member 18 radiates heat to the outside.
【００１１】図２には、本発明の他の実施例に係る多層
配線基板の構成が示されている。この実施例は、図１に
示した実施例を変形したものであり、半導体チップ１１
と多層配線基板との間に高熱伝導性物質２３を充填して
いる。このように構成することにより、半導体チップ１
１と金属プレート１３との間の熱抵抗が低下し、放熱効
率がより向上する。FIG. 2 shows the structure of a multilayer wiring board according to another embodiment of the present invention. This embodiment is a modification of the embodiment shown in FIG.
The high thermal conductive material 23 is filled between the substrate and the multilayer wiring board. With this configuration, the semiconductor chip 1
1, the thermal resistance between the metal plate 13 and the metal plate 13 is reduced, and the heat dissipation efficiency is further improved.
【００１２】[0012]
【発明の効果】以上説明したように本発明に係る多層配
線基板は、層間絶縁膜によって各々絶縁された複数の配
線層から成り、下面に放熱部材を備え、表面に半導体チ
ップをフリップチップ・ボンディングによって搭載する
多層配線基板において、層間絶縁膜中に放熱用ヴィアホ
ールを形成するとともに、ヴィアホールと接続された金
属プレートを、当該多層配線基板表面及び配線層内に配
置しているため、半導体チップの放熱効率が向上すると
いう効果がある。As described above, the multilayer wiring board according to the present invention comprises a plurality of wiring layers each insulated by an interlayer insulating film, has a heat dissipation member on the lower surface, and flip-chip-bonds a semiconductor chip on the surface. In the multilayer wiring board to be mounted by the semiconductor chip, the heat dissipation via hole is formed in the interlayer insulating film, and the metal plate connected to the via hole is arranged on the surface of the multilayer wiring board and in the wiring layer. There is an effect that the heat dissipation efficiency of is improved.
【図１】本発明の実施例に係る多層配線基板の構造を示
す断面図である。FIG. 1 is a sectional view showing a structure of a multilayer wiring board according to an embodiment of the present invention.
【図２】本発明の他の実施例に係る多層配線基板の構成
を示す側面図（一部断面）である。FIG. 2 is a side view (partial cross section) showing a configuration of a multilayer wiring board according to another embodiment of the present invention.
１１ 半導体チップ １２ａ，１２ｂ 層間絶縁層 １３，１４ａ，１４ｂ 金属プレート １５ａ，１５ｂ 放熱用ヴィアホール １６ａ，１６ｂ 配線層 １７ａ，１７ｂ 配線用ヴィアホール １８ 放熱部材 １９ Ｉ／Ｏピン ２０ 半田バンプ ２３ 高熱伝導性物質 11 semiconductor chips 12a, 12b interlayer insulating layers 13, 14a, 14b metal plates 15a, 15b heat dissipation via holes 16a, 16b wiring layers 17a, 17b wiring via holes 18 heat dissipation member 19 I / O pin 20 solder bump 23 high thermal conductivity material
Claims (2)
の配線層から成り、下面に放熱部材を備え、表面に半導
体チップをフリップチップ・ボンディングによって搭載
する多層配線基板において、 前記層間絶縁膜中に放熱用ヴィアホールを形成するとと
もに、 前記ヴィアホールと接続された金属プレートを、当該多
層配線基板表面及び前記配線層内に配置したことを特徴
とする多層配線基板。1. A multilayer wiring board comprising a plurality of wiring layers each insulated by an interlayer insulating film, having a heat dissipation member on the lower surface, and mounting a semiconductor chip on the surface by flip-chip bonding, wherein: A multilayer wiring board, wherein a heat dissipation via hole is formed, and a metal plate connected to the via hole is arranged on the surface of the multilayer wiring board and in the wiring layer.
と前記半導体チップとの間に高熱伝導性物質を充填して
成ることを特徴とする請求項１記載の多層配線基板。2. The multilayer wiring board according to claim 1, wherein a high thermal conductive material is filled between the metal plate and the semiconductor chip arranged on the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4047504A JPH05218226A (en) | 1992-02-03 | 1992-02-03 | Multilayer interconnection board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4047504A JPH05218226A (en) | 1992-02-03 | 1992-02-03 | Multilayer interconnection board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05218226A true JPH05218226A (en) | 1993-08-27 |
Family
ID=12776942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4047504A Pending JPH05218226A (en) | 1992-02-03 | 1992-02-03 | Multilayer interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05218226A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0982857A (en) * | 1995-09-18 | 1997-03-28 | Nec Corp | Multi-chip package structure |
| FR2745953A1 (en) * | 1996-03-06 | 1997-09-12 | Siemens Automotive Sa | Electronic Chip Heat Dissipation Method for Car Circuitry |
| JP2007096009A (en) * | 2005-09-29 | 2007-04-12 | Sanyo Electric Co Ltd | Laminated circuit substrate and portable electronic equipment with the same |
| US8823145B2 (en) | 2007-12-12 | 2014-09-02 | Lg Innotek Co., Ltd. | Multilayer board and light-emitting module having the same |
| JP2016009771A (en) * | 2014-06-25 | 2016-01-18 | 三菱電機株式会社 | Semiconductor device |
| JP2021163936A (en) * | 2020-04-03 | 2021-10-11 | 株式会社小糸製作所 | Printed circuit board |
-
1992
- 1992-02-03 JP JP4047504A patent/JPH05218226A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0982857A (en) * | 1995-09-18 | 1997-03-28 | Nec Corp | Multi-chip package structure |
| FR2745953A1 (en) * | 1996-03-06 | 1997-09-12 | Siemens Automotive Sa | Electronic Chip Heat Dissipation Method for Car Circuitry |
| JP2007096009A (en) * | 2005-09-29 | 2007-04-12 | Sanyo Electric Co Ltd | Laminated circuit substrate and portable electronic equipment with the same |
| US8823145B2 (en) | 2007-12-12 | 2014-09-02 | Lg Innotek Co., Ltd. | Multilayer board and light-emitting module having the same |
| KR101491138B1 (en) * | 2007-12-12 | 2015-02-09 | 엘지이노텍 주식회사 | Multi-layer substrate and light-emitting diode module |
| JP2016009771A (en) * | 2014-06-25 | 2016-01-18 | 三菱電機株式会社 | Semiconductor device |
| JP2021163936A (en) * | 2020-04-03 | 2021-10-11 | 株式会社小糸製作所 | Printed circuit board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6590282B1 (en) | Stacked semiconductor package formed on a substrate and method for fabrication | |
| TW201436130A (en) | Thermally enhanced wiring board with built-in heat sink and build-up circuitry | |
| KR20010104217A (en) | Semiconductor device, method of manufacture thereof, circuit board, and electronic device | |
| JP2004537849A (en) | Structure of leadless multi-die carrier and method for its preparation | |
| JPH09321073A (en) | Package for semiconductor device, and semiconductor device | |
| JP2006512775A5 (en) | ||
| US8153516B2 (en) | Method of ball grid array package construction with raised solder ball pads | |
| JPS6370498A (en) | Combination of ceramic substrate and radiator | |
| JP3603354B2 (en) | Hybrid integrated circuit device | |
| JP2803603B2 (en) | Multi-chip package structure | |
| JPH0573079B2 (en) | ||
| JPH05218226A (en) | Multilayer interconnection board | |
| JP2006295119A (en) | Multilayer semiconductor device | |
| JP2735912B2 (en) | Inverter device | |
| JP2003282778A (en) | Semiconductor device and printed wiring board | |
| JP2570645B2 (en) | Semiconductor device | |
| US20050258533A1 (en) | Semiconductor device mounting structure | |
| JP2004087700A (en) | Semiconductor device and its manufacturing method | |
| JPH10256428A (en) | Semiconductor package | |
| JPH10256413A (en) | Semiconductor package | |
| JPH11204565A (en) | Semiconductor device | |
| JPH10256414A (en) | Semiconductor package | |
| JP3965867B2 (en) | Semiconductor package | |
| JP3831173B2 (en) | Semiconductor module | |
| JP2656120B2 (en) | Manufacturing method of package for integrated circuit |