JPH05218223A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05218223A JPH05218223A JP4075692A JP4075692A JPH05218223A JP H05218223 A JPH05218223 A JP H05218223A JP 4075692 A JP4075692 A JP 4075692A JP 4075692 A JP4075692 A JP 4075692A JP H05218223 A JPH05218223 A JP H05218223A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chips
- fet
- chip carrier
- protrusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000003786 synthesis reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はマイクロ波無線通信用デ
バイスに関し、特にＦＥＴチップをチップキャリアを用
いて接地ボンディングする半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for microwave radio communication, and more particularly to a semiconductor device for grounding an FET chip using a chip carrier.
【０００２】[0002]
【従来の技術】従来のチップキャリアを用いた半導体装
置の一例を図２に示す。同図（ａ）は平面図、同図
（ｂ）はそのＢ−Ｂ線断面図である。金属で形成される
ヘッダ４上に基板１が搭載され、これら基板１間のヘッ
ダ４上にＦＥＴチップ２が搭載される。又、ＦＥＴチッ
プ２間にチップキャリア３Ａが搭載される。そして、Ｆ
ＥＴチップ２のゲートやドレインはワイヤ５を介して基
板１にボンディングされ、ソースはチップキャリア３Ａ
にワイヤ５でボンディングしている。このようにチップ
キャリア３Ａを設けてＦＥＴチップ２のソースをワイヤ
ボンディングすることでワイヤ５を短くし、高周波にお
けるワイヤ５のインダクタンスによる影響を少なくして
いる。2. Description of the Related Art An example of a conventional semiconductor device using a chip carrier is shown in FIG. The figure (a) is a top view and the figure (b) is the BB sectional drawing. The substrate 1 is mounted on the header 4 made of metal, and the FET chip 2 is mounted on the header 4 between the substrates 1. A chip carrier 3A is mounted between the FET chips 2. And F
The gate and drain of the ET chip 2 are bonded to the substrate 1 via the wire 5, and the source is the chip carrier 3A.
The wire 5 is used for bonding. In this way, the chip carrier 3A is provided and the source of the FET chip 2 is wire-bonded to shorten the wire 5, thereby reducing the influence of the inductance of the wire 5 at high frequencies.
【０００３】[0003]
【発明が解決しようとする課題】このような従来の半導
体装置では、チップキャリア３Ａは取扱いのためある程
度の大きさが必要であり、そのためＦＥＴチップ自体の
レイアウトの障害となる。図２の例ではチップキャリア
のために、２つのＦＥＴチップ２の間隔が大きくなり、
入出力のゲート、ドレインのワイヤ５の長さが均等にな
らず、合成効率が悪くなるという問題がある。又、ＦＥ
Ｔチップ２をそれぞれ個別にヘッダ４上に搭載すること
になるため、両ＦＥＴチップ２の位置にバラツキが生
じ、均一な電気特性が得られないこともある。本発明の
目的は、ＦＥＴチップの配置の自由度を高め、半導体装
置の電気的特性を改善した半導体装置を提供することに
ある。In such a conventional semiconductor device, the chip carrier 3A needs to have a certain size for handling, which hinders the layout of the FET chip itself. In the example of FIG. 2, because of the chip carrier, the distance between the two FET chips 2 becomes large,
There is a problem that the lengths of the input / output gate and drain wires 5 are not uniform and the synthesis efficiency is deteriorated. Also, FE
Since the T chips 2 are individually mounted on the header 4, variations may occur in the positions of the FET chips 2 and uniform electrical characteristics may not be obtained. An object of the present invention is to provide a semiconductor device in which the degree of freedom in arranging FET chips is increased and the electrical characteristics of the semiconductor device are improved.
【０００４】[0004]
【課題を解決するための手段】本発明は、ヘッダ上に搭
載したチップキャリアはその一部に突部を形成し、この
突部に隣接する位置にＦＥＴチップを搭載し、この突部
に対してＦＥＴチップをワイヤボンディングして接地を
行っている。例えば、チップキャリアの上面中央部分に
狭幅の突部を設け、この突部の両側の平坦面上にそれぞ
れＦＥＴチップを搭載し、ＦＥＴチップのソースを突部
にワイヤボンディングする。According to the present invention, a chip carrier mounted on a header has a protrusion formed on a part thereof, and an FET chip is mounted on a position adjacent to the protrusion, and the chip is mounted on the protrusion. The FET chip is wire-bonded for grounding. For example, a narrow-width protrusion is provided at the center of the upper surface of the chip carrier, FET chips are mounted on the flat surfaces on both sides of the protrusion, and the source of the FET chip is wire-bonded to the protrusion.
【０００５】[0005]
【作用】チップキャリアを取扱い可能な大きさに形成し
ても、チップキャリア上にＦＥＴチップを搭載し、かつ
チップキャリアに設けた突部に対してワイヤボンディン
グすることで、ＦＥＴチップの搭載間隔を狭め、かつＦ
ＥＴチップの搭載位置を規定する。[Effect] Even if the chip carrier is formed in a size that can be handled, by mounting the FET chip on the chip carrier and wire-bonding to the protrusion provided on the chip carrier, the mounting intervals of the FET chips can be increased. Narrow and F
Specify the mounting position of the ET chip.
【０００６】[0006]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明のチップキャリアを用いた半導体装置
の一実施例を示し、同図（ａ）は平面図、同図（ｂ）は
Ａ−Ａ線断面図である。ヘッダ４上に基板１とチップキ
ャリア３を搭載し、このチップキャリア３上にＦＥＴチ
ップ２を搭載している。チップキャリア３は中央部分に
突部３ａを有し、その両側を平坦にした形状とする。そ
して、この突部３ａを挟む両側平坦面上にそれぞれＦＥ
Ｔチップ２を搭載し、これらＦＥＴチップ２のソースを
突部３ａにワイヤ５をボンディングしてグランドに電気
接続している。又、ＦＥＴチップ２のゲート、ドレイン
はワイヤ５で基板１にボンディングしている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A and 1B show an embodiment of a semiconductor device using a chip carrier of the present invention. FIG. 1A is a plan view and FIG. 1B is a sectional view taken along the line AA. The substrate 1 and the chip carrier 3 are mounted on the header 4, and the FET chip 2 is mounted on the chip carrier 3. The chip carrier 3 has a protrusion 3a at the center and is flattened on both sides. Then, the FE is provided on each of the flat surfaces on both sides of the protrusion 3a.
The T chip 2 is mounted, and the sources of these FET chips 2 are electrically connected to the ground by bonding the wire 5 to the protrusion 3a. The gate and drain of the FET chip 2 are bonded to the substrate 1 with wires 5.
【０００７】この構成によれば、チップキャリア３は取
扱いが可能な大きさに形成する一方で、突部３ａをワイ
ヤボンディングが可能な範囲で狭幅に形成することがで
き、チップキャリア３上に搭載する２つのＦＥＴチップ
２の間隔を小さくすることができる。これにより、ＦＥ
Ｔチップ２に対する入出力（ゲート、ドレイン）のワイ
ヤ５の偏りを解消し、２つのＦＥＴチップの合成効率が
改善される。又、チップキャリア３によってＦＥＴチッ
プ２の搭載位置を規定することができ、ＦＥＴチップ位
置のバラツキを抑制し、電気特性を改善することができ
る。According to this structure, the chip carrier 3 can be formed in a size that can be handled, while the protrusion 3a can be formed in a narrow width within a range in which wire bonding can be performed. The distance between the two mounted FET chips 2 can be reduced. This allows FE
The bias of the input / output (gate, drain) wires 5 with respect to the T chip 2 is eliminated, and the synthesis efficiency of the two FET chips is improved. Further, the mounting position of the FET chip 2 can be defined by the chip carrier 3, the variation in the FET chip position can be suppressed, and the electrical characteristics can be improved.
【０００８】[0008]
【発明の効果】以上説明したように本発明は、突部を設
けたチップキャリアにＦＥＴチップを搭載し、この突部
に対して接地のワイヤボンディングを行なうので、ＦＥ
Ｔチップの搭載位置を規定し、位置のバラツキを防止し
て電気特性を改善する。又、突部を狭幅に形成し、その
両側に２つのＦＥＴチップを搭載することで、両ＦＥＴ
チップの間隔を小さくでき、入出力ワイヤを均一化して
合成効率を改善することができる効果がある。As described above, according to the present invention, the FET chip is mounted on the chip carrier provided with the protrusion, and the wire is grounded to the protrusion.
The mounting position of the T-chip is specified to prevent the positional variation and improve the electrical characteristics. Also, by forming a narrow protrusion and mounting two FET chips on both sides, both FETs
There is an effect that the interval between chips can be reduced, the input / output wires can be made uniform, and the synthesis efficiency can be improved.
【図１】本発明の半導体装置の一実施例を示し、（ａ）
は平面図、（ｂ）はそのＡ−Ａ線断面図である。FIG. 1 shows an embodiment of a semiconductor device of the present invention, (a)
Is a plan view and (b) is a sectional view taken along line AA.
【図２】従来の半導体装置の一例を示し、（ａ）は平面
図、（ｂ）はそのＢ−Ｂ線断面図である。2A and 2B show an example of a conventional semiconductor device, FIG. 2A is a plan view, and FIG. 2B is a sectional view taken along line BB.
１ 基板 ２ ＦＥＴチップ ３ チップキャリア ４ ヘッダ ５ ワイヤ 1 substrate 2 FET chip 3 chip carrier 4 header 5 wire
Claims (2)
し、このＦＥＴチップを前記基板に対してワイヤボンデ
ィングするとともに、前記ヘッダ上に搭載したチップキ
ャリアにワイヤボンディングして接地を行うようにした
半導体装置において、前記チップキャリアはその一部に
突部を形成し、この突部に隣接する位置に前記ＦＥＴチ
ップを搭載し、かつ前記突部に対してＦＥＴチップをワ
イヤボンディングして接地を行うことを特徴とする半導
体装置。1. A semiconductor in which a substrate and an FET chip are mounted on a header, the FET chip is wire-bonded to the substrate, and the chip carrier mounted on the header is wire-bonded to ground. In the device, the chip carrier has a protrusion formed on a part thereof, the FET chip is mounted at a position adjacent to the protrusion, and the FET chip is wire-bonded to the protrusion to perform grounding. A semiconductor device characterized by:
突部を設け、この突部の両側の平坦面上にそれぞれＦＥ
Ｔチップを搭載し、ＦＥＴチップのソースを前記突部に
ワイヤボンディングしてなる請求項１の半導体装置。2. The chip carrier is provided with a narrow protrusion in the central portion of the upper surface thereof, and FEs are provided on flat surfaces on both sides of the protrusion, respectively.
The semiconductor device according to claim 1, wherein a T-chip is mounted, and the source of the FET chip is wire-bonded to the protrusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4075692A JPH05218223A (en) | 1992-01-31 | 1992-01-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4075692A JPH05218223A (en) | 1992-01-31 | 1992-01-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05218223A true JPH05218223A (en) | 1993-08-27 |
Family
ID=12589473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4075692A Pending JPH05218223A (en) | 1992-01-31 | 1992-01-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05218223A (en) |
-
1992
- 1992-01-31 JP JP4075692A patent/JPH05218223A/en active Pending
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