JPH05217376A - Amplifier - Google Patents

Abstract

PURPOSE:To shorten operating time in which an output voltage is fixed to the L level by setting potential of first and second connecting nodes at the time of non-operation to the intermediate potential between each potential which is generated at the first and the second potential nodes at the time of operation. CONSTITUTION:When the IN 3 is L level at the operation starting point P1, since the IN inverted signal 4 is H level, the transistor Tr3 becomes ON state and the transistor Tr4 becomes OFF state. Therefore, since potential of the second connecting node is charged via the transistor Tr2, Tr1 becomes OFF state. Also, since the Tr3 is ON state, the output voltage V becomes GND level from the intermediate potential Vc/2. Operating time required to change output voltage V to L level is expressed with time from the operation starting point P1 to the fixed point P4' and is the same as the case of change of H level, operating time to L level is shortened. Therefore, an amplifier which realizes high speed L level operation can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of an amplifier used as, for example, a current mirror type sense amplifier, and particularly to an amplifier which realizes high speed by shortening the time from the operation start point to the L level output signal fixed point. It is about.

[0002]

2. Description of the Related Art FIG. 6 is a circuit diagram showing a conventional current mirror type sense amplifier (amplifier). This kind of amplifier
For example, it is used as a sense amplifier for differentially amplifying the potentials of a pair of bit lines in a DRAM and transmitting it to a pair of I / O lines. In the figure, Tr1 and Tr2 are P
Type transistors (first and second transistors), and their sources are connected to the power supply node Vcc to which the power supply voltage Vc is applied. The control electrodes (gates) of the transistors Tr1 and Tr2 are connected to each other, and the connection node is connected to the drain of the transistor Tr2.

Tr3 and Tr4 are N-type transistors (first
And a second input transistor), the drains of which are connected to the drains of the transistors Tr1 and Tr2. Tr5 is an N-type transistor, the drain is connected to the sources of the transistors Tr3 and Tr4, and the source is connected to the ground GND.

Tr6 is an N-type transistor inserted between the drains of the transistors Tr1 and Tr2, and Tr7 is a P-type transistor inserted between the drains of the transistors Tr1 and Tr2 like Tr6. These transistors Tr6 and Tr7 serve as a transistor Tr3 when the amplifier is not operating.
And the drain potentials of Tr4 are equalized.

Reference numeral 1 is a preamplifier enable signal (hereinafter referred to as PAE) for putting the amplifier into an operating state, which is applied to the gates of the transistors Tr5 and Tr7. 2 is a PAE inversion signal applied to the gate of the transistor Tr6, 3
Is an input signal applied to the gate of the transistor Tr4 (hereinafter referred to as IN), 4 is an IN inverted signal applied to the gate of the transistor Tr3, and 5 is the transistors Tr1 and Tr3.
Is an output signal (hereinafter, referred to as OUT) drawn from a connection node (first connection node) C1 of. The IN inverted signal 4 serves as a first input signal for controlling the first input transistor Tr3, and IN3 serves as a second input signal for controlling the second input transistor Tr4.

Here, from the first connection node C1 to OUT
Although the case of pulling out 5 is shown, the transistors Tr2 and T2
OUT5 can also be derived from the connection node of r4, the second connection node C2. E1 is a node that connects the sources of the first and second transistors Tr1 and Tr2, and is a first potential node related to the power supply node Vcc. E2 is the first and second input transistors Tr3 and Tr4
And a second potential node related to the ground GND.

FIG. 7 shows a PAE operation of the amplifier shown in FIG.
3 is a timing chart for explaining together with the waveforms of IN and IN, the horizontal axis represents time t, and the vertical axis represents the output voltage V of OUT5.
Is. Also, the solid line shows the case where IN3 is H level (H level read) during operation, and the alternate long and short dash line shows the case where IN3 is L level (L level read) during operation. Usually IN
3 (IN inversion signal 4) is not desirable to be delayed from the output timing of PAE1 (PAE inversion signal 2).
The output timing of 3 (IN inversion signal 4) is set earlier than PAE1 (PAE inversion signal 2) as shown in the figure.

In FIG. 7, a period T from time t0 to t1
o is a non-operation period of the amplifier, t1 is an operation start time, P1 is an operation start point corresponding to the operation start time t1, P2 is a fixed point of the H level output signal 5, t2 is a fixed time corresponding to the fixed point P2, P3
Is a fixed point of the L level output signal 5, t3 is a fixed time corresponding to the fixed point P3, Vc is a power supply voltage, and Vthn is an N-channel threshold voltage between the sources and gates of the transistors Tr1 and Tr2.

Next, the operation of the conventional amplifier shown in FIG. 6 will be described with reference to FIG. First, when the PAE1 is at the L level and the PAE inversion signal 2 is at the H level during non-operation, the transistor Tr5 is in the off state, and
r6 and Tr7 are on. Therefore, regardless of the ON / OFF state of the transistors Tr3 and Tr4 based on the levels of IN3 and IN inverted signal 4, OUT5 of the amplifier
Is separated from the ground GND.

At this time, as the output voltage V of OUT5,
Although the drain potential of the transistor Tr1 appears, the potential of the drain and gate of Tr2 becomes (Vc-Vthp) because the transistor Tr2 is diode-connected. Here, Vthp is a P-channel threshold voltage between the sources and gates of the transistors Tr1 and Tr2. Also, since the gates of the transistors Tr1 and Tr2 are connected to each other,
The drain potential of the transistor Tr1 also becomes (Vc-Vthp).

At this time, the drain potentials of the transistors Tr1 and Tr2 are equalized by the transistors Tr6 and Tr7. Therefore, as shown in FIG. 7, the non-operation period To
Is a value (Vc-V) obtained by subtracting the threshold voltages Vthp of the transistors Tr1 and Tr2 from the power supply voltage Vc.
thp).

Next, at time t1, the operation is started and P
When AE1 becomes H level, PAE inversion signal 2 becomes L level, transistor Tr5 is turned on, and Tr6 and Tr7 are turned on.
Turns off. Here, as indicated by the solid line in FIG. 7, when IN3 is at H level and IN inverted signal 4 is at L level, the transistor Tr3 is turned off and Tr4 is turned on, so that the gate potential of the transistor Tr2 becomes ( Vc-Vt
hp) is pulled to the ground GND, and the transistor Tr1 is turned on. Therefore, the drain potential of the transistor Tr1, that is, the output voltage V changes from (Vc-Vthp) to the power supply voltage Vc. At this time, the time required to change the output voltage V to the H level is the time from the operation start point P1 to the fixed point P2 (t2-t
It becomes 1).

On the other hand, at the operation start time t1, when IN3 is at L level and IN inverted signal 4 is at H level, the transistor Tr4 is off and Tr3 is on. At this time, since the transistor Tr4 is turned off,
The gate potential of the transistor Tr1 is the gate potential of Tr2 (Vc
-Vthp), the transistor Tr1 remains in the off state. Therefore, the output voltage V of OUT5 changes from (Vc-Vthp) to GN by the transistor Tr3 in the ON state.
It is pulled to D level and becomes 0V. Output voltage V at this time
Takes a time (t3-t1) from the operation start point P1 to the fixed point P3, and is longer than the time (t2-t1) required to change to the H level.

[0014]

As described above, in the conventional amplifier, the output voltage V during the non-operating period To is the power supply voltage Vc.
And the voltage (Vc-Vthp) based on the threshold voltage Vthp is set. Therefore, when IN1 is at L level and the output voltage V is pulled to GND level at the operation start time t1, the output voltage V It takes a long time to be fixed. Therefore, there is a problem in that the L-level read operation cannot be speeded up.

The present invention has been made in order to solve the above problems, and it is an object of the present invention to obtain an amplifier which realizes high speed L level operation by shortening the operation time when the input signal is at L level. To aim.

[0016]

An amplifier according to the present invention is inserted between first and second connection nodes from which an output signal is drawn from at least one side, and a first potential node and a first connection node. The first transistor and the first transistor
Between the second potential node and the first connection node inserted between the second potential node and the second connection node, the control electrode being connected to the control electrode of the first transistor. A first input transistor that is inserted into the control electrode to which the first input signal is applied and a second potential node that is inserted between the second potential node and the second connection node.
Second input transistor to which the input signal is applied, and the potentials of the first and second connection nodes in non-operation are set to be intermediate between the respective potentials appearing in the first and second potential nodes in operation. And an intermediate potential setting means.

[0017]

In the present invention, when the output voltage at the time of non-operation, that is, the operation start point is set to the intermediate potential of each output voltage during operation, the change of the output voltage to the power supply voltage (H level) and the ground potential ( The operation time required to change to the L level) is made substantially equal, and the operation time until the L level is fixed is shortened.

[0018]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 is a circuit diagram showing a first embodiment of the present invention,
Vcc, GND, C1, C2, E1, E2, Tr1 to Tr7 and 1 to 5
Is the same as described above.

Vcc 'is an intermediate power supply node connected to the intermediate power supply, and an intermediate potential (Vc / 2) obtained by dividing the power supply voltage Vc into 1/2 by a resistor or the like is applied. Tr8 is an N-type transistor inserted between the intermediate power supply node Vcc 'and the connection node C1 (OUT5 output node), the drain is connected to the intermediate power supply node Vcc', and the source is connected to the drain of the transistor Tr1. Has been done. The transistor Tr8 has a gate to which the PAE inversion signal 2 is applied, and constitutes a first switching means which is turned on when the amplifier is not operating and is turned off when the amplifier is operating.

The intermediate power supply connected to the intermediate power supply node Vcc 'and the transistors Tr8, Tr6, and Tr7 control the potentials of the first and second connection nodes C1 and C2 when the amplifier is not operating and the first and second connection nodes C1 and C2 when operating. It constitutes an intermediate potential setting means for setting the potential Vc appearing at the two potential nodes E1 and E2 to the middle of each potential Vc and 0.

Tr9 is a power supply node Vcc and a transistor Tr1.
, And Tr2, the source is connected to the power supply node Vcc, and the drain is connected to the sources of the transistors Tr1 and Tr2. The PAE inversion signal 2 is applied to the gate of the transistor Tr9, and constitutes the second switching means which is turned off when not operating and is turned on when operating.

FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention shown in FIG.
t1, To, P1 and Vc are the same as described above. or,
Although not particularly shown in FIG. 2, each waveform of PAE and IN is as shown in FIG. Vc / 2 is the output voltage V when not operating, P4 is a fixed point when the output voltage V changes to the power supply voltage Vc (H level), and P4 'is the output voltage V at the GND level (L level).
Fixed point when changing to (Level), t4 is each fixed point P4 and P
It is a fixed time corresponding to 4 '.

Next, the operation of the first embodiment of the present invention shown in FIG. 1 will be described with reference to FIG. First, when not operating, PAE1 is at L level as described above.
(Ground potential), the transistor Tr5 is off, and Tr7
Turns on. Also, the PAE inversion signal 2 is at H level
Since it is (power supply voltage Vc), the transistors Tr6 and Tr8 are
Turns on and Tr9 turns off.

Therefore, the transistors Tr1 and Tr2 are separated from the power supply node Vcc and connected to the intermediate power supply node Vcc ', and the output voltage V appearing at the output node, that is, the first connection node C1 is at the intermediate potential via the transistor Tr8. (V
c / 2). This output voltage V (= Vc / 2) is also applied to the gate of the transistor Tr1 via the transistors Tr6 and Tr7 and the second connection node C2.

Next, when the operation starts at time t1,
Since the PAE1 is at the H level and the PAE inversion signal 2 is at the L level, the transistor Tr5 is in the on state, Tr6 and Tr7 are in the off state, and the transistor Tr8 is in the off state, T
r9 turns on. Therefore, the intermediate power supply node Vcc '
Is disconnected from the first connection node C1 serving as an output node, and the power supply voltage Vc applied to the power supply node Vcc is
The first potential node E1 appears at the sources of the transistors Tr1 and Tr2.

At this time, if IN3 is at the H level, the transistor Tr4 is turned on, the gate potential of the transistor Tr1 is pulled to the GND level and the transistor Tr1 is turned on, so that the potential appearing at the first connection node C1. That is, the output voltage V changes from the intermediate potential Vc / 2 to the power supply voltage Vc. At this time, the operation time required to change the output voltage V to the H level is the time from the operation start point P1 to the fixed point P4 (t
4-t1).

On the other hand, if IN3 is L level at the operation starting point P1, the IN inversion signal 4 is H level,
The transistor Tr3 is turned on and Tr4 is turned off.
Therefore, the potential of the second connection node C2 is charged through the transistor Tr2 until it reaches (Vc-Vthp).
The gate potential of the transistor Tr1 is from Vc / 2 before operation.
(Vc-Vthp), and Tr1 is turned off. Further, since the transistor Tr3 is on, the output voltage V is Vc
It becomes GND level from / 2.

The operating time required to change the output voltage V to the L level at this time is represented by the time (t4'-t1) from the operation starting point P1 to the fixed point P4 ', and the fixed time t4' is t4. Is the same as the case of changing to the H level, and the operation time to the L level is shorter than in the conventional case.

Generally, since the discharge time to the L level is faster than the charge time to the H level, the operating time (t4'-t1) is
Although it may be shorter than (t4-t1), the operating time depends on the operating characteristics of each of the transistors Tr1 to Tr9. ) Can be considered approximately equal.

Example 2. In the first embodiment, the N-type transistor Tr8 is used as the first switching means for setting the output voltage V at the time of non-operation to Vc / 2, and the PAE inversion signal 2 is applied to the gate. Like 3, P
-Type transistor Tr8 'is used with its gate
1 may be applied.

Example 3. Further, a P-type transistor Tr9 is used as the second switching means for cutting off the through current due to the power supply voltage Vc when it is not operating, and the PAE is used for the gate.
Although the inverted signal 2 is applied, the PAE1 may be applied to its gate by using an N-type transistor Tr9 'as shown in FIG.

Example 4. Furthermore, although the case of a single amplifier is shown, it is needless to say that the same effect can be obtained when a plurality of similar amplifiers are used. FIG. 5 is a block diagram showing a case where three current mirror type sense amplifiers (amplifiers) 10 to 12 are used, and the first stage amplifiers arranged in parallel.
The output signals 10 and 11 are the IN3 'and IN inverted signal 4'of the second-stage amplifier 12, respectively. Usually, a multi-stage configuration as shown in FIG. 5 is often used as the sense amplifier. In this case, the operation time is overlapped, so that the effect of speeding up the L level operation becomes more remarkable.

That is, since the time from the start of operation of the first-stage amplifiers 10 and 11 until each output voltage is fixed at the L level becomes short, the output voltage is set to IN3 'and IN inverted signal 4'. The final L-level operation time of OUT5 of the second-stage amplifier 12 is also shortened. In this way, since the operation time to the H level and the L level according to the level of IN3 becomes equal, the imbalance of the operation time as in the conventional case does not occur, and the speedup of the L level operation is realized.

Although the intermediate potential is set to Vc / 2 in the first to third embodiments, it is not strictly limited to Vc / 2 and may be set to about Vc / 2. Furthermore, the application of the amplifier according to the present invention is not limited to the current mirror type sense amplifier for transmitting DRAM information, but can be applied to various applications.

[0035]

As described above, according to the present invention, it is inserted between the first and second connection nodes from which an output signal is derived from at least one, and the first potential node and the first connection node. A first transistor, a second transistor inserted between the first potential node and the second connection node and having a control electrode connected to the control electrode of the first transistor, and a second potential node And a first connection node between the first connection node and a first input signal to which a first input signal is applied to the control electrode, and a second potential node and a second connection node. The second input transistor to which the second input signal is applied to the control electrode, and the potentials of the first and second connection nodes in the non-operating state are intermediate between the potentials appearing in the first and second potential nodes in the operating state. Intermediate potential setting for setting Since the operating time required to change the output voltage to the H level and the L level is made substantially equal to each other, the operating time until the output voltage is fixed to the L level is shortened to realize the high speed operation of the L level. There is an effect that can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a conventional amplifier.

FIG. 7 is a timing chart for explaining the operation of the conventional amplifier.

[Explanation of symbols]

 3 2nd input signal 4 1st input signal 5 Output signal 10-12 Current mirror type sense amplifier C1 1st connection node C2 2nd connection node E1 1st electric potential node E2 2nd electric potential node GND ground P1 Operation start point P4, P4 'Fixed point Tr1 First transistor Tr2 Second transistor Tr3 First input transistor Tr4 Second input transistor Tr8 First switching means Tr9 Second switching means To Non-operation period Vcc Power supply node Vcc 'Intermediate power supply node Vc Power supply voltage Vc / 2 Intermediate potential V Output voltage

[Procedure amendment]

[Submission date] April 19, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art FIG . 5 is a circuit diagram showing a conventional current mirror type sense amplifier (amplifier). This kind of amplifier
For example, it is used as a sense amplifier for differentially amplifying the potentials of a pair of bit lines in a DRAM and transmitting it to a pair of I / O lines. In the figure, Tr1 and Tr2 are P
Type transistors (first and second transistors), and their sources are connected to the power supply node Vcc to which the power supply voltage Vc is applied. The control electrodes (gates) of the transistors Tr1 and Tr2 are connected to each other, and the connection node is connected to the drain of the transistor Tr2.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

FIG . 6 shows a PAE operation of the amplifier shown in FIG.
3 is a timing chart for explaining together with the waveforms of IN and IN, the horizontal axis represents time t, and the vertical axis represents the output voltage V of OUT5.
Is. Also, the solid line shows the case where IN3 is H level (H level read) during operation, and the alternate long and short dash line shows the case where IN3 is L level (L level read) during operation. Usually IN
3 (IN inversion signal 4) is not desirable to be delayed from the output timing of PAE1 (PAE inversion signal 2).
The output timing of 3 (IN inversion signal 4) is set earlier than PAE1 (PAE inversion signal 2) as shown in the figure.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

In FIG . 6 , a period T from time t0 to t1
o is a non-operation period of the amplifier, t1 is an operation start time, P1 is an operation start point corresponding to the operation start time t1, P2 is a fixed point of the H level output signal 5, t2 is a fixed time corresponding to the fixed point P2, P3
Is a fixed point of the L level output signal 5, t3 is a fixed time corresponding to the fixed point P3, Vc is a power supply voltage, and Vthp is a P-channel threshold voltage between the sources and gates of the transistors Tr1 and Tr2.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

[0009] Next, referring to FIG. 6, the operation of the conventional amplifier is described as shown in FIG. First, when the PAE1 is at the L level and the PAE inversion signal 2 is at the H level during non-operation, the transistor Tr5 is in the off state, and
r6 and Tr7 are on. Therefore, regardless of the ON / OFF state of the transistors Tr3 and Tr4 based on the levels of IN3 and IN inverted signal 4, OUT5 of the amplifier
Is separated from the ground GND.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

At this time, the drain potentials of the transistors Tr1 and Tr2 are equalized by the transistors Tr6 and Tr7. Therefore, as shown in FIG. 6 , the non-operation period To
Is a value (Vc-V) obtained by subtracting the threshold voltages Vthp of the transistors Tr1 and Tr2 from the power supply voltage Vc.
thp).

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

Next, at time t1, the operation is started and P
When AE1 becomes H level, PAE inversion signal 2 becomes L level, transistor Tr5 is turned on, and Tr6 and Tr7 are turned on.
Turns off. Here, as indicated by the solid line in FIG. 6 , when IN3 is at the H level and IN inverted signal 4 is at the L level, the transistor Tr3 is in the OFF state and Tr4 is in the ON state, so that the gate potential of the transistor Tr2 is ( Vc-Vt
hp) is pulled to the ground GND, and the transistor Tr1 is turned on. Therefore, the drain potential of the transistor Tr1, that is, the output voltage V changes from (Vc-Vthp) to the power supply voltage Vc. At this time, the time required to change the output voltage V to the H level is the time from the operation start point P1 to the fixed point P2 (t2-t
It becomes 1).

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention shown in FIG.
t1, To, P1 and Vc are the same as described above. or,
Although not shown in particular in FIG. 2, each waveform of PAE and IN is shown in the figure.
As shown in FIG. Vc / 2 is the output voltage V when not operating, P4 is a fixed point when the output voltage V changes to the power supply voltage Vc (H level), and P4 'is the output voltage V at the GND level (L level).
Fixed point when changing to (Level), t4 is each fixed point P4 and P
It is a fixed time corresponding to 4 '.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Delete

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

Example 3 Further, although the case of a single amplifier is shown, it is needless to say that the same effect can be obtained when a plurality of similar amplifiers are used. FIG. 4 is a block diagram showing a case where three current mirror type sense amplifiers (amplifiers) 10 to 12 are used, and the first stage amplifiers arranged in parallel.
The output signals 10 and 11 are the IN3 'and IN inverted signal 4'of the second-stage amplifier 12, respectively. Usually, a multi-stage configuration as shown in FIG. 4 is often used as the sense amplifier . In this case, the operation time is overlapped, so that the effect of speeding up the L level operation becomes more remarkable.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional amplifier .

FIG. 6 is a timing diagram for explaining the operation of a conventional amplifier .
It is a chart .

[Description of Reference Signs] 3 Second input signal 4 First input signal 5 Output signal 10-12 Current mirror type sense amplifier C1 First connection node C2 Second connection node E1 First potential node E2 Second Potential node GND ground P1 operation start point P4, P4 'fixed point Tr1 first transistor Tr2 second transistor Tr3 first input transistor Tr4 second input transistor Tr8 first switching means Tr9 second switching means To non Operating period Vcc power supply node Vcc 'intermediate power supply node Vc power supply voltage Vc / 2 intermediate potential V output voltage

[Procedure Amendment 11]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

[Procedure Amendment 12]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure Amendment 13]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

Claims (1)

[Claims] 1. A first and a second connection node from which an output signal is drawn from at least one side, a first transistor inserted between a first potential node and the first connection node, and the first and second connection nodes. A second transistor inserted between the first potential node and the second connection node and having a control electrode connected to the control electrode of the first transistor; a second potential node and the first connection; A first input transistor inserted between the control electrode and a first input signal to the control electrode; and a control electrode inserted between the second potential node and the second connection node. A second to which a second input signal is applied
An input transistor, and an intermediate potential setting means for setting the potentials of the first and second connection nodes during non-operation to an intermediate level between the potentials appearing on the first and second potential nodes during operation, With an amplifier.