JPH05211777A - Inverter device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] It is possible to reduce the fluctuation of the output voltage due to the difference in the power factor of the load, and in particular, to greatly reduce the fluctuation of the output voltage due to the phase-advancing load that changes in the direction of increasing the output voltage. To provide an inverter device. A sine wave output circuit detects an output current of AC power by a current detection circuit, and a power factor correction circuit (26) advances the phase of the detection current detected by the current detection circuit by about 90 °. Since the amplitude of this sine wave reference signal is corrected by feeding back to the sine wave reference signal output from, the voltage fluctuation due to the fluctuation of the load power factor can be greatly reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device,
In particular, the present invention relates to a pulse width modulation type inverter device used in a portable AC power supply device or the like.

[0002]

2. Description of the Related Art In recent years, an inverter device has been increasingly used in a portable AC power supply device in order to stabilize the output frequency. For example, an AC generator driven by an engine supplies a commercial frequency power supply. In a portable power supply device that outputs AC power, a high-power AC current is obtained from a generator by operating the engine in a high rotation speed region, this AC current is once converted to DC, and then commercialized by an inverter device. A device adapted to convert the frequency into an alternating current and output the alternating current is known from Japanese Utility Model Application Laid-Open No. Sho 59-132398.

By the way, in such an AC power supply device, there is a demand for the output waveform to be as close to a sine wave as possible depending on the application, and in order to meet this demand, the inverter device is subjected to pulse width modulation (PW).
An AC power supply device adopting the M) system has also been studied (Japanese Patent Laid-Open No. 82098/60).

[0004]

By the way, in the AC power supply device of this kind, even if the output currents of the same magnitude are output depending on the power factor of the load (cos φ; φ is the phase difference between the voltage and the current). The voltage fluctuates greatly.

An example of comparing the degree of fluctuation of the output voltage with the output voltage when no load is applied is shown by an example of data measured by the applicant of the present invention for a pulse modulation type AC power supply device. ± 6.6% depending on the load power factor, such as −6.6% for the load, −11.0% for the delayed load (cos φ = 0.4), and + 9.7% for the advanced load (cos φ = 2.5). % Will also fluctuate.

This can be explained as follows.

That is, the internal output voltage of the AC power supply device is V0 [V], the load voltage is V [V], the choke inductance of the output stage of the AC power supply device is L [H], and the load current is I.
[A], the load impedance is Z [Ω], and the angular velocity of the output voltage is ω, the output voltage V0 is V0 = | ωL + Z | · I, and the load current I is I = V / | Z | , The above equation can be expressed as V0 = | ωL + Z | · V / | Z |, and therefore the load voltage V can be expressed as V = V0 · | Z / (ωL + Z) |.

If .vertline.Z / (. Omega.L + Z) .vertline. = A, then A <1 and V <V for the resistance load and the delay load.
It becomes 0, but with the advance load, | ωL + Z | decreases and
A> 1 and V> V0. From this, it can be seen that the output voltage rises in the phase advance load.

Such fluctuations in the output voltage are not desirable, and it is desirable to keep the fluctuation range as small as possible. Further, the fluctuation in the direction in which the output voltage rises is likely to cause a failure both to the load and to the power supply device side itself, so it is preferable to make it particularly small.

The present invention has been made under such circumstances, and can reduce the fluctuation of the output voltage due to the difference in the power factor of the load, and in particular, the fluctuation of the output voltage due to the phase-advancing load changing in the direction of increasing the output voltage. It is an object of the present invention to provide an inverter device that can be significantly reduced.

[0011]

In order to achieve the above object, the present invention provides a DC power supply circuit, an inverter circuit for switching control of the output of the DC power supply circuit, and a sine wave for outputting a sine wave reference signal of a predetermined frequency. A wave output circuit, a pulse width modulation circuit for pulse-width modulating the sine wave reference signal output from the sine wave output circuit to output a PWM signal, and a PWM signal output from the pulse width modulation circuit In an inverter device having a switching control circuit that forms alternating current power of the predetermined frequency by performing a switching operation of the inverter circuit, a current detection circuit that detects an output current of the alternating current power and a current detection circuit that detects the current. The phase of the detected current is advanced by about 90 ° and is fed back to the sine wave reference signal to generate a sine wave reference signal. It is characterized in the provision of the power factor correction circuit for correcting the amplitude of the signal.

Preferably, a switching circuit for switching the output frequency of the AC power and a feedback gain of the power factor correction circuit are increased so that the output frequency can be switched to a higher frequency by the switching circuit. The power factor correction circuit is provided with a feedback gain changing circuit for advancing the phase of the detected current by approximately 90 °.

Further, the switching circuit can switch the output frequency between 50 hertz and 60 hertz, and the feedback gain changing circuit changes the feedback gain of the power factor correction circuit when the output frequency is 50 hertz. It is characterized in that it is controlled to be higher in the case of 60 hertz than in the case of 60 Hz.

[0014]

In the inverter device according to the present invention, the output current of the AC power formed by the switching control circuit is detected by the current detection circuit, and the phase of the detection current detected by the current detection circuit is detected by the power factor correction circuit. About 90
The phase of the sine wave reference signal is advanced and fed back to the sine wave reference signal to correct the amplitude of the sine wave reference signal.

As a result, it is possible to reduce the fluctuation of the output voltage due to the difference in the power factor of the load, and it is possible to greatly reduce the fluctuation of the output voltage due to the phase advancing load which changes in the direction in which the output voltage increases.

Further, the feedback gain changing circuit is
The feedback gain of the power factor correction circuit is increased as the output frequency of the AC power output by the switching circuit is switched to a higher frequency. As a result, the power factor correction circuit advances the phase of the detected current by approximately 90 ° regardless of switching of the output frequency of the AC power.

[0017]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

1 to 6 are general configuration diagrams of an engine generator including an inverter device according to the present invention. In FIG. 1, reference numerals 1 and 2 denote output windings independently wound around a stator of an AC generator, 1 denotes a three-phase output winding, and 2 denotes a single-phase auxiliary winding. Further, a magnetic pole of a multi-pole permanent magnet is formed on the rotor (not shown), and the rotor is configured to be rotationally driven by an engine (not shown). The output end of the three-phase output winding 1 is connected to the bridge rectifier circuit 3 composed of three thyristors and three diodes, and the output end of the bridge rectifier circuit 3 is connected to the smoothing circuit 4.

The output end of the single-phase auxiliary winding 2 is connected to a constant voltage supply device 5 having positive and negative output terminals E and F.
The constant voltage supply device 5 includes two sets of a rectifying circuit, a smoothing circuit, and a constant voltage circuit 5a. For a current in one direction from the single-phase auxiliary winding 2, each circuit of one set works, and For the current in the direction opposite to the direction, each circuit of the other set operates, whereby positive and negative constant voltages are output to the output terminals E and F, respectively.

Reference numeral 6 denotes a thyristor control circuit, one end of which is on the power supply input side is connected to the positive electrode output terminal E of the constant voltage supply device 5, and the other end is grounded together with the positive electrode terminal of the smoothing circuit 4. The signal input terminal of the thyristor control circuit 6 is a capacitor C.
1, a series circuit of resistors R1 to R3, one end of the signal input end on the capacitor C1 side is connected to the positive output terminal E of the constant voltage supply device 5, and the other end of the signal input end on the resistor R3 side is a smoothing circuit. 4 is connected to the negative electrode side terminal. The connection point between the resistors R1 and R2 is connected to the base of the transistor Q1, the collector of the transistor Q1 is connected to the base of the transistor Q2, and the collector of the transistor Q2 is connected to the gate input circuit of each thyristor of the bridge rectifier circuit 3, The input signal of the gate input circuit is controlled according to the potential of the connection point between R1 and the resistor R2 (for detailed description of the thyristor control circuit 6, refer to Japanese Patent Application No. 1-230908 of the applicant of the present application. It will be omitted here because it will be disclosed in the issue).

The output side of the transient suppression circuit 7 is connected to the connection point K between the capacitor C1 and the resistor R1. According to the transient suppression circuit 7, the cathode side of the Zener diode D1 is connected to the input side (G) of the constant voltage circuit 5a provided on the positive output terminal E side of the constant voltage supply device 5, and the anode side of the Zener diode D1 is a resistor. Is connected to the negative output terminal F of the constant voltage supply device 5 via the inverting comparator 701 and is connected to the inverting terminal (−) of the inverting comparator 701 composed of an operational amplifier, and the non-inverting terminal (+) of the inverting comparator 701 is a resistor. Grounded through. The output side of the inverting comparator 701 is the NOR circuit 702.
Of the NOR circuit 702 is connected to one terminal of the input side of the NOR circuit 702, and a protection device for detecting that the other side of the input side of the NOR circuit 702 needs to be protected, such as an overcurrent state of the engine generator. 8 is connected and a high level signal is supplied to the NOR circuit 702 when a state requiring protection is detected. N
The output side of the OR circuit 702 is connected to the base of the transistor Q3 via an inverter 703 and a resistor. The emitter of the transistor Q3 is connected to the negative output terminal F of the constant voltage supply device 5, and the collector of the transistor Q3 has a resistor R
4 is connected to the positive electrode output terminal E of the constant voltage supply device 5 via the capacitor 4 and the constant voltage supply device 5 via the capacitor C2.
Is connected to the negative output terminal F. The base of the transistor Q4 is connected to the positive terminal of the capacitor C2, the collector of the transistor Q4 is connected to the positive output terminal E of the constant voltage supply device 5, and the emitter of the transistor Q4 is connected to the anode of the diode D2. The connection point K between the capacitor C1 and the resistor R1 of the thyristor control circuit 6
Connected to. The cathode of the diode D2 is connected to the positive terminal of the capacitor C2.

The output side of the smoothing circuit 4 is connected to the bridge type inverter circuit 9 shown in FIG. The bridge type inverter circuit 9 has four FETs (field effect transistors) Q5 to Q.
FET Q5, Q6
The current detecting resistors R5 and R6 for detecting the load current are connected between the drain and the common line grounded. The drive signal circuit connected to the gate terminals of the FETs Q5 to Q8 will be described later.

The output side of the bridge type inverter circuit 9 is connected to output terminals 11 and 12 to which a load (not shown) is connected via output lines 10a and 10b and an output circuit 10 composed of a low pass filter. The output circuit 10 includes a low-pass filter including coils L1 and L1 connected in series with a load and a capacitor C3 connected in parallel with the load.

The output lines 10a and 10b are connected to the detection circuit 13 shown in FIG. 4, which is composed of a dividing resistor and a differential amplifier.
The detection circuit 13 detects the waveform distortion or offset component of the output by directly comparing the output voltages appearing on the output lines 10a and 10b, and outputs a detection signal.

14 is a commercial frequency, for example, 50 Hz or 6
It is a sine wave oscillator (sine wave forming circuit) that generates a 0 Hz sine wave reference signal. The output side of the sine wave oscillator 14 is connected to the inverting input terminal (−) of the differential amplifier 15. The output side of a power factor correction circuit 26 (FIG. 5) described later is connected to the inverting input terminal (−) of the differential amplifier 15. The non-inverting input terminal (+) of the operational amplifier of the differential amplifier 15 has a peak detection circuit 1 which constitutes a correction circuit together with the differential amplifier 15.
The output side of 6 (FIG. 3) is connected. Peak detection circuit 16
Is composed of three stages of high-speed type operational amplifiers. The gain in each operational amplifier is increased by about 10 times to obtain a high slew rate, and a total of four stages including the differential amplifier 15 are stacked to obtain a high gain. I try to secure it.

The peak detection circuit 16 of FIG. 3 is constructed as follows. Current detection resistors R5 and R6 and FETs Q5 and Q
The connection points M and N with 6 are the non-inverting input terminal (+) and the inverting input terminal (-) of the input side amplifier 1611 of the two-stage amplifier 161.
The output side of the amplifier 1611 is connected to the two-stage amplifier 16
1 output side amplifier 1612 is connected via an output line 161a. The output side of the amplifier 1612 is connected to the non-inverting input terminals (+) of the offset amplifier 162 and the offset amplifier 163 and the input side of the power factor correction circuit 26.

In the power factor correction circuit 26, the amplifier 16
The output side of 12 is connected to the inverting input terminal (−) of the operational amplifier 261 via the resistor R13, and is connected to the non-inverting input terminal (+) of the operational amplifier 261 via the phase shift circuit of the capacitor C8 and the resistor R14. The output terminal of the operational amplifier 261 is connected to the inverting input terminal (−) of the differential amplifier 15 via the resistor R15. The signal input to the power factor correction circuit is output with the phase advanced by 90 ° by the phase shift circuit including the capacitor C8 and the resistor R14.

An upper and lower limit value setting circuit 164 is composed of four series resistors R7 to R10, one end of which is connected to the positive output terminal E of the constant voltage supply circuit 5 and the other end of which is the negative output of the constant voltage supply circuit 5. While being connected to the terminal F, the connection point between the resistors R8 and R9 is grounded. This upper and lower limit value setting circuit 1
The predetermined upper limit voltage value obtained by 64 is supplied to the inverting input terminal (−) of the operational amplifier of the offset amplifier 162, and the predetermined lower limit voltage value is supplied to the inverting input terminal (−) of the operational amplifier of the offset amplifier 163. ..

The output side of the offset amplifier 162 is connected to the anode of the diode D3.
The output side of 3 is connected to the cathode of diode D4.
The cathode of the diode D3 and the anode of the diode D4 are grounded via a resistor and connected to the non-inverting input terminal (+) of the operational amplifier of the differential amplifier 15 in FIG. As will be described in detail later, the differential amplifier 15 outputs from the sine wave oscillator 14 according to a feedback signal corresponding to the output current (load current) of the output lines 10a and 10b and a feedback signal output from the power factor correction circuit 26. The sine wave reference signal is corrected.

The output side of the differential amplifier 15 is a differential amplifier 17.
Is connected to the inverting input terminal (−) of the operational amplifier of the differential amplifier 17, and the non-inverting input terminal (+) of the operational amplifier of the differential amplifier 17 is connected to the output side of the detection circuit 13. The differential amplifier 17 corrects the sine wave reference signal level output from the sine wave oscillator 14 with the detection signal output from the detection circuit 13, and outputs a corrected sine wave signal.

Reference numeral 18 is a rectangular wave oscillator. The frequency of the rectangular wave signal oscillated and output by the rectangular wave oscillator 18 is set to a value significantly higher than the frequency of the sine wave reference signal output from the sine wave oscillator 14. It The output side of the rectangular wave oscillator 18 is connected to an integrating circuit 19, which integrates the rectangular wave signal and converts it into a triangular wave signal.

The corrected sine wave signal output from the differential amplifier 17 and the triangular wave signal output from the integrating circuit 19 are superposed on each other to form an inverter buffer (pulse width modulation circuit).
20. The inverter buffer 20 has a predetermined threshold value (threshold level), outputs a low level signal when a signal having a level exceeding the threshold value is input, and outputs a signal having a level below the threshold value. Outputs a high-level signal when is input, and forms a so-called pulse width modulation (PWM) signal. For example, a CMOS gate IC having a fixed threshold value with respect to an input signal to the gate terminal is used. To be done.

The output side of the inverter buffer 20 is shown in FIG.
The signal is input to one input end of the NAND circuit 22 via the inverter 21 and directly input to one input end of the NAND circuit 23. The output terminal J of the NOR circuit 702 of the transient suppression circuit 7 is connected to the other input terminal of the NAND circuit 22 and the other input terminal of the NAND circuit 23. The output sides of the NAND circuits 22 and 23 of FIG. 6 are connected to the FET gate drive signal circuits 24 and 25, respectively. The FET gate drive signal circuit 24 is a push-pull amplifier, a surge absorbing diode, and a capacitor C for cutting low frequency components.
4. Composed of primary coils of pulse transformers A and C. Similarly, the FET gate drive signal circuit 25 includes a push-pull amplifier, a surge absorbing diode, a capacitor C5 for cutting low frequency components, and a primary of pulse transformers B and D. It consists of a side coil.

The secondary coil of the pulse transformer A (shown in the bridge type inverter circuit 9 in FIG. 2) is an attenuation resistor, a demodulating capacitor C6, and a bidirectional voltage regulating diode D.
It is connected to the gate of the FET Q5 via 5, D6. The secondary side coils of the pulse transformers B, C, and D are also FETs through a circuit exactly the same as the secondary side circuit of the pulse transformer A.
Connected to the gates of Q6, A7, and Q8 respectively (FET
A switching control circuit is configured by the gate drive signal circuits 24 and 25, each pulse transformer, an attenuation resistor, a demodulation capacitor, a bidirectional voltage regulation diode, etc.).

Next, the operation of the engine generator including the inverter device configured as described above will be described.

The three-phase AC power output from the three-phase output winding 1 as the engine is driven is rectified by the bridge rectifier circuit 3, smoothed by the subsequent smoothing circuit 4 and converted to DC power, and the smoothing circuit 4 is also provided. The fluctuation of the DC voltage at the resistor R2
The output voltage of the smoothing circuit 4 is stably maintained at a predetermined DC voltage by being detected by the thyristor control circuit 6 via R3 and controlling the conduction of each thyristor of the bridge rectifier circuit 3 based on the detection signal. Feedback control is performed. Although the output signal from the transient suppression circuit 7 is also input to the thyristor control circuit 6, the operations of the thyristor control circuit 6 and the bridge rectification circuit 3 based on this signal will be described later.

A pulse width modulation (PWM) signal, which will be described later, is input to the gates of the FETs Q5 and Q7 and the FETs Q6 and Q8 of the inverter circuit 9, and F is generated according to the PWM signal.
By alternately conducting the ETQ5, Q7 and the FETs Q6, Q8, the DC output of the smoothing circuit 4 is switching-controlled and output to the output circuit 10. The output circuit 10 cuts high frequency components and outputs AC power of commercial frequency to the output terminal 1
Supply from 1 and 12 to the load.

The output voltage appearing on the output line 10a and the output voltage appearing on the output line 10b are the resistors R11 and R1.
The high-frequency component is removed by the filter circuit including 2 and the capacitor C7, the commercial frequency component is compared by the detection circuit 13, and the difference, that is, the distortion or offset component of the waveform of the output voltage is detected, and the detection signal is detected. It is output to the differential amplifier 17.

The sine wave reference signal of the commercial frequency output from the sine wave oscillator 14 is subjected to the power factor correction and the peak value correction according to the AC output current by the operation of the differential amplifier 15 which will be described later in detail, and then the difference. It is input to the dynamic amplifier 17.

The differential amplifier 17 compares the corrected sine wave signal output from the differential amplifier 15 with the feedback signal including the distortion of the waveform of the output voltage output from the detection circuit 13 or the DC offset, The level of the corrected sine wave signal is corrected by the feedback signal, and the corrected sine wave signal is output again.

The rectangular wave signal output from the rectangular wave oscillator 18 is integrated by the integrating circuit 19 and converted into a triangular wave signal. The triangular wave signal and the corrected sine wave signal from the differential amplifier 17 are superimposed to form a superimposed signal, which is input to the inverter buffer 20. The inverter buffer 20 outputs a low-level signal when the superposed signal exceeds the threshold value, and outputs a high-level signal when the superimposed signal is below the threshold value. Thus, the pulse width modulated PWM signal is output. Since this PWM signal is formed based on the corrected sine wave signal, the power factor correction and the peak value correction of the AC output current are performed (this will be described later) and the distortion and offset component of the output voltage. It is possible to reduce the frequency of the carrier wave because the inverter buffer (about 50 nsec), which has a response time much faster than that of the comparator (about 1 μsec), is used to form the PWM signal.
This makes it possible to supply higher-quality AC power that approximates the output waveform to a sine wave.

P output from the inverter buffer 20
One of the WM signals is inverted by the inverter 21 and NAND
The other is input to the circuit 22 and the other is input to the NAND circuit 23 as it is. A low level signal is supplied to the NAND circuits 22 and 23 from the transient suppression circuit 7 when a state requiring protection such as an overcurrent state is detected or when a low rotation state such as engine start is detected. Sometimes the NAND circuit 22,
The output of 23 becomes a high level signal regardless of the PWM signal, and since this state is continued, the PWM signal is not transmitted. On the other hand, when the state requiring protection is not detected and the engine speed is also equal to or higher than the predetermined speed, a high level signal is supplied from the transient suppression circuit 7, and at this time, the NAND circuits 22 and 23 respectively input. Inverted or non-inverted PWM according to inverted or non-inverted PWM signal, respectively
A signal obtained by inverting the signal is output, the PWM signal is supplied to the FET gate drive signal circuit 24, and the inverted PWM signal is supplied to the FET gate drive signal circuit 25.

In the FET gate drive signal circuit 24, P
After the WM signal is push-pull amplified, the capacitor C
At 4, the low frequency component, that is, the commercial frequency component is cut.
The signal immediately before passing through the capacitor C4 is a PWM signal whose amplitude is constant with respect to the reference level, but the average voltage (integral value) of this signal changes in the same cycle as the sine wave from the sine wave oscillator 14. Therefore, this PWM signal contains the same frequency (commercial frequency) component as this sine wave. After the PWM signal passes through the capacitor C4, the entire pulse train goes up and down in reverse phase to the commercial frequency component and is converted into a pulse signal train in which the average voltage is always zero.

Since the pulse signal train whose average voltage is always zero is supplied to the primary coils of the pulse transformers A and C, the transformer cores forming the pulse transformers A and C are magnetically saturated by the commercial frequency component. Therefore, it is possible to configure the transformers A and C with a small size that does not cause magnetic saturation at the PWM carrier frequency.

The operation of the FET gate drive signal circuit 25 is exactly the same as that of the FET gate drive signal circuit 24.

The pulse signal output from the secondary coil of the pulse transformer A is compared with each breakdown voltage of the Zener diodes D5 and D6, and the capacitor C6 is charged / discharged by the amount exceeding each breakdown voltage. Shows the average voltage (which has a commercial frequency) by virtue of exceeding each breakdown voltage. Therefore, between the gate and source of the FET Q5, a signal in which the voltage across the capacitor C6 having the commercial frequency and the pulse signal output from the secondary coil of the pulse transformer A are superimposed, that is, the PWM signal before passing through the capacitor C4 Is demodulated. The FET Q5 conducts only while the positive pulse of the PWM signal is input to the gate.

The pulse signal output from the secondary coil of the pulse transformer C is processed in exactly the same manner as the pulse signal output from the secondary coil of the pulse transformer A described above, and FE
The conduction of TQ7 is performed at the same timing as the conduction of FET Q5.

The pulse signals output from the secondary coils of the pulse transformers B and D are processed in the same manner as the pulse signals output from the secondary coils of the pulse transformers A and C described above. However, since the PWM signal input to the pulse transformers B and D and the PWM signal input to the pulse transformers A and C have opposite phases, when the FETs Q5 and Q7 become conductive, F
ETQ6 and Q8 become non-conducting, on the contrary, FETQ5 and Q8
When Q7 becomes non-conductive, the FETs Q6 and Q8 operate so as to become conductive.

As described above, the sine wave signal of the commercial frequency, which is feedback-corrected based on the output waveform, is pulse-width modulated by the high-frequency triangular wave signal, and the inverter circuit 9 performs the switching control based on the pulse-width modulated signal. After that, the carrier frequency component is cut by the output circuit 10, and the AC power of the commercial frequency that approximates a sine wave is output from the output terminal 1.
1, 12 is supplied to the load.

The bridge type inverter circuit 9 and the detection circuit 13 or the FET gate drive signal circuits 24 and 2 described above.
5 (However, the differential amplifier 15 and the peak detection circuit 16,
For a more detailed description of the configuration and operation of the power factor correction circuit 26), refer to Japanese Patent Application No. 2-30
No. 7823.

Next, the operation of the transient suppression circuit 7 will be described.

Since the output voltage of the AC generator is low immediately after the engine is started, the constant voltage circuit 5 constituting the constant voltage supply device 5
Since the voltage at the input end of a is low, it does not exceed the breakdown voltage of the Zener diode D1 (the voltage corresponding to the set value of the engine speed set to a value lower than the rotational speed during rated operation) at the beginning of starting, Zener diode D1 is non-conductive. Therefore, the inverting terminal (−) of the inverting comparator 701 has a low level, and the output of the inverting comparator 701 has a high level.

Since the NOR circuit 702 outputs a low level signal when a high level signal is input to at least one of the input sides, the output of the NOR circuit 702 is the high level output of the inverting comparator 701 or the high level output of the protection device 8. Output goes low.

This low level signal is inverted by the inverter 703 to become a high level signal, which makes the transistor Q3 conductive and discharges the capacitor C2. Therefore, the transistor Q4 becomes non-conductive, and the potential at the connection point K between the capacitor C1 and the resistor R1 becomes low level.

Therefore, the transistor Q1 of the thyristor control circuit 6 becomes non-conductive, the transistor Q2 becomes conductive, and a low level signal is supplied to the gate of each thyristor of the bridge rectifier circuit 3. As a result, the thyristors do not conduct, and the bridge rectifier circuit 3 does not supply the rectified output. That is, when the engine speed is less than or equal to the set value, or when a state requiring protection is detected, the bridge rectifier circuit 3 is prevented from supplying a rectified output, which causes an unstable operation of the inverter device at engine start. Is suppressed, and the output supply is stopped when a condition requiring protection such as an overcurrent condition due to overload is detected.

Next, after the engine is started, the output voltage of the AC generator gradually rises, the voltage at the input end of the constant voltage circuit 5a rises, and the breakdown voltage of the Zener diode D1 is exceeded, that is, the engine speed is increased. When the set value is exceeded, the Zener diode D1 becomes conductive, the inverting terminal (−) of the inverting comparator 701 turns to high level, and the output of the inverting comparator 701 becomes low level.

At this time, if the state requiring protection is not detected, the output of the NOR circuit 702 turns to high level,
The output of the inverter 703 becomes low level. Therefore, the transistor Q3 becomes non-conductive, and the capacitor C2 has a resistance R.
It is charged via 4. By this charging, the capacitor C2
The potential on the positive electrode side gradually increases based on the time constant determined by the capacitance of the capacitor C2 and the resistance value of the resistor R4. Although the transistor Q4 becomes conductive due to the increase in the potential on the positive electrode side of the capacitor C2, the conduction of this transistor Q4 increases the emitter potential of the transistor Q4 and causes the transistor Q4.
If it becomes higher than the base potential of the transistor Q4, the transistor Q4 is turned off, so that the potential at the point K is always maintained at a value slightly lower than the potential on the positive electrode side of the capacitor C2. Therefore, the potential at the point K gradually increases after the engine speed exceeds the set value based on the time constant determined by the capacitance of the capacitor C2 and the resistance value of the resistor R4.

Therefore, since the thyristor control voltage (between XY) is proportional to the K point potential, it gradually rises, and finally the K point potential reaches the positive electrode output potential of the substantially constant voltage supply device 5, and the gate of each thyristor. The voltage reaches a predetermined feedback control input value for maintaining the potential at the connection point between the resistors R1 and R2 at a predetermined value.

Thus, even when the load is still connected to the output terminals 11 and 12 when the engine is started, the output voltage of the alternator is not sufficiently increased and the bridge rectifier circuit is unstable. It is possible to prevent sudden current inrush into each of the thyristors of No. 3. This prevents each FET of the bridge-type inverter circuit 9 from being subjected to a sudden voltage change in an unstable state. This prevention effect is obtained when the engine is started and the output terminals 11, 12 are
The larger the load connected to is, the larger the effect is, and particularly when the load is in the short-circuit state, the effect of suppressing the adverse effect on the thyristor and the FET is extremely large.

Next, the operation of the power factor correction circuit 26 will be described.

The pair of current detecting resistors R5 and R6 of the bridge type inverter circuit 9 are connected to the bridge type inverter circuit 9.
A voltage corresponding to the output current (load current) of is generated. Figure 7
The detected current waveform at the connection point M is shown in (a). As shown in FIG. 7B, the detected current waveform at the connection point N has a phase opposite to that in FIG. 7A. The detected current waveform signal (output current signal) at the connection points M and N is the operational amplifier 1611 of the peak detection circuit 16.
Is input to the non-inverting input terminal (+) and the inverting input terminal (-) of the. The operational amplifier 1611 constitutes an integrating circuit,
High frequency components are removed from the input potential signals at the connection points M and N, and when attention is paid only to the potential signal at the connection point M, a signal including a DC component and a commercial frequency component is an operational amplifier 16
Appears on the output side of 11. This signal is inverted and amplified by the operational amplifier 1612 which constitutes the integrating circuit, so that FIG.
The signal of the commercial frequency from which the high frequency component as shown in (c) is removed is input to the power factor correction circuit 26 of FIG.

In the power factor correction circuit 26, the input current waveform is output with its phase advanced by 90 ° by the phase shift circuit.

Here, the input end point of the differential amplifier 15 to which the sine wave reference signal output from the sine wave oscillator 14 is input is a, the input end point of the power factor correction circuit 26 is b, and the operational amplifier of the power factor correction circuit 26 is. The output end point of the H.261 is c, and the differential amplifier 1
Assuming that the inverting input end point of the operational amplifier of 5 is d, at the point d, resistance mixing is performed by the resistor R15 at the output stage of the power factor correction circuit 26 and the resistor connected to the inverting input terminal of the operational amplifier of the differential amplifier 15. Therefore, the voltage value X (φ) at the point d is the voltage value sin θ of the sine wave reference signal at the point a and the output voltage value sin (θ + φ + of the power factor correction circuit 26 at the point c.
π / 2), and can be expressed as X (φ) = sin θ + B sin (θ + φ + π / 2). Here, B is a mixing ratio determined by the resistance R15 of the output stage of the power factor correction circuit 26 and the resistance connected to the inverting input terminal of the operational amplifier of the differential amplifier 15.

Based on the above equation, in the case of a resistive load (cos
FIG. 8 shows the signal waveforms in each of the case of φ = 1), the case of the advance load (cosφ = 0) and the case of the delay load (cosφ = 0). That is, assuming that the amplitude VM of the sine wave reference signal at point a is 1 and the mixing ratio B is 1,
In the case of a resistive load, the signal waveform of the output current at point b has the same phase and amplitude as the sine wave reference signal waveform at point a, and the signal waveform at point c, which is the output end point of the power factor correction circuit 26, is at this point b. The signal waveform of is advanced by 90 °. Therefore, a
The amplitude X (φ) of the signal waveform at the point d obtained by resistance mixing the signal waveform at the point and the signal waveform at the point c with the mixing ratio B of 1 is √
It becomes 2.

Further, in the case of a phase advance load, the signal waveform of the output current at point b is advanced by 90 ° from the sine wave reference signal waveform at point a, and the signal waveform at point b is advanced by 90 °. The signal waveform at the point c which has been phased leads the signal waveform at the point a by 180 °. As a result, the amplitude X (φ) of the signal waveform at point d in this case becomes zero.

Further, in the case of a lagging load, the signal waveform of the output current at point b is delayed by 90 ° from the sine wave reference signal waveform at point a, and the signal waveform at point b is advanced by 90 °. The signal waveform at point c thus made is in phase with the signal waveform at point a. Therefore, the amplitude X (φ) of the signal waveform at point d in this case is 2.

An absolute amplification factor Y obtained by further dividing the signal amplitude X (φ) at the point d, which shows a typical case in FIG. 8, by | sin θ |
FIG. 9 is a graph showing (φ) = | X (φ) | / | sin θ | as a function of the phase angle φ for various mixing ratios. A mixing ratio B of about 0.17 is suitable for implementation.

In this way, by advancing the phase of the detection current by 90 ° and using the power factor-corrected sine wave reference signal as a new sine wave reference signal, the fluctuation of the output voltage can be minimized. it can. For example, according to the actual measurement data of the present embodiment, the voltage fluctuation rate at the time of resistance load is -6.2% (-
6.6%), the voltage fluctuation rate at the time of a delayed load is -1.4% (-1
1.0%), voltage fluctuation rate during phase advancing load -1.7% (+
9.7%); (in the parentheses, the voltage fluctuation rate in the case where the power factor correction according to the present invention is not applied) except for the time of resistive load,
The voltage fluctuation rate can be significantly reduced, and in particular, the fluctuation in the voltage increasing direction can be almost completely eliminated. As a result, it is possible to avoid a failure of the load or the AC power supply device itself caused by the output voltage fluctuation.

Next, the operations of the peak detection circuit 16 and the differential amplifier 15, which are one of the correction circuits, will be described.

The detected current signal input to the two-stage amplifier 161 of the peak detection circuit 16 is integrated and amplified by the two-stage amplifier 161, becomes a commercial frequency signal with high frequency components removed, and is output to the offset amplifiers 162 and 163. It The offset amplifier 162 compares the amplitude of the commercial frequency signal from the operational amplifier 1612 with a predetermined upper limit voltage value input from the upper and lower limit value setting circuit 164 to the inverting terminal (−) of the operational amplifier, and determines the peak current determination threshold value. Amplifies only the amount exceeding a predetermined upper limit voltage value (offset amplification). In the offset amplifier 163, the operational amplifier 161
The upper and lower limit value setting circuit 1 sets the amplitude of the commercial frequency signal from 2
64 is compared with a predetermined lower limit voltage value which is a threshold value of the peak current discrimination input to the inverting terminal (-) of the operational amplifier,
Only the amount that falls below the predetermined lower limit voltage value is amplified (offset amplification). The outputs of the offset amplifiers 162 and 163 pass through the diodes D3 and D4, respectively, and are superimposed.
Therefore, the signal after this superposition is a signal in which only the part where the level of the amplified commercial frequency signal exceeds the predetermined upper limit voltage value or the part where it falls below the lower limit voltage value is synthesized,
When the level of the amplified commercial frequency signal does not exceed the predetermined upper and lower limit voltage values, this combined signal maintains the zero level.

This composite signal is input to the non-inverting terminal (+) of the operational amplifier of the differential amplifier 15. Differential amplifier 15
Then, this combined signal is compared with the above-described power factor-corrected sine wave reference signal and differentially amplified. That is, when the AC output current becomes large and the level of the commercial frequency signal corresponding thereto exceeds a predetermined upper and lower limit voltage value, the footback correction is performed according to the exceeded amount and the peak of the corresponding sine wave is obtained. The part is crushed, and the sine wave whose peak part is corrected is output to the next differential amplifier 17.

As a result, the AC output current obtained by the pulse width modulation control performed on the basis of the thus corrected sine wave signal has its corresponding peak portion crushed, whereby the peak current value of the AC output current is reduced. You are limited. It should be noted that when the overcurrent flows, the peak current value is only limited and the current supply is not interrupted. Therefore, the load in which the peak current value of the output temporarily becomes large can be energized without any trouble. Can be continued.

Further, even in the case of a special load such as a half-wave rectification load, the DC component is not lost as shown in FIGS. 6B and 6C, so that the peak value can be accurately detected. Therefore, the overcurrent can be appropriately suppressed.

FIG. 10 is a circuit diagram showing another embodiment of the power factor correction circuit of FIG.

This embodiment is different from the above embodiment in that
The difference is that the feedback gain of the power factor correction circuit can be changed according to the change of the output frequency of the AC power.

That is, in the present embodiment, when the circuit constant in the power factor correction circuit 26 of FIG. 5 described above is set to a value that advances the phase by approximately 90 ° when the output frequency is 50 hertz (Hz), U The phase of the output current output from the point W with respect to the input current input to the point is, for example, when the input current frequency is 5
This solves the problem that the phase advances by 90 ° at 0 hertz but does not advance by 90 ° at 60 hertz. Hereinafter, description will be given by actually setting the circuit constants.

FIG. 11 shows only the elements necessary for explanation in the power factor correction circuit of FIG. In the figure, the inverting input terminal of the operational amplifier 261 (-) and a resistor connected between the output terminal and R17, the frequency to 90 ° leading phase output current to the input current when the f _90, f ₉₀ is calculated by the following mathematical expression (1).

F ₉₀ = [1 / (2πR14 · C8)] · [(R13 + R17) / (2R13)] (1) Further, the gain A at this time is

[0079]

[Equation 1] Becomes

Here, as a circuit constant, R13 = 10K
If Ω, R14 = 33 KΩ, and C8 = 0.1 μF are set, an input current having a frequency of 50 Hertz will have a gain of A
When = 1, the phase advances by 90 °.

FIG. 12 is a graph showing the result of simulation using this circuit constant. In the figure,
The vertical axis represents gain, phase difference and delay time, and the horizontal axis represents
The frequency indicates the frequency, and the characteristic curves of the three graphs indicate the delay time, the gain, and the phase difference in order from the top. As shown in the phase difference graph, the input current having a frequency of 50 hertz is advanced by 90 °, but the input current having a frequency of 60 hertz is advanced by only 77 °. This embodiment solves this point.

As shown in FIG. 10, the power factor correction circuit 26 'of this embodiment is different from the power factor correction circuit 26 shown in FIG.
A resistor 18 and an analog switch 26 which form an output frequency switching circuit and a feedback gain changing circuit.
2, an operational amplifier 263 and a switch 264 are added. 10, the elements corresponding to those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 10, the resistor R18 and the analog switch 262 are connected in series.
It is connected in parallel with 17. Further, a control input terminal CONT for controlling the on / off of the analog switch 262.
Is connected to the output side of the operational amplifier 263, and the inverting input terminal (-) of the operational amplifier 263 is connected to a switch 264 for selecting -5V voltage when the output frequency is 50 hertz and 0V voltage when the output frequency is 60 hertz. At the non-inverting input terminal (+), a voltage of -5 V is divided by two resistors R19 and R20 each having a resistance value of 10 KΩ,
A voltage of 2.5V is applied. The switch 264
Is attached to the panel of the inverter device, for example,
The output frequency (50 or 60 hertz) is interlocked with a switch (not shown) to switch the output frequency according to the output frequency.

The power factor correction circuit 2 configured as described above
At 6 ', when a current having a frequency of 50 Hertz is input, a voltage of -5V is applied to the inverting input terminal (-) of the operational amplifier 263 by the switching operation of the switch 264, and the non-inverting input terminal (+) is applied. Of the applied voltage of -2.5 V, the operational amplifier 263 outputs a high level voltage (supply voltage of the operational amplifier 263). This output voltage turns on the analog switch 262, the resistor R18 is connected in parallel with the resistor R17, and the combined resistors R17 and R18 are connected.
/ (R17 + R18) is connected to the inverting input terminal (−) and the output side of the operational amplifier 261. By substituting the value of this combined resistance for the value of R17 in the equation (1), f ₉₀ becomes 60 hertz. At this time, R18 = 3
It is 6 KΩ, and other circuit constants are the same as the values described in FIG. Further, assuming that the gain when a current having a frequency of 60 hertz is input is A ₆₀ and the gain when the current is 50 hertz is A ₅₀ , A ₆₀ > A ₅₀ by the formula (2).
Becomes

FIG. 13 and FIG. 14 are views showing the power factor load characteristic without the output frequency switching circuit and the feedback gain changing circuit of this embodiment and the power factor load characteristic with it, respectively, for comparison. , The vertical axis and the horizontal axis represent the output voltage and the output current, respectively. In FIG. 13, the slope characteristic of the output voltage against the output current during a phase-advanced load is flat when the output frequency is 50 hertz, but the output voltage rises as the output current increases when the output frequency is 60 hertz. In the case of 50 Hz in the case of a lagging load, the slope characteristic does not drop so much with respect to the increase in the output current, but in the case of 60 Hz, the drop amount is considerably large. On the other hand, in the characteristics of FIG. 14 obtained by this example, there is almost no difference in characteristics between 50 hertz and 60 hertz both when the phase is advanced and when the phase is retarded. Is also suppressed, and the drop in lagging load is also improved.

As described above, in the present embodiment, the phase of the output frequency can be advanced by 90 ° with respect to the input frequency regardless of the change of the output frequency of the AC power, and it depends on the fluctuation of the power factor of the load. The output voltage fluctuation can be minimized.

[0087]

As described above, in the inverter device of the present invention, the phase of the detected current detected by the current detection circuit is advanced by about 90 ° and is fed back to the sine wave reference signal so that the sine wave reference signal is fed back. Since the amplitude of the reference signal is corrected, the output voltage fluctuation due to the fluctuation of the power factor of the load of the AC power supply is minimized, and the output voltage fluctuation due to the phase-advanced load that changes in the direction in which the output voltage rises is minimized. It can be greatly reduced.

According to the second aspect of the present invention, the phase of the detection current detected by the current detection circuit is advanced by about 90 ° regardless of the output frequency of the AC power and fed back to the sine wave reference signal. Therefore, even when the output frequency of the AC power is changed, the above-mentioned effects can be reliably exhibited.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a bridge-type rectifier circuit and the like which constitute an engine generator including an inverter device according to the present invention.

FIG. 2 is a circuit diagram showing a bridge-type inverter circuit or the like which constitutes an engine generator including an inverter device according to the present invention.

FIG. 3 is a circuit diagram showing a peak detection circuit constituting an engine generator including an inverter device according to the present invention.

FIG. 4 is a circuit diagram showing a pulse width modulation circuit and the like constituting an engine generator including an inverter device according to the present invention.

FIG. 5 is a circuit diagram showing a power factor correction circuit constituting an engine generator including an inverter device according to the present invention.

FIG. 6 is a circuit diagram showing a FET gate drive signal circuit and the like which constitute an engine generator including an inverter device according to the present invention.

7 is a time chart showing signals of respective parts of the peak detection circuit of FIG.

8 is a waveform diagram showing a typical example of signal waveforms of respective parts of the power factor correction circuit of FIG.

9 is a graph showing an absolute amplification factor of the power factor correction circuit of FIG.

FIG. 10 is a circuit diagram showing another embodiment of the power factor correction circuit.

11 is a circuit diagram showing main elements of the power factor correction circuit of FIG.

12 is a graph showing a result of simulation performed by setting a circuit constant in the circuit of FIG.

13 is a diagram showing power factor load characteristics of an inverter device having the power factor correction circuit of FIG.

14 is a diagram showing power factor load characteristics of an inverter device having the power factor correction circuit of FIG.

[Explanation of symbols]

 9 bridge type inverter circuit 14 sine wave oscillator (sine wave forming circuit) 15, 16 differential amplifier, peak detector (correction circuit) 20 inverter buffer (pulse width modulation circuit) 26 power factor correction circuit R5, R6 current detection resistor R14 Phase shift resistor C8 Phase shift capacitor

Claims (3)

[Claims] 1. A DC power supply circuit, an inverter circuit for switching control of the output of the DC power supply circuit, a sine wave output circuit for outputting a sine wave reference signal of a predetermined frequency, and the sine wave output circuit for outputting the sine wave output circuit. A pulse width modulation circuit for pulse width modulating a sine wave reference signal and outputting a PWM signal;
In an inverter device having a switching control circuit that forms AC power of the predetermined frequency by performing a switching operation of the inverter circuit based on the PWM signal output from the pulse width modulation circuit, an output current of the AC power is output. A current detection circuit for detecting and a power factor correction for correcting the amplitude of the sine wave reference signal by advancing the phase of the detected current detected by the current detection circuit by about 90 ° and feeding it back to the sine wave reference signal. An inverter device comprising a circuit. 2. A switching circuit for switching the output frequency of the AC power, and increasing the feedback gain of the power factor correction circuit so that the output frequency is switched to a higher frequency by the switching circuit, thereby correcting the power factor. The inverter device according to claim 1, further comprising a feedback gain changing circuit that allows the circuit to advance the phase of the detected current by approximately 90 °. 3. The output frequency of the switching circuit is 50.
It is possible to switch between Hertz and 60 Hertz, and the feedback gain changing circuit controls the feedback gain of the power factor correction circuit so that the feedback gain is higher when the output frequency is 60 Hertz than when it is 50 Hertz. The inverter device according to claim 2, wherein: