JPH05211432A - Data output circuit and semiconductor integrated circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In an integrated circuit that can operate at high speed, when it is not necessary to drive the external signal line at high speed during low speed operation,
The drive capability of the data output circuit is reduced to reduce the transient current,
Noise generated inside and outside the integrated circuit is reduced. [Structure] A plurality of drive circuits are provided for one external signal line so that each drive circuit may or may not drive the external signal line, or the timing for driving the external signal line can be set individually. The setting can be freely set by a user after the manufacturing process by a control signal inside or outside the integrated circuit, a register, a memory, or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technology and a technology effectively applied to a noise reduction method in a semiconductor integrated circuit, and more particularly to a technology effectively applied to a data output circuit in a logic LSI. ..

[0002]

2. Description of the Related Art In a conventional data output circuit in a semiconductor integrated circuit, one drive circuit is provided for each external signal line, and the load drive capability of the data output circuit is used. It was impossible for Z to change or set as needed. Also, in an integrated circuit that can operate at high speed,
The load drive capability of the data output circuit is set according to the case of operating at the maximum operating frequency.The switching speed of the external signal does not change even if the operating frequency becomes low, and the transient current is the same as during high-speed operation. There wasn't.

[0003]

The present inventors have found that even an integrated circuit capable of operating at high speed is not always operated at the maximum operating frequency, but is operated at a frequency lower than the maximum operating frequency. I noticed that there is. However,
In conventional semiconductor integrated circuits, no consideration is given to changing the load driving capacity of the data output circuit according to the operating frequency of the circuit. As with high-speed operation, since high-speed switching is performed with a large current, noise may be added to the power supply line to cause various circuits mounted on the integrated circuit chip to malfunction, or electromagnetic waves may be generated to cause various electronic signals outside the integrated circuit. There is a problem that the circuit causes malfunction due to radiation noise and deterioration of accuracy.

It is an object of the present invention to suppress a noise level in a semiconductor integrated circuit capable of high-speed operation during low-speed operation that does not require high driving capability, and prevent malfunction of various circuits inside and outside the integrated circuit due to noise. There is. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, by providing a plurality of drive circuits for one external signal line, each of which can be operated individually, and by changing the number of drive circuits to be operated according to the operating frequency after manufacturing the integrated circuit, the data output circuit The load driving capability can be changed.

To operate a plurality of drive circuits individually,
Set valid / invalid (operation enable / disable) for each drive circuit,
There are a method of changing the number of operating drive circuits, a method of individually setting the operation timing of a plurality of drive circuits by a delay element, a clock, etc., or a method of combining them. As the operation control method of the drive circuit, a method by a combination of control signals composed of a plurality of signals,
There is a method of holding information in a register or a memory, or a method of combining them.

[0007]

According to the above means, the number of drive circuits to be operated is changed according to the operating frequency so that an unnecessarily large transient current does not flow in the output circuit. The peak value of the transient current, which is the cause, can be significantly reduced as compared with the case of operating at the maximum operating frequency, and the above-described object of minimizing the generation of noise is achieved.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a data output circuit according to the present invention. In the figure, 1 is an external output terminal to which an external signal line (not shown) is connected. In this embodiment, three drive circuits 2 are provided corresponding to one external output terminal 1.
a, 2b, 2c are provided, and each drive circuit 2a, 2
b and 2c are control signals C supplied from the output control circuit 3.
1, C2, C3 determine whether to enable / disable, that is, to operate or not to operate.

The output control circuit 3 has a driving force according to the operating frequency or the load of the external signal line by, for example, providing a state setting means having a fuse therein and cutting the fuse or not. The control signal is configured to operate only the drive circuit.
Alternatively, the output control circuit 3 may be configured to generate the control signals C1, C2, C3 in response to a mode designation signal from the mode setting circuit, or a register or memory may be provided inside the mode setting circuit, depending on the stored contents. Alternatively, the control signals C1, C2 and C3 may be formed. Further, the output control circuit 3 may be provided with a circuit for monitoring the operating clock to detect the operating frequency, and the control signals C1, C2, C3 may be formed according to the detected frequency.

The driving forces of the drive circuits 2a, 2b and 2c may be the same or different. When the driving forces are the same, the number of driving circuits driven simultaneously is changed according to the operating frequency. When the driving force is different, it is possible to further finely change the driving force by selecting the driving circuit driven according to the operating frequency or changing the number of driving circuits driven at the same time.

Further, by shifting the timings of the control signals C1, C2, C3 formed by the output control circuit 3 according to the operating frequency as shown in FIG. 2, the drive circuits 2a, 2b, 2c are sequentially arranged. May be driven to control the transient current to reduce noise. That is,
As shown in FIG. 3, when the rising edges of the control signals C1, C2, C3 are matched, a large transient current flows at once in the drive circuits 2a, 2b, 2c as indicated by symbol B, so that relatively large power supply noise and radiation noise are generated. Although generated, if the rising timings of the control signals C1, C2, C3 are shifted as shown in FIG. 2, the drive circuits 2a, 2b, 2c are driven in order, and the peak of the transient current becomes small as indicated by symbol A. It can be suppressed.

Therefore, when high speed operation is not required,
By shifting the rising timings of the control signals C1, C2, C3 as shown in FIG. 2, power supply noise and radiation noise can be reduced. In addition, by combining both the method of changing the number of drive circuits driven at the same time and the method of shifting the rising timings of the control signals C1, C2, C3,
Change the number of drive circuits to operate according to the size of the load,
In addition, it is possible to control the transient current according to the operating frequency. FIG. 4 shows an example in which two drive circuits 2a and 2b out of the three drive circuits are selected as one example of the waveforms of the control signals C1, C2, and C3 in that case, and the drive circuits are driven at different timings.

FIG. 5 shows a specific circuit configuration example of the output control circuit 3. That is, the output control circuit 3 includes a NAND gate G1 which receives the mode specifying signals MD0, MD1 and MD2 supplied from an external terminal or a mode setting circuit (not shown) as input signals, and a mode specifying signal M.
Drive circuits 2a, 2 which are composed of an inverter INV for inverting D2 and constitute the data output circuit shown in FIG.
Control signals C1, C2 and C3 for b and 2c are formed. The following table 1 shows the mode designating signals MD0, MD1,
An example of the relationship between MD2 and control signals C1, C2, C3 is shown.

[Table 1] In Table 1 above, modes 1 and 3 and modes 5 and 7 are shown.
Shows an example in which the output circuits have the same load driving force.

As described above, according to the present invention, since a plurality of drive circuits for one external signal line are provided and each of them can operate individually, the drive capability of the data output circuit of the integrated circuit can be controlled by the operating frequency. The peak value of transient current, which causes noise, is significantly reduced during low-speed operation compared to when operating at the maximum operating frequency by setting it to the minimum required according to It is possible to prevent adverse effects such as deterioration in accuracy of the circuit or various analog circuits installed in the periphery and malfunction of the circuit. In addition, it is possible to reduce radiation noise generated outside the chip and reduce adverse effects on various electronic devices installed in the periphery.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, all or part of the mode designating signals MD0, MD1, MD2 in FIG. 5 may be replaced with a signal according to the state held in the register or the memory. Further, when the drive circuit forming the output circuit is formed of a CMOS circuit, a P-channel MOSFET and an N-channel MOSFET are used.
By shifting the on / off timing with and,
It is also possible to suppress the transient current.

[0016]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. In other words, during low-speed operation, the peak value of transient current that causes noise can be significantly reduced compared to when operating at the maximum operating frequency, and it can be incorporated into integrated circuits or various analog circuits installed in the periphery. It is possible to prevent adverse effects such as deterioration in accuracy and malfunction of circuits, reduce radiation noise generated outside the chip, and reduce adverse effects on various electronic devices installed in the periphery.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data output circuit according to the present invention.

FIG. 2 is a timing diagram showing an example of timing of control signals for controlling a drive circuit of the data output circuit of FIG.

FIG. 3 is a timing chart showing the timing of control signals when the data output circuit of FIG. 1 is operated with the maximum drive capacity.

FIG. 4 is a timing diagram showing another example of timing of control signals for controlling the drive circuit of the data output circuit of FIG.

FIG. 5 is a logic circuit diagram showing a specific circuit configuration example of an output control circuit.

[Explanation of symbols]

 1 External output terminals 2a, 2b, 2c Data output circuit drive circuit 3 Output control circuit

Claims (3)

[Claims] 1. A plurality of drive circuits are provided corresponding to one external signal line, and a control means is provided to control whether these drive circuits are enabled or disabled. Data output circuit. 2. Data comprising a plurality of drive circuits provided corresponding to one external signal line, and a timing control circuit for determining an operation timing of these drive circuits. Output circuit. 3. A data output circuit comprising one or more external output terminals, a plurality of drive circuits provided corresponding to each external output terminal, and enabling or disabling each of the drive circuits. Or a timing control circuit for determining the operation timing of the drive circuit.