JPH05211172A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form the distance between an ohmic electrode, which is connected to N-type high-concentration layers, and a recess in a small and stable process in an extent that a failure of a gate breakdown strength is not caused and to contrive a reduction in a series resistance in a GaAs FET of a recess structure. CONSTITUTION:Ions are implanted in a semi-insulative gallium-arsenic substrate 1 to form an N-type active layer 2 and thereafter, a silicon oxide film 3 is deposited, the film 3 is etched using a photoresist 4 as a mask and a side etching 6 is performed by a prescribed distance. Then, N-type high-concentration layers 5 are formed by ion-implantation and after a silicon nitride film 7 is deposited, the film 7 is etched using the photoresist 4 as a mask and the film 3 is subjected to wet etching. Then, a wet etching is performed using the film 7 as a mask to form a recess 8. Then, a gate metal film 9 is deposited to lift off. Thereby, a GaAs FET is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a gallium arsenide field effect transistor (GaA).
(sFET) manufacturing method.

[0002]

2. Description of the Related Art A conventional method for manufacturing a GaAs FET will be described.

First, an N-type active layer is formed on a semi-insulating gallium arsenide substrate by ion implantation, followed by ion implantation using a photoresist as a mask and annealing to form a high-concentration N-type layer for reducing contact resistance. ..

Next, after depositing a silicon nitride film or a silicon oxide film, the silicon oxide film or the silicon nitride film is side-etched by a predetermined distance by dry etching or wet etching using a photoresist as a mask.

Next, the N-type active layer on the surface of the substrate is etched to form a recess having a predetermined depth. Next, a gate metal is deposited using one of a photoresist, a silicon oxide film, and a silicon nitride film as a mask, and then lifted off to form a gate electrode, thereby completing the element portion.

GaAs FET formed in this way
Then, the positions of the high-concentration N-type layer, the gate electrode, and the recess are determined by patterning the respective photoresists.

[0007]

[Problems to be Solved by the Invention] Conventional GaAs FET
In the manufacturing method of 1., the positions of the high-concentration N-type layer, the gate electrode, and the recess are determined by patterning the respective photoresists. Therefore, due to misalignment of patterning,
The fluctuation of the distance between the high-concentration N-type layer and the gate electrode or recess is large.

In order to reduce the series resistance, it is preferable that the high-concentration N-type layer connected to the source electrode and the gate electrode are as close as possible, but there is a problem that the gate breakdown voltage is lowered if they are too close to each other.

[0009]

According to a method of manufacturing a semiconductor device of the present invention, an N-type active layer is formed on one main surface of a semi-insulating gallium arsenide substrate by ion implantation, and then a silicon oxide film is deposited on the entire surface. A step of forming a first photoresist pattern having an ohmic electrode planned region as an opening, and a step of wet-etching the silicon oxide film using the first photoresist as a mask and side-etching a predetermined distance. A step of forming a high concentration N-type layer by ion implantation using the first photoresist as a mask, a step of performing a heat treatment after removing the first photoresist, a silicon nitride film is deposited on the entire surface, and a gate is formed. A step of forming a second photoresist pattern having an opening in the electrode planned region; and using the second photoresist as a mask, A step of dry etching the silicon oxide film and then completely removing the silicon oxide film by wet etching; and a step of etching the N-type active layer using the silicon nitride film as a mask to form a recess of a predetermined depth. And a step of depositing a gate metal by using the second photoresist or the silicon nitride film as a mask to form a gate electrode made of the gate metal.

[0010]

EXAMPLE FIG. 1A shows a first example of the present invention.
This will be described with reference to (c).

First, as shown in FIG. 1A, ions are implanted into a semi-insulating gallium arsenide substrate 1 to form an N-type active layer 2. Next, a 100-nm-thick silicon oxide film 3 is deposited on the entire surface, and the photoresist 4 is used as a mask in a ratio of 1: 6.
The silicon oxide film 3 is etched with the buffered hydrofluoric acid and the side etching 6 is performed for a predetermined distance. Next, a high concentration N-type layer 5 is formed by ion implantation, and then the photoresist 4 is peeled off with an organic solvent and annealed.

Next, as shown in FIG. 1B, a silicon nitride film 7 having a thickness of 150 nm is deposited on the entire surface, and the silicon nitride film 7 is dry-etched using the photoresist 4 as a mask. The silicon oxide film 3 is etched with buffered hydrofluoric acid.

At this time, since the silicon nitride film 7 has a low etching rate, it is hardly attacked by buffered hydrofluoric acid.

Next, using the silicon nitride film 7 as a mask, etching is performed with a mixed solution of sulfuric acid: hydrogen peroxide: water = 1: 8: 600 to form a recess 8 having a predetermined depth, and a thickness of 50 nm.
A gate metal 9 made of Ti and Al having a thickness of 100 nm is deposited.

Next, as shown in FIG. 1C, an unnecessary gate metal 9 is formed together with the photoresist 4 by an organic solvent.
Is lifted off to complete the element portion of the GaAs FET.

Next, a second embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 2A, an N-type active layer 2 is formed on a semi-insulating gallium arsenide substrate 1 by ion implantation or epitaxial growth, and then a silicon oxide film 3 is deposited. Next, as in the first embodiment, the silicon oxide film 3 is etched with a buffered hydrofluoric acid of 1: 6 using a photoresist as a mask, and side etching 6 is performed for a predetermined distance. After depositing 40 nm of ohmic metal 10 made of Ni, lift-off and alloying are performed.

Next, as shown in FIG. 2B, a silicon nitride film 7 is deposited, the silicon nitride film 7 is dry-etched using the photoresist 4 as a mask, and then the silicon oxide film 3 is wet-etched. Next, a recess 8 is formed by etching using the silicon nitride film 7 as a mask, and then a gate metal 9 is deposited.

Next, as shown in FIG. 2C, the unnecessary gate metal 9 is lifted off together with the photoresist 4 to complete the element portion of the GaAs FET.

[0020]

The distance between the high-concentration N-type layer and the gate electrode can be determined by the side etching distance of the silicon oxide film. Furthermore, the position of the recess with respect to the ohmic electrode can be accurately determined.

In order to reduce the series resistance, it becomes possible to bring the high-concentration N-type layer connected to the source electrode and the gate electrode close to each other without causing breakdown voltage failure.
A stable recess process has been realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in process order.

[Explanation of symbols]

 1 Semi-insulating gallium arsenide substrate 2 N-type active layer 3 Silicon oxide film 4 Photoresist 5 High concentration N-type layer 6 Side etching 7 Silicon nitride film 8 Recess 9 Gate metal 10 Ohmic metal

Claims (1)

[Claims] 1. A first photoresist in which an N-type active layer is formed on one main surface of a semi-insulating gallium arsenide substrate by ion implantation, and then a silicon oxide film is deposited on the entire surface to form an ohmic electrode planned region as an opening. A step of forming a pattern,
Wet etching the silicon oxide film using the first photoresist as a mask and side etching a predetermined distance, and forming a high concentration N-type layer by ion implantation using the first photoresist as a mask. A step of performing a heat treatment after removing the first photoresist, and depositing a silicon nitride film on the entire surface,
A step of forming a second photoresist pattern having an opening in a gate electrode planned region, and dry etching the silicon nitride film using the second photoresist as a mask, and then completely etching the silicon oxide film by wet etching. A step of removing, a step of etching the N-type active layer with the silicon nitride film as a mask to form a recess having a predetermined depth, and a step of removing the gate metal with the second photoresist or the silicon nitride film as a mask. A step of depositing to form a gate electrode made of the gate metal.