JPH05210920A - Error correction circuit - Google Patents

Abstract

PURPOSE:To reduce the erroneous correction of C2 correction by forcibly setting an error flag at the time of erroneous segment reproducing. CONSTITUTION:The reproduced segment number passing an address detecting circuit 1 and a reproduced segment number generating circuit 2 is compared with the segment number from a reference segment number generating circuit 3 by a segment number comparing circuit 4, and a noncoincidence signal is outputted from the circuit 4 in the case of erroneous segment reproducing. Data which does not form a code word is outputted from a reproduced data conversion circuit 5 by this output, and the error flag is outputted from a C1 correction circuit 6, and write to an essential write area of a buffer memory circuit 7 is inhibited, and the error flag is written in an area other than the essential write area. The error flag is forcibly written in all of the essential write area of the circuit 7 after the completion of read of a C2 correction circuit 8, and the frequency in erroneous correction of C2 correction is reduced to improve the C2 correction capability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction circuit included in a reproducing system circuit of a magnetic recording apparatus capable of recording / reproducing digital data using a rotary head, and more particularly to a generation direction of a C1 correction code used for error correction. And a device in which the data recording directions on the recording medium are the same and the segment recording is performed.

[0002]

2. Description of the Related Art In a digital data recording apparatus, a data error occurs during reproduction due to the effects of dust, scratches, intersymbol interference, etc. attached to a recording medium. Therefore, by adding an error correction code to the data you want to record, you can perform error correction using that redundancy during playback,
The reliability of the reproduction data is improved.

The error correction codes are DAT and digital VT.
In various VTRs and the like capable of recording R and PCM voices, many devices employ the Reed-Solomon code. In general, the correction code is applied twice or more by changing the direction of code generation. In a recording / reproducing apparatus such as a VTR, the inner code is a recording direction to a recording medium in consideration of slow reproduction and high-speed reproduction. It is often hung in the same direction as.

In a device for recording a signal having a large amount of information as seen in a high definition VTR or the like, one field of a video signal is recorded in one track as seen in a conventional TV system home VTR or the like. Since it is impossible to assign to each track, a method called segment recording is used in which a video and audio signal for one field is divided into two or more tracks and recorded.

FIG. 1 shows an example of 1-field 3-segment recording. When the device is operating normally, the signal recorded in the first segment is not reproduced in the second segment during the first segment reproduction period.
The signal recorded in the segment is reproduced in the second segment reproduction period, and the signal recorded in the third segment is reproduced in the third segment reproduction period. SCK
Indicates a segment clock signal which serves as a reference signal for the rotational phase of the rotary head. FCK represents a frame clock signal that serves as a reference for the operation of the VTR device.

FIG. 2 shows a state in which another track is being reproduced while deviating from the track to be originally reproduced. This situation occurs when the tracking adjustment is wrong or when playing incompatible tape. It can also happen temporarily when playing a heavily damaged tape. Moreover, this state also transits transiently when the tape reproduction state is changed to the normal reproduction state from the stopped state.

FIG. 3 shows an example of a data block to which an error correction code is added. First, data input during a certain one-field period is accumulated, and a C2 correction code is added to this data in the direction shown in the figure. C in the direction shown
1 Add error correction code. Next, the sync signal and the address data are added in the direction in which the C1 correction code is generated. At this time, values 0 to n (n is an integer) are sequentially given as address data from the left.

FIG. 4 shows the contents of the data forming the data block shown in FIG. FIG. 5 shows an example of dividing the data block of FIG. 3 into three segments. Here, the data frame of FIG.
It shall be assigned to the segment of the value obtained by mod 3) +1. The segmented data string shall be recorded on the tape in the order shown by the arrow.

In reproducing the data recorded in the above-mentioned format, when the bit error rate is low enough not to be uncorrectable by the C1 correction, if the signal of another segment is mistakenly reproduced during a certain segment period, the C1 correction is performed. In the error correction by the code, the generation direction of the C1 correction code coincides with the recording direction on the track, so that there is no error or correction is possible.

Next, when the erasure correction by the C2 correction code is executed by using the error flag obtained as a result of the error correction by the C1 correction code, the segment is erroneously reproduced, so that it is input to the C2 correction circuit. Not only does the data become a data sequence different from the sequence in which the C2 correction code is generated at the time of recording, but the error flag added to each symbol does not indicate an error. FIG. 6 shows the data arrangement for one field when the segment is erroneously reproduced as in the example shown in FIG. The data one field before the data not shaded is input to the shaded portion shown. EFO-EFn is C
1 shows the arrangement of error flags by 1 correction.

When the data having the arrangement shown in FIG. 6 is erasure-corrected by using the C2 correction code and the error flag by the C1 correction, the C2 correction circuit has no error flag indicating that it is an error symbol, and the code word Data columns that do not
Alternatively, a data string that is a codeword is accidentally input. FIG. 7 shows an example of a data string input to the C2 correction circuit. The shaded data indicates data different from the data for which the C2 correction code is generated.

[0012]

As described above, in the error correction circuit of the apparatus in which the direction of generation of the C1 correction code used for error correction coincides with the direction of data recording on the recording medium and the segment recording is performed, When C2 erasure correction is performed on data that may be reproduced due to a segment error, the error flag obtained as a result of C1 correction cannot be relied on, and erasure correction capability is available in C2 correction. To reduce the probability of error detection error, or to perform erasure correction up to the number possible with the C2 correction code while leaving the possibility of erroneous correction.

[0013]

A first configuration provided by the present invention is an error correction code (hereinafter, referred to as a first parity).
C1 correction code) and then a second parity error correction code (hereinafter, C1 correction code) is added to the first data block having a product code configuration to which the C1 correction code is added. N second data blocks (here, n = 2, 3, 4) in which each data frame is a unit of at least a synchronization signal and unique address data.
, N), and the data frames forming the segments are assigned to and recorded on one track on the magnetic tape or an arbitrary part of one track by the rotary head according to a predetermined order. An error correction circuit in a signal processing circuit on the reproducing side of a digital data recording / reproducing apparatus for obtaining a first segment number to which a frame to which the address data is added belongs from address data obtained from the reproduced signal. A number generation circuit, a second segment number generation circuit that obtains the number of the second segment by inputting the reference phase signal inside the device that is synchronized with the rotation phase reference signal of the rotary drum, the first segment number, and the second segment number. Segment number comparison circuit that performs comparison with the segment number of the The output of the instrument number comparison circuit first
Data conversion circuit for converting reproduced codeword data to which the C1 correction code is added to data that does not form a codeword when indicating that the segment number of No. 1 and the second segment number do not match, and the output of the data conversion circuit As input,
An error correction circuit comprising: a first error correction circuit that executes error correction using a C1 correction code.

A second means provided by the present invention is to add an error correction code which is the first parity (hereinafter, C2 correction code), and then add an error correction code which is the second parity (hereinafter, C1 correction code). ) Is added to the first data block to form a product code, and the first data block is formed of a data frame in which at least a synchronization signal and unique address data are combined for each code word to which the C1 correction code is added. The second data block is divided into n (here, n = 2, 3, 4, ..., N) segments using the data frame as a unit, and the data frames forming the segment are rotated in a predetermined order. A signal processing circuit on the reproducing side of a digital data recording / reproducing apparatus for recording by allocating to one track on a magnetic tape or an arbitrary part of one track by a head. A first segment number generation circuit for obtaining the first segment number to which the frame to which the address data is added from the address data obtained from the reproduction signal, and the rotation phase reference signal of the rotary drum. A second segment number generation circuit that obtains the number of the second segment by inputting the synchronized reference phase signal inside the device; and a segment number comparison circuit that compares the first segment number and the second segment number. As a result of error correction using the C1 correction code, at least a second error correction circuit having a function of outputting an error flag indicating that correction is impossible, and the first segment number and the second segment number are When indicating that they do not match, the error flag output from the first error correction circuit is changed to a state indicating that it cannot be corrected. And error flag conversion circuit for conversion, an error correction circuit, characterized in that and a third error correction circuit executable of erasure correction due C2 correction code.

A third configuration provided by the present invention is to add an error correction code which is the first parity (hereinafter, C2 correction code), and then add an error correction code which is the second parity (hereinafter, C1 correction code). ) Is added to the first data block to form a product code, and the first data block is formed of a data frame in which at least a synchronization signal and unique address data are combined for each code word to which the C1 correction code is added. The second data block is divided into n (here, n = 2, 3, 4, ..., N) segments using the data frame as a unit, and the data frames forming the segment are rotated in a predetermined order. A signal processing circuit on the reproducing side of a digital data recording / reproducing apparatus which allocates and records to one track on a magnetic tape or an arbitrary part of one track by a head. A first segment number generation circuit for obtaining the first segment number to which the frame to which the address data is added from the address data obtained from the reproduction signal, and the rotation phase reference signal of the rotary drum. A second segment number generation circuit that obtains the number of the second segment by inputting the synchronized reference phase signal inside the device; and a segment number comparison circuit that compares the first segment number and the second segment number. As a result of error correction using the C1 correction code, at least a second error correction circuit having a function of outputting an error flag indicating that it is uncorrectable and data error-corrected by the second error correction circuit First to store once
Buffer memory circuit, a second buffer memory circuit for temporarily storing the error flag output from the second error correction circuit, and the second error correction circuit outputs to the first buffer memory circuit. A first write address generation circuit that generates an address for writing corrected data, and a second write address that generates an address for writing an error flag output from the second error correction circuit to the second buffer memory circuit. When the outputs of the write address generation circuit and the segment number comparison circuit are input to indicate that the first segment number and the second segment number do not match, the address output by the third address generation circuit An address for converting a signal into an address number not used by the second buffer memory circuit A replacement circuit, a third error correction circuit capable of performing erasure correction using a C2 correction code by reading the data of the first buffer memory circuit and the error flag of the second buffer memory circuit, and the first buffer circuit. Of the second buffer memory circuit and the second buffer memory circuit, after reading the data and the error flag according to the generation sequence of the C2 correction code, at least the address of the second buffer memory circuit from which the error flag is read,
An error correction circuit comprising: a flag write circuit for writing a logic level indicating an error.

According to a fourth structure provided by the present invention, after adding an error correction code which is a first parity (hereinafter, C2 correction code), an error correction code which is a second parity (hereinafter, C1 correction code) is added. ) Is added to the first data block to form a product code, and the first data block is formed of a data frame in which at least a synchronization signal and unique address data are combined for each code word to which the C1 correction code is added. The second data block is divided into n (here, n = 2, 3, 4, ..., N) segments using the data frame as a unit, and the data frames forming the segment are rotated in a predetermined order. A signal processing circuit on the reproducing side of a digital data recording / reproducing apparatus which allocates and records to one track on a magnetic tape or an arbitrary part of one track by a head. A first segment number generation circuit for obtaining the first segment number to which the frame to which the address data is added from the address data obtained from the reproduction signal, and the rotation phase reference signal of the rotary drum. A second segment number generation circuit that obtains the number of the second segment by inputting the synchronized reference phase signal inside the device; and a segment number comparison circuit that compares the first segment number and the second segment number. As a result of error correction using the C1 correction code, at least a second error correction circuit having a function of outputting an error flag indicating that it is uncorrectable and data error-corrected by the second error correction circuit First to store once
And a second buffer memory circuit for temporarily storing the error flag output from the second error correction circuit.
Buffer memory circuit, a first write address generation circuit for generating an address for writing the corrected data output from the second error correction circuit to the first buffer memory circuit, and the second buffer A second write address generation circuit that generates an address for writing an error flag output from the second error correction circuit to a memory circuit, and the output of the segment number comparison circuit as an input, and the first segment number And the second segment number match, the error flag write signal output from the second error correction circuit is output to the second buffer memory. A buffer memory write control circuit having a function of not outputting a write signal; The data of the buffer memory circuit and the error flag of the second buffer memory circuit are read, and a third error correction circuit capable of erasure correction using a C2 correction code, the first buffer memory circuit and the second buffer After reading the data and the error flag from the buffer memory circuit in accordance with the generation sequence of the C2 correction code, at least the error flag of the second buffer memory circuit is written on the address at which the logic level indicating the error is written. An error correction circuit comprising a writing circuit.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the drawings. Embodiment (1) FIG. 8 is a block diagram showing an embodiment of the invention shown in claim 1. FIG. 9 shows an example of a timing chart of the reference segment number generation circuit, FIG. 10 shows an example of a data frame, FIG. 11 shows an example of the timing chart of this embodiment, and FIG. 12 shows a C1 correction circuit 6 used for error correction. An example of the generated contents of the error code is shown below.

The address detection circuit 1 detects the position of the synchronization signal SYNC inserted in the input signal DIN, and S
Address data ADRS is detected and output based on the phase of YNC.

The reproduction segment number generation circuit 2 receives the address number ADRS detected by the address detection circuit 1 as an input and obtains and outputs the segment number PSEG to which the data frame of the address data ADRS belongs. It is assumed that the relationship between the address data and the segment number is known in advance.

Reference segment number generation circuit 3
Receives the field clock FCK and the segment clock SCK, which are the operation reference phase signals of the apparatus, and obtains and outputs the segment number RSEG which should be currently reproduced.

The segment number comparison circuit 4 receives the segment number PSEG and the segment number RSEG as input, compares the two numbers, and outputs a comparison signal COMP. C
OMP is a logic level "H" when the comparison result does not match.
When they match, it becomes "L".

The reproduction data conversion circuit 5 receives the input signal DIN.
And the comparison signal COMP are input, when the comparison signal COMP or "H", the code word data portion of the data frame to which the address data detected by the address detection circuit 1 is added is converted into a data string that does not form a code word. , Comparison signal C
When the OMP indicates coincidence, the input signal DIN is output without conversion.

An example in which the comparison signal COMP is "H" is shown in the nth data frame. For simplification, it is assumed that there is no data error before and after the nth frame.

The comparison signal COMP is "H", that is, RSE.
When G and PSEG do not match, it is assumed that data that does not form a code word in the code example shown in FIG. 12, that is, all symbols are converted to "FF" in this embodiment. FIG. 13 shows an example of a circuit for realizing this. DOUT represents the output.

The C1 correction circuit 6 is a reproduction data conversion circuit 5
Error correction is executed using the error correction code added to the data output by. Further, the C1 correction circuit 6 is assumed to have a function of outputting an error flag EF indicating that the error cannot be corrected if the result of the error correction is that the error cannot be corrected. The error flag EF is "H" when it cannot be corrected.
Suppose you reach a level.

Since all the symbols of the nth data frame have been converted to "FF" in the reproduction data conversion circuit 5, the C1 correction circuit 6 cannot correct and the error flag EF becomes "H".

The buffer memory circuit 7 accumulates the data and the error flag which have been error-corrected by the C1 correction circuit 6 for a certain period of time and reads them out at a predetermined timing in accordance with the generation sequence of the C2 correction code.

The C2 correction circuit 8 is an error correction circuit capable of erasure correction by referring to an error flag input from the buffer memory circuit 7 according to the C2 series, together with the data.

Embodiment (2) FIG. 14 is a block diagram showing an embodiment of the present invention as defined in claim 2. FIG. 15 shows an example of a timing chart of this embodiment.

The contents of generation of codes used for error correction in the C1 correction circuit 13 and the C2 correction circuit 16 are the same as those in FIG. 12 used in the embodiment (1).

The address detection circuit 9 is a circuit that performs the same operation as in the embodiment (1).

The reproduction segment number generation circuit 10 is a circuit which performs the same operation as that of the embodiment (1).

Reference segment number generation circuit 11
Is a circuit that performs the same operation as the circuit of the embodiment (1).

The segment number comparison circuit 12 is a circuit that performs the same operation as in the embodiment (1).

The C1 correction circuit 13 receives the input signal DIN and executes error correction using the error correction code added to DIN. Further, the C1 correction circuit 13 has a function of outputting an error flag EF indicating that the error cannot be corrected if the result of the error correction is that the error cannot be corrected. It is assumed that the error flag EF becomes "H" level when it cannot be corrected.

The error flag conversion circuit 14 receives the error flag EF output from the C1 error revision circuit 13 and the output COMP of the segment number comparison circuit 12 as input, and the COMP
Is a circuit for converting the input error flag EF to an "H" level, that is, a level indicating uncorrectable, regardless of its logical level when is "H" level. FIG. 16 shows an example of a circuit for realizing this. EFO stands for output.

The buffer memory circuit 15 is a circuit that performs the same operation as that of the embodiment (1). C2 correction circuit 1
Reference numeral 6 is a circuit that performs the same operation as that of the embodiment (1).

Embodiment (3) FIG. 17 is a block diagram showing an embodiment of the present invention as defined in claim 3. 18 shows an example of a timing chart, and FIG. 19 shows an example of specifications of addresses of a memory included in the flag buffer circuit 25.

The contents of generation of codes used for error correction in the C1 correction circuit 21 and the C2 correction circuit 27 are the same as those in FIG. 12 used in the embodiment (1).

The address detection circuit 17 is a circuit which performs the same operation as in the embodiment (1).

The reproduction segment number generation circuit 18 is a circuit which performs the same operation as in the embodiment (1).

Reference segment number generation circuit 19
Is a circuit that performs the same operation as the circuit of the embodiment (1).

The segment number comparison circuit 20 is a circuit which performs the same operation as in the embodiment (1).

The C1 correction circuit 21 is a circuit which performs the same operation as in the embodiment (2).

Corrected data write address generation circuit 22
Is the address data A output from the address detection circuit 17.
It is a circuit that receives the DRS as an input and generates an address for writing the data corrected by the C1 correction circuit 21 into a predetermined address of the data buffer circuit 23.

Correction flag write address generation circuit 24
Is the address data A output from the address detection circuit 17.
It is a circuit having a function of generating an address signal EFAD for writing an error flag indicating a correction result of the input signal DIN corrected by the C1 correction circuit 21 at a predetermined address of the flag buffer circuit 25 by using DRS as an input.

The flag write address generation circuit 26
This is a circuit for generating all the addresses read by the flag buffer circuit 25 in an arbitrary order.

The correction flag address conversion circuit 28 normally outputs the address signal EFAD from the correction flag write address generation circuit 24 as it is, but when the output COMP of the segment comparison circuit 20 is "H", the flag buffer circuit 25 outputs. This is a circuit that converts to an unused address number. In FIG. 18, all bits are converted into an address of "H". The output address is EFADX. Figure 2
An example of a circuit for realizing 0 is shown.

The data buffer circuit 23 uses the C2 correction circuit 27 to convert the data corrected by the C1 correction circuit 21 into C data.
2 It is a memory that can be stored until it is corrected.

The flag buffer circuit 25 uses the error flag obtained as a result of the correction by the C1 correction circuit 21 as C2.
This is a memory that can be stored until the correction circuit 27 performs C2 correction. It has a region as shown in FIG. FIG. 21 shows addresses given to the areas 0 and 1. The area 0 is an area in which an error flag obtained as a result of error correction of the input signal DIN input during the period when the video frame signal is at "L" level is written by the C1 correction circuit 21. The area 1 is an area in which an error flag obtained as a result of error correction of the input signal DIN input during the period when the video frame signal is at the “H” level by the C1 correction circuit 21 is written. The area 0 and the area 1 are configured to be independently writable and readable. Area 2 indicates an area where the error flag obtained as a result of error correction in the C1 correction circuit 21 is not written. Further, the flag buffer circuit 25 is assumed to operate so that the “H” level data is written at the address designated by the flag write address generation circuit 26 instead of the error flag from the C1 correction circuit 21.

The C2 correction circuit 27 stores the data written when the video frame signal of the data buffer circuit 23 is at the "H" level when the video frame signal is at the "L" level together with the error flag of the area 1 of the flag buffer circuit 25. When the video frame signal is read, the video frame signal of the data buffer circuit 23 is "H" when the video frame signal is at "L" level.
This is an error correction circuit capable of performing erasure correction by a C2 correction code by reading the data written at the time of the level together with the error flag of the area 0 of the flag buffer circuit 25.

The flag address selection circuit 29 is a circuit for selecting the address signal from the correction flag address conversion circuit 28 and the address signal from the flag write address generation circuit 26. When the video frame signal is at "L" level, the address signal from the correction flag address conversion circuit 28 is sent to the area 0 of the flag buffer circuit 25, and when the video frame signal is at "H" level, the flag write address generation circuit 26 Address signal to C2 correction circuit 2
7 reads the data for C2 correction from area 0 and sends it to area 0. When the video frame signal is "H" level, the address signal from the correction flag address conversion circuit 28 is sent to the area 1 of the flag buffer circuit 25, and when the video frame signal is "L" level, the flag write address generation circuit 26 outputs the address signal. Address signal to C2 correction circuit 2
7 reads the data for C2 correction from area 1 and sends it to area 1.

That is, the correction flag address conversion circuit 28
Is configured to convert the comparison signal output from the segment number comparison circuit 20 into an arbitrary address in the area 2 when COMP is at "H" level, and when the segment does not match, the error of the C1 corrected data is generated. Even if the flag is "L", the error flag specifies an address in an unused area different from the original address and the error flag is "H" for the area of the flag buffer circuit for which the C2 correction has been completed. Since the level is written, the error flag is set when the C2 correction circuit 27 reads the data.

Embodiment (4) FIG. 22 is a block diagram showing an embodiment of the present invention as defined in claim 4. FIG. 23 shows an example of a timing chart of this embodiment.

The generated contents of the codes used for error correction in the C1 correction circuit 34 and the C2 correction circuit 42 are the same as those in FIG. 12 used in the embodiment (1).

The address detection circuit 30 is a circuit which performs the same operation as that of the embodiment (1).

The reproduction segment number generation circuit 31 is a circuit which performs the same operation as in the embodiment (1).

Reference segment number generation circuit 32
Is a circuit that performs the same operation as the circuit of the embodiment (1).

The segment number comparison circuit 33 is a circuit which performs the same operation as in the embodiment (1).

The C1 correction circuit 34 is a circuit which performs the same operation as that of the embodiment (2).

Corrected data write address generation circuit 35
Is a circuit that performs the same operation as that of the embodiment (3).

Correction flag write address generation circuit 36
Is a circuit that performs the same operation as that of the embodiment (3).

The flag write address generation circuit 37 is
The circuit is the same as that of the embodiment (3). The data buffer circuit 41 is a circuit that performs the same operation as that of the embodiment (3). The flag buffer circuit 39 is a circuit that performs the same operation as that of the embodiment (3).

Flag buffer write control circuit 38
Outputs a signal that permits writing of the correction flag from the C1 correction circuit 34 to the flag buffer circuit 39, but outputs a signal that does not permit this when the output COMP of the segment comparison circuit 33 is "H". Is.

In the timing chart of FIG. 22, when the inversion WE is "L", the writing is permitted, and when it is "H", the writing is not permitted.

FIG. 23 shows an example of a circuit for realizing this. Reference numeral 44 is a circuit that outputs an "L" level when the flag write address generation circuit 37 generates an address signal.

The flag address selection circuit 40 is a circuit for selecting the address signal from the correction flag write address generation circuit 36 and the address signal from the flag write address generation circuit 37. Video frame signal is "L"
At the level, the correction flag write address generation circuit 36
Address signal from the flag buffer circuit 39 to the area 0 of the flag buffer circuit 39. After reading the data for correction, it is sent to area 0. When the video frame signal is "H" level, the address signal from the correction flag write address generation circuit 36 is sent to the area 1 of the flag buffer circuit 39, and when the video frame signal is "L" level, the flag write address generation circuit 37. Address signal of the C2 correction circuit 42
Reads out the data for C2 correction from the area 1 of the flag buffer circuit 39 and sends it to the area 1.

That is, the flag buffer write control circuit 38 writes the error flag from the C1 correction circuit 34 to the flag buffer circuit 39 when the comparison signal COMP output from the segment number comparison circuit 33 is at "H" level. The error flag of the C1 corrected data is "L" when the segment mismatch does not occur.
However, since the error flag "H" level is written in the area of the flag buffer circuit where the C2 correction is completed, the error flag is set when the C2 correction circuit 42 reads the data.

[0069]

As described above, according to the present invention,
In the C2 erasure correction of a data block in which a segment is reproduced by mistake, an error flag can be set at the time of reading the C2 correction for a symbol that originally cannot be detected by the C1 correction. It has the effect of reducing the probability of erroneous correction.

[Brief description of drawings]

FIG. 1 is a diagram showing 1-field 3-segment recording.

FIG. 2 is a diagram showing a state in which another track is being reproduced, being deviated from the track to be originally reproduced.

FIG. 3 is a diagram showing an example of a data block to which an error correction code is added.

FIG. 4 is a diagram showing the contents of data forming the data block shown in FIG.

5 is a diagram showing an example of dividing the data block of FIG. 3 into three segments.

FIG. 6 is a diagram showing a data arrangement for one field when a segment is erroneously reproduced as shown in FIG.

FIG. 7 is a diagram showing an example of a data string input to a C2 correction circuit.

FIG. 8 is a block diagram of an embodiment (1).

FIG. 9 is a timing chart of a reference segment number generation circuit.

FIG. 10 is a diagram showing an example of a data frame.

FIG. 11 is a timing chart of the embodiment (1).

FIG. 12 is a diagram showing an example of generation contents of an error correction code.

FIG. 13 is a diagram showing an example of implementation of the reproduction data conversion circuit 5.

FIG. 14 is a block diagram of an embodiment (2).

FIG. 15 is a timing chart of the embodiment (2).

FIG. 16 is a diagram showing an embodiment of an error flag conversion circuit.

FIG. 17 is a block diagram of an embodiment (3).

FIG. 18 is a timing chart of the embodiment (3).

FIG. 19 is a diagram showing specifications of a memory address of a flag buffer circuit.

FIG. 20 is a diagram showing one implementation example of a correction flag address conversion circuit 28.

FIG. 21 is a region 0 and a region 1 of the flag buffer circuit 25.
The figure showing the address given to the.

FIG. 22 is a block diagram of an embodiment (4).

FIG. 23 is a timing chart of the embodiment (4).

FIG. 24 is a diagram showing one implementation circuit of a flag buffer write control circuit 38.

Claims (4)

[Claims] 1. A product code configuration in which an error correction code (hereinafter, C2 correction code) that is a first parity is added, and then an error correction code (hereinafter, C1 correction code) that is a second parity is added. And a second data block formed of a data frame formed by combining at least a synchronization signal and unique address data for each code word formed by adding the C1 correction code to the data block. N units (where n =
2, 3, 4 ..., N), and the data frame forming the segment is divided into one track on the magnetic tape by the rotary head or any one of the tracks in one track according to a predetermined order. An error correction circuit in a signal processing circuit on the reproducing side of a digital data recording / reproducing apparatus which allocates and records to a part, and which determines the first segment number to which the frame to which the address data is added belongs from the address data obtained from the reproduced signal. A first segment number generation circuit for obtaining, a second segment number generation circuit for obtaining the number of the second segment by inputting a reference phase signal inside the apparatus synchronized with the rotation phase reference signal of the rotary drum, and a first segment A segment number comparison circuit for comparing the number with the second segment number, and an output of the segment number comparison circuit. As a force, when the output of the segment number comparison circuit indicates that the first segment number and the second segment numbers do not match, C
A data conversion circuit for converting reproduced codeword data to which 1 correction code is added into data which does not form a codeword, and a first error which receives an output of the data conversion circuit as an input and executes an error correction by a C1 correction code. An error correction circuit comprising a correction circuit. 2. A product code structure in which an error correction code (hereinafter, C2 correction code) that is a first parity is added and then an error correction code (hereinafter, C1 correction code) that is a second parity is added. And a second data block formed of a data frame formed by combining at least a synchronization signal and unique address data for each code word formed by adding the C1 correction code to the data block. N units (where n =
2, 3, 4 ..., N), and the data frame forming the segment is divided into one track on the magnetic tape by the rotary head or any one of the tracks in one track according to a predetermined order. An error correction circuit in a signal processing circuit on the reproducing side of a digital data recording / reproducing apparatus which allocates and records to a part, and which determines the first segment number to which the frame to which the address data is added belongs from the address data obtained from the reproduced signal. A first segment number generation circuit for obtaining, a second segment number generation circuit for obtaining the number of the second segment by inputting a reference phase signal inside the apparatus synchronized with the rotation phase reference signal of the rotary drum, and a first segment Number comparison circuit that compares the number with the second segment number, and the result of error correction using the C1 correction code At least a second error correction circuit having a function of outputting an error flag indicating that the first segment number and the second segment number do not match, and a first error correction circuit when indicating that the first segment number and the second segment number do not match. An error correction characterized by comprising an error flag conversion circuit for converting an error flag output from the circuit into a state indicating that it cannot be corrected, and a third error correction circuit capable of executing erasure correction by a C2 correction code. circuit. 3. A product code configuration obtained by adding an error correction code that is the first parity (hereinafter, C2 correction code) and then adding an error correction code that is the second parity (hereinafter, C1 correction code). And a second data block formed of a data frame formed by combining at least a synchronization signal and unique address data for each code word formed by adding the C1 correction code to the data block. N units (where n =
2, 3, 4 ..., N), and the data frame forming the segment is divided into one track on the magnetic tape by the rotary head or any one of the tracks in one track according to a predetermined order. An error correction circuit in a signal processing circuit on the reproducing side of a digital data recording / reproducing apparatus which allocates and records to a part, and which determines the first segment number to which the frame to which the address data is added belongs from the address data obtained from the reproduced signal. A first segment number generation circuit for obtaining, a second segment number generation circuit for obtaining the number of the second segment by inputting a reference phase signal inside the apparatus synchronized with the rotation phase reference signal of the rotary drum, and a first segment Number comparison circuit that compares the number with the second segment number, and the result of error correction using the C1 correction code A second error correction circuit having a function of outputting an error flag indicating at least an uncorrectable state; and a first buffer memory circuit for temporarily storing the data corrected by the second error correction circuit. A second buffer memory circuit for temporarily storing the error flag output from the second error correction circuit, and writing corrected data output from the second error correction circuit to the first buffer memory circuit. Write address generation circuit for generating an address for writing, and a second write address generation circuit for generating an address for writing the error flag output from the second error correction circuit to the second buffer memory circuit And using the output of the segment number comparison circuit as an input, the first segment number and the second segment number. An address conversion circuit for converting an address signal output from the third address generation circuit into an address number not used by the second buffer memory circuit when indicating that the numbers do not match, and the first buffer memory The circuit data and the error flag of the second buffer memory circuit are read, and C
A third error correction circuit capable of erasure correction using a 2-correction code, and after reading data and an error flag from the first buffer memory circuit and the second buffer memory circuit in accordance with a C2 correction code generation sequence. An error correction circuit comprising: a second buffer memory circuit; and a flag writing circuit that writes a logic level indicating an error on at least the address from which the error flag is read. 4. A product code configuration in which an error correction code that is the first parity (hereinafter, C2 correction code) is added, and then an error correction code that is the second parity (hereinafter, C1 correction code) is added. And a second data block formed of a data frame formed by combining at least a synchronization signal and unique address data for each code word formed by adding the C1 correction code to the data block. N units (where n =
2, 3, 4 ..., N), and the data frame forming the segment is divided into one track on the magnetic tape by the rotary head or any one of the tracks in one track according to a predetermined order. An error correction circuit in a signal processing circuit on the reproducing side of a digital data recording / reproducing apparatus which allocates and records to a part, and which determines the first segment number to which the frame to which the address data is added belongs from the address data obtained from the reproduced signal. A first segment number generation circuit for obtaining, a second segment number generation circuit for obtaining the number of the second segment by inputting a reference phase signal inside the apparatus synchronized with the rotation phase reference signal of the rotary drum, and a first segment Number comparison circuit that compares the number with the second segment number, and the result of error correction using the C1 correction code A second error correction circuit having a function of outputting an error flag indicating at least an uncorrectable state; and a first buffer memory circuit for temporarily storing the data corrected by the second error correction circuit. A second buffer memory circuit for temporarily storing an error flag output from the second error correction circuit, and corrected data output from the second error correction circuit to the first buffer memory circuit. And a second write address generating circuit for generating an address for writing an error flag output from the second error correction circuit to the second buffer memory circuit. An address generation circuit and an output of the segment number comparison circuit as inputs, and the first segment number and the first segment number. Output a write signal of the error flag output from the second error correction circuit to the second buffer memory when the segment numbers of the two match, and output a write signal of the error flag when indicating that they do not match. A buffer memory write control circuit having a function not to read, data of the first buffer memory circuit, and an error flag of the second buffer memory circuit, and C
A third error correction circuit capable of erasure correction using a 2-correction code, and after reading data and an error flag from the first buffer memory circuit and the second buffer memory circuit in accordance with a C2 correction code generation sequence. An error correction circuit comprising: a second buffer memory circuit; and a flag writing circuit that writes a logic level indicating an error on at least the address from which the error flag is read.