JPH05210573A - Address generating method - Google Patents

Abstract

(57) [Abstract] [Object] The present invention relates to an address generation method for continuously transferring data of a bit smaller than the bit width of a data bus, and improves bus transfer efficiency and address generation flexibility. To aim. [Structure] When the stride value is "1", it is determined whether or not the base address is the upper data address (steps 102 and 103), the output address is used as the base address (steps 104 and 113), and the stride value is set. A value obtained by multiplying the transfer data width is added to the base address (previous output address) to generate a new output address (steps 106 and 115). As a result, two pieces of 32-bit data are transferred by the 64-bit width data bus. When the stride value is "-1", substantially the same processing as above is executed (steps 116 to 125).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address generating method, and more particularly to an address generating method for continuously transferring data having a bit smaller than a bit width of a data bus.

For example, as shown in FIG. 7, a microprocessor 11 and a data bus 1 for the microprocessor 11 are provided.
2. External memory 1 connected via address bus 13
4 and the peripheral microprocessor 15 and the like, in the case where the data of the bit smaller than 1/2 times the bit width of the data bus 12 is continuously present,
Transferring those data at the same time improves the efficiency of the data bus 12 and contributes to improving the system performance. Therefore, there is a need for an address generation method capable of simultaneously transferring data of bits smaller than the bit width of the data bus 12.

[0003]

2. Description of the Related Art Conventionally, as a method of generating an address by a microprocessor 11, as shown schematically in FIG. 8A, a reference address (hereinafter referred to as "base address") As and one before Distance from the output address (This is an integer multiple of the number of data, and its unit is
Hereinafter, a method for generating an address by incrementing it by (stride) × (data unit) based on “(stride)” is known.

Therefore, according to this method, for example, when the data is 64 bits and the stride is "1", the address to be output is the value obtained by adding the address of 8 bytes to the address previously output.

[0005]

However, the data is shown in FIG.
As schematically shown in (B), in the case where the stride is "1" or "-1" and data is continuously present, the data length is 1/2 times that of the 64-bit data bus. In the case of 32 bits, when transferring data, it is better to transfer two data at the same time (that is, to make 64 bits), but the data bus transfer efficiency is better, but the previous one is output as in the conventional method. There is a problem that two addresses cannot be transferred simultaneously and the bus transfer efficiency cannot be improved if an address is created by simply adding (stride value) x (data address output one before) to the address. .. There is also a problem that the degree of freedom in address generation is low.

The present invention has been made in view of the above points,
An object of the present invention is to provide an address generation method capable of simultaneously transferring a plurality of data.

[0007]

According to the address generating method of the present invention, the number of bits is N / m (where m is an integer of 2 or more) in the data bus having the bit width N, and the stride value is 1 or-.
An address generation method for simultaneously transferring m consecutive 1's of data, determining whether the base address starts from a lower address or an upper address of m's of data and determining the stride value. Value is determined, and an output address for transferring m or m-1 data is first generated based on the determination result of the base address and the stride value, and thereafter the stride value and N are transferred according to the number of the previous transfer data. Alternatively, a value obtained by adding a value obtained by multiplying N / m to the previous output address is generated as a new output address.

[0008]

In the method of the present invention, the base address transfers m
An optimum address can be generated depending on whether the upper side address or the lower side address of each piece of data starts and the stride value. Moreover, the method of the present invention can generate an address not only when the stride value is "1" but also when the stride value is "-1".

[0009]

1 is a flow chart for explaining the operation of an embodiment of the method of the present invention. The present embodiment relates to a method of generating an address generated by the microprocessor 11 in the system shown in FIG. 7, and as shown in FIG. 2, a data bus having a bit width of 64 bits (12 in FIG. 7) has 64 bits. Is an address generation method for transferring one piece of data or two pieces of data having a bit number of 32 bits at the same time or one piece. In FIG. 1, first, the microprocessor determines whether or not 32-bit data is accessed (step 101), and when the 32-bit data is accessed, the stride value is determined (step 102). The stride value includes "1", "-1" and other values.

Therefore, first, an address generating method when the stride value is determined to be "1" in step 102 will be described with reference to FIGS. In this case, it is judged whether or not the base address starts from the upper side (step 103). When starting from the upper side,
64-bit data transfer using the first output address as the base address, as schematically shown by A _B1 in (A) (that is, simultaneous transfer of the first two 32-bit data indicated by square numbers 1 and 2). Is performed (step 104).

Then, the data number counter is decremented by "2" (step 105). The total number of data to be transferred is set in advance in the counter for the number of data, and since two data have been transferred in step 104, they are decremented by "2" in step 105.

Next, a value obtained by multiplying the stride value "1" by the transfer data width of 64 bits (data length x counter decrement value) is added to the above base address to generate an output address (step 106). .. Subsequently, it is determined whether or not the remaining transfer data number indicated by the data number counter is smaller than "2" (step 107). When it is "2" or more, 64 bits worth is obtained based on the address generated in step 106. After the data is transferred (step 108), the value of the data number counter is decremented by "2" and the base address is updated to the current output address (step 109).

Then, it is judged whether or not the value of the data number counter is "0" (step 110), and when it is not "0", the process returns to step 106 again, and the stride value "1" and 64 bits are set to the base address. A value multiplied by is added to generate an output address. Thereafter, in the same manner as above, in steps 106 to 110, a value obtained by adding 64 bits to the previous output address (here, the updated base address) is generated as a new output address.
In the order shown by circled numbers in (A), 32-bit data is 2
It is transferred one by one.

When the number of remaining data becomes one, the process proceeds from step 107 to step 111 and step 10
The 11th 32-bit data transfer is performed with the output address generated in 6. When it is determined in step 110 that the number of data is "0", or when 32-bit data is transferred in step 111, the address generation process ends (step 112).

Next, a method for generating an address when the stride value is "1" but it is determined in step 103 that the base address starts from the lower side will be described with reference to FIGS. 1 and 3B. In this case, as shown schematically in FIG. 3B, the first output address is used as the base address A _B2 , and the first 32-bit data transfer is performed (step 113).

Then, after decrementing the data number counter by "1" (step 114), a transfer data width of 32 bits and a stride value which are multiplication values of the data length (here 32 bits) and the decrement value "1". Multiply "1" and add 32 bits of the multiplication result to the base address A _B2 to generate a second output address (step 115).

After that, the above-mentioned steps 107 to 1 are carried out.
The processing of 11 and 106 is executed, and the remaining number of data is 2
When the number is 32 or more, two pieces of 32-bit data are transferred two by two, and the output address is generated by adding a value of 64 bits to the previous output address as a new output address. As a result, the data shown in FIG. 3B is transferred in the order shown by the circled numbers.

Next, at step 102, the stride value is "-
1 ", and the address generation method when it is determined in step 116 that the base address starts from the lower side will be described with reference to FIGS. 1 and 4A. In this case, the first output address Is not the base address but an address of A _{B3 in} FIG. 4 (A) indicating a higher-order address of 32 bits from the base address. Based on this address A _B3 , the first and second 32-bit data 2
Transfer is performed (step 117).

Subsequently, after decrementing the data number counter by "2" (step 118), the first output address A _B3 is updated as a base address (step 119), and the value of the data number counter is "2". It is determined whether or not it is less than (step 120). When the value of the data number counter is "2" or more, the product value of the stride value "-1" and the transfer data width (64 bits) is added to the updated base address to generate the output address (step 121).

That is, in step 121, a value obtained by subtracting 64 bits from the previous output address is generated as a new output address. Two pieces of 32-bit data are transferred based on this new output address, and the data number counter is decremented by "2" (step 1
22), it is determined whether or not the data number counter is "0" (step 123).

When there is still the remaining transfer data, the first byte address of the higher-order data is generated as the output address by the above steps 119 to 123 and 32
Bit data is transferred two by two. When the remaining transfer data is one, the process proceeds from step 120 to step 124, and the value obtained by multiplying the stride value "-1" by one data length 32 bits is added to the previous output address (base address). Generate a value as a new output address. Then, based on this output address, the seventh 32-bit lower data is transferred as shown in FIG. 4A (step 125). Step 1
After the processing of 23 or 125, the address generation processing ends (step 126).

Next, the address generation method in the case where the stride value is determined to be "-1" in step 102 and the base address is determined to start from the upper side in step 116 will be described with reference to FIGS. ) Together. In this case, the first output address is shown in FIG.
_Is generated as a base address schematically shown by A _B4 in
The first 32-bit data is transferred (step 127). Then, after decrementing the data number counter by "1" (step 128), step 119
The subsequent processing is performed.

Therefore, as described above, FIG.
As shown schematically, the leading byte address of the data on the upper side is generated as an output address, and two pieces of 32-bit data are transferred in the order shown by the circled numbers.

If it is determined in step 101 that the access is not a 32-bit access, or if it is determined in step 102 that the stride value is neither "1" nor "-1", the output address is the same as the conventional one. , (Stride value) × (transfer data width) at the previous output address
A value obtained by adding the multiplication value of is generated as the current output address (step 129).

Thus, according to this embodiment, 32
Since two bit data can be simultaneously transferred by the 64-bit width data bus, the bus transfer efficiency can be improved as compared with the conventional one, and the data transfer order is from the largest address to the smallest address. Therefore, it is possible to significantly increase the degree of freedom in using the memory and the like.

The 32-bit transfer process of steps 103 to 128 can be performed by the circuit shown in FIG. In the figure, the comparator 41 compares the stride value with "1" and outputs a signal of logic "1" only when the stride value is "1". The comparator 42 compares whether or not the stride value is "-1", and outputs a signal of logic "1" only when the stride value is "-1".
The OR circuit 43 determines that the data is continuous and outputs a logic "1" only when one of the comparators 41 and 42 outputs a signal of logic "1".

The comparator 44 compares whether the data length is 32 bits or not, and outputs a logic "1" only when the data length is 32 bits.
The AND circuit 45 is logical only when the outputs of the OR circuit 43 and the comparator 44 are both "1", that is, when the 32-bit data continuously exists with the stride value "1" or "-1". Decrement control circuit 46
Output to.

On the other hand, the comparator 47 compares whether or not the lower 3 bits of the base address are "000" and determines whether or not the base address is the address of the upper data by the decrement control circuit 46. Output to. Further, the adder circuit 48 adds the base address 49 and the address stride 50 controlled by the decrement control circuit 46 to generate an output address 51, which is updated as the base address 49.

Also, the decrement control circuit 46 compares the remaining number of data with the comparator 52 every time data is transferred.
And the data count is compared here. The comparator 52 outputs a predetermined logical value to the decrement control circuit 46 when the number of remaining data is "1". The decrement control circuit 46 sets the address stride 50 to 32 bits when the number of remaining data is "1".

The address generation in step 129 of FIG. 1 can also be realized by the circuit of FIG. In FIG. 6, the adder circuit 61 adds the multiplication result 63 of the stride value and the data length to the base address 62 and generates the addition result as the output address 64. The output address 64 is updated to the base address 62, and the same operation as described above is repeated thereafter. First output address 64
The base address 62 is used as the output address.

[0031]

As described above, according to the present invention, an optimum address can be generated according to the result of determination whether the base address is on the upper side and the stride value. Therefore, the bit width N of the data bus is 1 / m. It is possible to transfer continuous data of double the number of bits by m, thus improving bus transfer efficiency, and stride value of "-1".
In this case, the address can be generated, so that the degree of freedom in using the memory area can be greatly increased as compared with the conventional one.

[Brief description of drawings]

FIG. 1 is a time chart for explaining the operation of an embodiment of the present invention.

FIG. 2 is a diagram showing the data size and the number of transfer data in one embodiment of the method of the present invention.

FIG. 3 is an operation explanatory diagram of a main part of the embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of another main part of the embodiment of the present invention.

FIG. 5 is a circuit diagram that realizes a main part of one embodiment of the present invention.

FIG. 6 is a block diagram of an example of an address generation circuit with stride.

FIG. 7 is a configuration diagram of a system to which the present invention is applied.

FIG. 8 is an explanatory diagram of an example of a conventional method.

[Explanation of symbols]

11 Microprocessor 12 Data Bus 102 Stride Value Determination Step 103,116 Base Address Position Determination Step 106,115,121,124 Output Address Generation Step

Claims (5)

[Claims] 1. Continuous data having a bit number of N / m (where m is an integer of 2 or more) and a stride value of 1 or -1 are simultaneously transferred to the data bus (12) having a bit width N by m. An address generating method for determining whether the base address starts from a lower address or an upper address of m pieces of data, determines a value of the stride value, and determines the base address and the stride. An output address for transferring m or m-1 data is first generated based on the value determination result, and the value obtained by multiplying the stride value by N or N / m according to the number of the previous transfer data is the previous value. An address generation method characterized in that a value added to the output address of is generated as a new output address. 2. When the number of bits of the data is N / 2 and the stride value is 1, and when the base address starts from the upper address of the two data, the base is used as the first output address. 2. The address generating method according to claim 1, wherein the address is output and two pieces of data are transferred at the same time, and a value obtained by adding N bits to the previous output address is generated as a new output address. 3. The data has a bit number of N / 2 and a stride value of 1, and when the base address starts from a lower address of two data, the base is used as a first output address. The address is output to transfer one data, and then a value obtained by adding N / 2 bits to the first output address is generated as the second output address, and thereafter, N bits are added to the previous output address. 2. The address generation method according to claim 1, wherein a value obtained by adding is generated as a new output address. 4. When the number of bits of the data is N / 2 and the stride value is −1, and the base address starts from the upper address of the two data, it is regarded as the first output address. Output the base address and output 1
2. The address generation method according to claim 1, wherein the data is transferred, and thereafter, a value obtained by subtracting N bits from the previous output address is generated as a new output address. 5. When the number of bits of the data is N / 2 and the stride value is −1, and the base address starts from the lower address of the two data, it is regarded as the first output address. It is characterized in that a value obtained by subtracting N / 2 bits from the base address is generated to transfer two pieces of data, and thereafter, a value obtained by subtracting N bits from the previous output address is generated as a new output address. The address generation method according to claim 1.