JPH05210447A - Microcomputer - Google Patents

Abstract

PURPOSE:To surely execute key scan and to restart display without wasting time offer completing the key scan by controlling the. restart of display according to an instruction from a CPU while detecting the end of the key scan. CONSTITUTION:When the output end of a final digit in the designated number of digits is detected by a final digit output end detection circuit 129, an interruption signal 119 is generated, and a detection signal 137 is impressed to a reset terminal R of an FF 123. In response to this signal, a display start flag (f) is changed from '1' to '0'. An interruption signal control circuit 139 loads interruption to a CPU 103 while considering priority. Thereafter, a display device 115 stops display until the display start flag (f) is changed from '0' to '1' by the next software, and the key scan can be executed by an interruption processing. The end of the key scan is transmitted from a key 113 through an input/output circuit 107 and a data bus 105 to the CPU 103 and while receiving this key scan end, the next display start flag set is commanded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer having a display controller for displaying an external display device, stopping the display, and issuing an interrupt request for key scan processing.

[0002]

2. Description of the Related Art Conventionally, in a microcomputer system having an external display device and a keyboard composed of a plurality of key groups, the microcomputer outputs a digit signal which enables each digit of the external display device having a plurality of digits to be displayed. It has a digit signal generation circuit and a segment signal generation circuit that specifies a segment to be displayed among a plurality of segments forming each digit, for example, 8 segments for a number with a decimal point. , The segment signal is output and the display device is displayed while synchronizing with the digit signal. Further, in such a microcomputer, the scanning of the keyboard is also used as the segment signal, and when one of the keys is pressed and the scanning signal is applied to the input terminal of the microcomputer, the microcomputer outputs the timing when the scanning signal is output. And the key pressed from the input terminal to which the scanning signal is applied to the CPU
The input data was identified by the software inside.

However, in such a system, it is difficult to synchronize the output timing of the digit signal with the software.
Therefore, Japanese Patent Laid-Open No. 61-278920 attempts to accurately determine the end of the key scanning time by providing a flag that is set during the key scanning period. Further, in Japanese Patent Laid-Open No. 62-22390, additional cycle control means for generating an additional cycle for a key scanning period with a designated length is provided. As a result, even if an interrupt having a higher priority than the input data determination occurs before and after the start of scanning the key group, the key scanning period can be secured and the time required for the key scanning can be saved.

[0004]

However, even in the inventions described in the above-mentioned publications, when there are a plurality of interrupts having a higher priority than the key scanning, the interrupt having the longest processing time among them or their addition is performed. An additional cycle for the key scan period must be specified from the processing time given. Therefore, there is a problem that most of the additional cycles are wasted unless an interrupt having a higher priority than the input data determination occurs before and after the start of key scanning.

It is an object of the present invention to provide a microcomputer having a display controller which eliminates the wasteful time of such an additional cycle and can perform the key scanning process accurately and without waste.

[0006]

According to the present invention, a CPU
And a data bus connected to the CPU, the microcomputer being connected to the display device.
Is connected to the data bus, the signal from the CPU input to the first terminal sets the display start flag which is an output signal to the first level, and the signal from the second terminal sets the display start flag to the first level. A display start flag generation circuit for setting the level to 2, a counter for counting clock signals in response to the display start flag, and a digit signal output for inputting the output of this counter and outputting a display signal for each digit of the display device A microcomputer having a circuit and a circuit for outputting an interrupt request signal in response to the output of a counter and for giving a signal to the second terminal of a display start flag.

[0007]

1 is a circuit block diagram of an embodiment of the present invention. An embodiment of the present invention will be described below with reference to FIG.

The microcomputer 101 has a central processing unit (CPU) 103 and a data bus 105. Since the CPU 103 and the data bus 105 are publicly known, description of their functions will be omitted. Further, the microcomputer 101 has an input / output circuit 107 connected to the data bus 105, a digit signal output circuit 109 and a segment signal output circuit 111. The input / output circuit 107 receives a signal from the external key 113 and receives the signal from the CPU 101.
It functions as a relay point for sending to. The digit signal output circuit 109 outputs a digit signal 117 to the external display device 115 and an interrupt signal 119 to the CPU 103. The segment signal output circuit 111 outputs a segment signal 121 to the display device 115.

Here, the digit signal output circuit includes a flip-flop (FF) 123, a digit number counter 125, and a decoder 12.
7 and the final digit output detection circuit 129.
The operation of the digit signal output circuit 109 will be described with reference to the timing chart of FIG.

First, in FF123, by software,
That is, a signal is given from the CPU 103 via the data bus 105, and the display start flag (f) which is the output of the FF 123 is changed from "0" to "1" (timing A in FIG. 2). As a result, the display on the display device 115 starts.

Next, in response to the "1" level of the display start flag (f), the digit number counter 125 causes the oscillator (OSC) 1
The clock of 31 is divided by the frequency divider (DIV) 133 to count the number of digits, and the output is counted by the decoder 1
Give to 27. In the decoder 127, the digit number counter 125
Output is decoded and the digit signal 117 is synchronized with the segment signal (a) to sequentially output 0 digit (b), 1 digit (c), 2 digits (d) ... N digits (e). When the final digit output end detection circuit detects the output end of the N digit (e) which is the final digit of the designated digit number, the interrupt signal 119 is generated and the detection signal 137 is given to the reset terminal R of the FF123. In response to this detection signal, the display start flag (f) changes from "1" to "0" (timing B in FIG. 2). The interrupt signal 119 is input to the interrupt signal control circuit 139 together with other interrupt signals 137. The interrupt signal control circuit 139 determines the order in consideration of the priority of the interrupt signal and outputs the interrupt signal to the CPU 10
Give to 3.

Thereafter, the display device 11 is operated for a period (period D in FIG. 2) from when the display start flag (f) changes from "0" to "1" (timing C in FIG. 2) by the next software.
In No. 5, display is stopped, and key scanning can be performed by interrupt processing. Completion of the key scanning process is transmitted from the key 113 to the CPU 103 via the input / output circuit 107 and the data bus 105, and in response to the completion of the key scanning, the next display start flag set (timing C in FIG. 2) is commanded.

[0013]

As described above in detail, according to the present invention, the end of the key scanning can be detected and the restart of the display can be controlled by the instruction from the CPU, so that the key scanning can be surely performed. Further, after the key scanning is completed, the display can be restarted without wasting time.

FIG. 3 is a diagram showing the key scanning processing time and waiting time according to the present invention and the related art. Hereinafter, the effect of the present invention will be described in comparison with the related art with reference to this drawing.

The key scanning process is performed as one of interrupt processes after the display stop 301. When only the key scanning process is performed while the display is stopped, in the present invention, (a)
As indicated by, the display is restarted 305 (indicated by a black circle) immediately after the key scanning process 303 (indicated by a thick solid line).
However, conventionally, as shown in FIG.
Unnecessary waiting time 307 after 3 is finished (thin solid line)
Will occur. This is because conventionally, the period from the display stop 301 to the display restart 305 is determined in a certain period.

If there is an interrupt process 309 (shown by a dotted line) having a higher priority than the key scanning process 303 after the stop 301 of display, that interrupt process is given priority. Therefore, in the case of the present invention, as shown in (b) and (e), the key scanning process 303 is performed after the process 309 is completed, and the display restart is immediately performed 3
05 is performed. However, conventionally, as shown in (e), if the other processing 309 is short, the waiting time 307 also occurs after the end of the key scanning 303. As shown in (f), the same result is obtained as in the related art and the present invention only when the other processing 309 and the key scanning processing 303 coincide with a predetermined period.

[Brief description of drawings]

FIG. 1 is a block diagram of the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a diagram showing a key scanning processing time according to the present invention and the related art.

[Explanation of symbols]

 103 CPU 105 Data Bus 107 Input / Output Circuit 109 Digit Signal Output Circuit 111 Segment Signal Output Circuit 123 Flip-Flop 125 Digit Number Counter 127 Decoder 129 Final Digit Output End Detection Circuit 119 Interrupt Signal 137 Detection Signal

Claims (1)

[Claims] 1. A microcomputer having a CPU and a data bus connected to the CPU, the first terminal being connected to the data bus and being input to the first terminal in a microcomputer connected to a display device. The display start flag, which is an output signal, is set to the first level by the signal from the CPU, and the second
A display start flag generating circuit for setting the display start flag to a second level by a signal given to the terminal of the counter, a counter for counting a clock signal in response to the display start flag, and an output of the counter, A digit signal output circuit that outputs a display signal of each digit of the display device, and a circuit that outputs an interrupt request signal in response to the output of the counter and that applies a signal to the second terminal of the display start flag. Microcomputer having.