JPH0520875A - Memory circuit - Google Patents

Abstract

PURPOSE:To obtain a memory circuit having small chip size and short access time. CONSTITUTION:A data D is transmitted on a single data line 4b to the gate of an NMOS transistor 12. When the data D has a potential higher than a reference voltage Vref((l/2)Vcc), a PMOS transistor 11 is turned ON whereas an NMOS transistor 13 is turned OFF and an 'H' level is outputted to a pad 7. When the data D has a potential lower than the reference voltage Vref, the PMOS transistor 11 is turned OFF whereas the NMOS transistor 13 is turned ON and an 'L' level is outputted to the pad 7. Consequently, only one data transmission line 4b is required and the output is inverted before the potential of the data D goes 'H' or 'L' level. According to the invention, space factor of data transmission line is reduced and access time is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission method for a memory circuit.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing the structure of a conventional memory IC, showing a memory IC having a word structure of x4. In the figure, 1 is a memory array, 2 is an I / O line pair for inputting / outputting data from the memory array 1, 3 is a preamplifier for amplifying a differential voltage between the I / O line pair 2, and 4a is an output of the preamplifier 3. Is a data transmission line pair 5 for transmitting data.
A main amplifier for converting the differential voltage from the output to "H" level or "L" level for output, 6 is an output line for transmitting the output of the main amplifier 5, and 7 is a pad for connecting the output line 6 and an external pin. ..

There are two pairs of data transmission lines 4a for transmitting the output of the preamplifier 3, and since the word structure is × 4, it is 2
× 4 = 8 data transmission lines are required. Recently, while the integration of memory has become more intense, × 8 products, × 16 products,
The word composition tends to increase with x32 items. If the word structure increases to x32, the data transmission line pair 4a has 32
It becomes a pair, and 2 × 32 = 64 data transmission lines are required, and the area occupied by the data transmission lines increases, which conflicts with the integration of the memory.

On the other hand, the data transmission line pair 4a is not a pair but 1
In the case of a book, a method of transmitting and outputting data by an inverter output has been conventionally used. Preamplifier 3 at this time
The differential voltage between the I / O line pair 2 is converted into a logical value of "H" level or "L" level. At this time, if the data transmission line from end to end of the chip becomes long, the load capacitance, wiring resistance, etc. of the data transmission line increase, and it takes time to charge and discharge the data transmission line for inverting the output of the inverter. However, this hinders faster access time.

[0005]

Since the conventional memory IC is configured as described above, there is a problem that the number of data transmission line pairs 4a increases and the chip size increases as the word configuration increases. It was On the other hand, if the number of data transmission lines is reduced and the logic signal is transmitted by the output of the inverter, the access time will be delayed.

The present invention has been made to solve the above problems, and an object thereof is to obtain a memory circuit having a small chip size and a fast access time.

[0007]

In a memory circuit according to the present invention, a line pair for outputting data from a memory cell array is connected, and the difference voltage is higher than a reference voltage in accordance with the difference voltage between the line pair. Alternatively, conversion means for converting to data having a small potential, one data transmission line for transmitting the data from the conversion means, and data from the data transmission line are received, and the potential of the data is set to the reference voltage. The output means is provided for comparing and outputting "H" level or "L" level according to the comparison result.

[0008]

According to the present invention, one data transmission line for transmitting data from the converting means and data from the data transmission line are received, the potential of the data is compared with the potential of the reference voltage, and the result of the comparison is determined. Since the output means for outputting the logic "H" level or the logic "L" level is provided, the area occupied by the data transmission line is reduced and the potential of the reference voltage is changed to the logic "H" level and the logic "L". When the potential of the data transmission line is set to an intermediate potential, the potential of the data transmission line becomes before the logical "H" level or the logical "L" level, that is, when the potential of the data transmission line becomes higher than or lower than the reference voltage. At that time, the output from the output means is inverted.

[0009]

1 is a block diagram showing the structure of a memory circuit according to the present invention. 1 is different from the conventional IC shown in FIG. 3 in that the data transmission line pair 4a is changed to one data transmission line 4b, and the potential of the data transmission line 4b is set to the logic "H" level or the logic "L" level. That is, the output of the main amplifier 5 is inverted before it becomes.

FIG. 2 is a circuit diagram showing an example of the configuration of the preamplifier 3. P-channel MOS transistor (hereinafter PM
The source of an OS transistor 30 is a power source 20.
And the gates are each connected to its own drain. P
The MOS transistor 31 has a source connected to the power supply 20 and a gate connected to the gate of the PMOS transistor 30. N-channel MOS transistor (hereinafter NMOS
The drain of the transistor 32) is connected to the drain of the PMOS transistor 30. The drain of the NMOS transistor 33 is the PMOS transistor 3
The drain and the source of 1 are connected to the source of the NMOS transistor 32, respectively. NMOS transistor 3
The gates of 2, 33 are connected to the I / O line pair 2. P
A common drain connection point between the MOS transistor 31 and the NMOS transistor 33 is connected to the data transmission line 4b. The NMOS transistor 34 has a gate to which an enable signal ES is applied, a drain connected to a common source connection point of the NMOS transistors 32 and 33, and a source connected to GND. The preamplifier 3 shown above has the same configuration as the preamplifier used in the case where the data transmission line shown in the prior art is integrated.

FIG. 3 is a circuit diagram showing an example of the configuration of the main amplifier 5. The main amplifier 5 is composed of PMOS transistors 10 and 11 and NMOS transistors 12, 13 and 14. The PMOS transistor 10 and the PMOS transistor 11 are current-mirror connected. The PMOS transistor 10 has a source connected to the power supply 20 and a gate connected to its own drain. The PMOS transistor 11 has a source connected to the power supply 20 and a gate connected to the gate of the PMOS transistor 10.

The NMOS transistor 12 has a gate for the data transmission line 4b and a drain for the PMOS transistor 1
2 drains, respectively. The gate of the NMOS transistor 13 has a reference voltage (the voltage value is (1/2) V).
_cc (V _cc is the voltage of the power supply 20)) V _ref , drain is P
The source is NMO at the drain of the MOS transistor 11.
Each is connected to the source of the S transistor 12. N
The MOS transistor 14 has an enable signal E at its gate.
S is given and the drain is the NMOS transistor 12,
Sources are respectively connected to GND at 13 common source connection points. The drain connection points of the PMOS transistor 11 and the NMOS transistor 13 are connected to the pad 7. Other configurations are similar to those of the conventional IC shown in FIG.

Next, the operation will be described. When the enable signal ES becomes "H", the preamplifier 3 is activated and the differential voltage from the memory array 1 is given to the preamplifier 3 via the I / O line pair 2. Referring to FIG. 2, NMOS transistors 32 and 33 are selectively turned on / off in accordance with a difference voltage between I / O line pair 2, and data transmission line 4b outputs "H" level or "L" level. Data D is output.

The data D output from the preamplifier 3 is 1
It is input to the gate of the PMOS transistor 12 of FIG. 3 via the book data transmission line 4b. Then, when the enable signal ES becomes "H" level, the main amplifier 5 is activated, and the potential of the data D and the potential of the reference voltage V _ref ((1 /
2) _Vcc ) is compared and the potential of data D is (1/2) V
If it is larger than _cc , the NMOS transistor 12 is turned on,
The NMOS transistor 13 turns off. Since the NMOS transistor 12 is turned on and the NMOS transistor 13 is turned off, the PMOS transistor 11 is turned on and the power source 20
Current is supplied from the pad 7 to the pad 7. Therefore, pad 7
"H" level is output to.

On the contrary, when the potential of the data D is smaller than (1/2) _Vcc , the NMOS transistor 12 is turned off and NMO is turned on.
The S transistor 13 is turned on. Since the NMOS transistor 12 is off and the NMOS transistor 13 is on, the PMOS transistor 11 is off. Since the NMOS transistor 13 is turned on, the NMOS is supplied from the pad 7.
Current is drawn through the transistor 13 and the pad 7
Becomes "L" level.

In this way, the "H" level or "L" level is output depending on whether the potential of the data D from the data transmission line 4b is larger than the potential ((1/2) _Vcc ) of the reference voltage _Vref. I am trying. Therefore, even if the data transmission line 4b becomes long and the wiring capacitance, the wiring resistance, etc. increase, the output of the main amplifier 5 is inverted before the potential of the data transmission line 4b becomes the logic "H" level or the logic "L" level. Therefore, the access time is not delayed unlike the transmission of the logic signal by the output of the inverter.

In the above embodiment, as described above, the preamplifier 3 has the same structure as the conventional one, and the difference voltage between the I / O line pair 2 is converted to the logic "H" level or the logic "L" level. As described above, the preamplifier 3 does not necessarily have to output the logic “H” level or the logic “L” level, and the difference voltage between the I / O line pair 2 is used as the reference voltage V
_Any configuration may be used as long as it is converted to a potential larger or smaller than _ref . At this time, the configuration of the preamplifier 3 is
If the differential voltage between the I / O line pair 2 to the configuration outputs a slightly larger potential or slightly smaller potential than the reference voltage V _ref, the slightly larger potential or slightly smaller potential than the reference voltage V _ref of the data transmission line 4b The amount of change can be small from (1/2) _Vcc . Therefore, when the output of the preamplifier 3 is inverted, the charging / discharging of the data transmission line 4b becomes faster, the output is inverted faster than in the above embodiment, and the access time becomes faster.

Further, since the number of data transmission lines 4b is one, the area occupied by the data transmission lines is smaller than that in the case of two lines, and the chip size is reduced.

In the above embodiment, the case where the output of the preamplifier 3 is transmitted by the data transmission line 4b has been described, but the output data of the sense amplifier may be transmitted by the data transmission line 4b.

[0020]

As described above, according to the present invention, one data transmission line for transmitting the data from the conversion means and the data from the data transmission line are received, and the potential of the data is set to the potential of the reference voltage. By comparison, since the output means for outputting the “H” level or the “L” level is provided, the area occupied by the data transmission line is reduced and the potential of the reference voltage is set to the logic “H” level and the logic “L”. When the potential of the data transmission line is set to an intermediate potential, the potential of the data transmission line becomes before the logical "H" level or the logical "L" level, that is, when the potential of the data transmission line becomes higher or lower than the reference voltage. The output from the output means is inverted by. As a result, the chip size is reduced and the access time is shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a memory circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a preamplifier.

FIG. 3 is a circuit diagram showing a configuration example of a main amplifier.

FIG. 4 is a diagram showing a configuration of a conventional memory IC.

[Explanation of symbols]

2 I / O line pair 3 Preamplifier 4b Data transmission line 5 Main amplifier V _ref Reference voltage

Claims (1)

Claim: What is claimed is: 1. A pair of lines for outputting data from a memory cell array are connected, and data having a potential larger or smaller than the reference voltage is applied to the difference voltage according to the difference voltage between the pair of lines. A conversion means for converting the data into one, a data transmission line for transmitting the data from the conversion means, data received from the data transmission line, a potential of the data is compared with the reference voltage, and a comparison result is obtained. A memory circuit having output means for outputting "H" level or "L" level in response.