JPH05207293A - Variable length coding decoding circuit - Google Patents

Abstract

PURPOSE:To reduce the capacity of a decoding table ROM in the variable length decoding circuit in which a luminance signal and a chrominance signal are separated, DCT and quantization are applied to them, the luminance signal and the chrominance signal of an AC component of a DCT coefficient already quantized for a compressed picture element applying variable length coding to the quantized DCT coefficient converted into the same Huffman code are received as input data and the data are decoded into the quantized DCT coefficient of a fixed length. CONSTITUTION:The circuit is provided with a decoding table ROM 1 outputting an additional bit length decoding a Huffman code included in input data and a succeeding address fed back to an address input terminal and a quantization coefficient decoding section 3 decoding a fixed length quantized DCT coefficient from the additional bit and an additional bit length outputted from the decoding table ROM 1, and the decoding table ROM 1 is provided with plural common areas for the AC component of the luminance signal and the chrominance signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable length code decoding circuit installed in a reproducing apparatus for multimedia information.

[0002]

2. Description of the Related Art Presently, a recording medium such as a CD-ROM as multimedia information is a combination of entertainment and educational software, which has been encoded by compressing materials such as video data, audio data and program data for compression. A multimedia information recording / reproducing system is being developed, which is recorded by a user and obtained and reproduced and output by using a reproducing device. The video data as a material includes a television screen signal, a computer screen signal created by a personal computer or the like, and a material obtained by combining these screen signals may be used as the material.

As a typical coding method for data compression, hybrid coding is known in which discrete cosine transform (DCT), quantization and variable length coding are sequentially combined. The coded data created by such hybrid coding is configured in units of coded data for one screen (frame) as shown in FIG. 4, and one screen is spatially divided into a plurality of blocks. Coded data obtained by equally dividing, discrete cosine transforming, quantizing, and variable-length coding each of the luminance signal and the chrominance signal in each block is block data (Y / C) in the order of arrangement of the blocks on the display screen. Are arranged after the frame header as. The encoded data group in each block is obtained by quantizing the coefficients of the discrete cosine transform and performing variable length encoding,
In each piece of data, first, a direct current (DC) component and then an alternating current (AC) component are arranged in ascending order of spatial harmonics. A dummy bit is inserted at the end of the block data in order to keep the data amount of the frame constant even if the data amount of the variable length code changes.

Each piece of coded data in units of discrete cosine transform coefficient is an additional bit which is a lower part (effective bit) of the quantized coefficient excluding the upper part of all "0" or all "1", and this addition. It is composed of a part obtained by converting an additional bit length indicating how many bits are formed into a Huffman code. The additional bits are obtained by cutting out from the lowest to the highest "1" for the positive quantized coefficient, and for the negative quantized coefficient, 1 is subtracted from the quantized coefficient and the lowest to the highest. It is a cutout up to "0". For example, when the quantization coefficient is “20” (decimal number), the additional bit is [10100] _B (binary number), and the additional bit length is “5”. When this is decoded into 11-bit fixed data, [00000010100] _B is obtained. When the quantization coefficient is “−20”, the additional bit is [01011] _B and the additional bit length is “5”. When this is decoded into 11-bit fixed data, “11111” is obtained.
101011] _B is obtained.

Therefore, in the decoding of the variable length code, first, the preceding Huffman code is decoded to recognize the additional bit length, and then the subsequent additional bit is cut out to the upper bit side (1
1-additional bit length) All "0" or all "1" of width
Is added to restore 11-bit fixed-length data. The additional bit length has a minimum of 0 bits to a maximum of 11 bits, and this is represented by a Huffman code having a minimum code length of 2 bits to a maximum of 9 bits. The shortest 2-bit Huffman code to indicate the additional bit length "3" with the highest appearance frequency

[00] _B is assigned.

Decoding of the Huffman code is important in decoding the variable length code, but the decoding of the Huffman code is mainly performed by the decoding table ROM from the viewpoint of improving the processing speed. As shown in FIG. 5, the decoding circuit having the decoding table ROM as a main component, as shown in FIG.
The ROM address generation unit 2, the quantized coefficient decoding unit 3, the quantized coefficient address decoding unit 4, the counting / control unit 5, the decoding sequencer 6, and the handshake control unit 7 are included.

As shown in FIG. 6, the ROM address generation unit 2 is composed of a parallel / serial conversion circuit 21, a selector 22, an address synthesis circuit 23, a selector 24 and an all-zero register 25. The 8-bit wide input data (variable length code) supplied to the input terminal is converted into 1-bit serial data by the parallel / serial conversion circuit 21 and supplied to one input terminal of the address synthesis unit 23. The other input terminal of the address synthesis unit 23 is supplied with the next address or the Y / C start address of 8-bit width selected by the selector 22 according to the Y / C discrimination signal. The 9-bit width composite address output from the address composition circuit 23 is selectively supplied to the decoding table ROM 1 in the selector 24 according to the input data discrimination signal.

As shown in FIG. 7, the decoding table ROM1 which is accessed by the address signal of 9-bit width supplied from the ROM address generating section 2 has a luminance signal (Y) and a chrominance signal (C). It is divided into address areas for decoding the Huffman code of the DC component and the Huffman code of the AC component of the spatial harmonics, and each address area stores the decoded data of 22-bit width having the structure shown in FIG. There is. The 0th bit to the 7th bit of this decoded data are the next address of 8-bit width which is fed back to the ROM address generation unit 1 in the previous stage, and the 8th bit to the 13th bit are supplied to the decoding sequencer 6. 6
This is a bit width control signal. In addition, the 14th
Bits to the 17th bit are an additional bit length of 4 bits supplied to the quantization coefficient decoding unit 3, which is called code 1. Further, the quantized coefficient address decoding unit 4 is used for the 18th to 21st bits of the decoded data.
Is a 4-bit wide run length, referred to as code 2.

The 6-bit width control signal included in the decoded data is constructed as shown in the lower part of FIG. The 8th bit of this control signal is a bit indicating the end or the continuation of the decoding of the variable length code, the 9th bit is a bit indicating that an error has occurred in the decoding of the variable length code, and the 10th bit is the decoding. It is a bit indicating whether the data inside is a DC component or an AC component. The 11th bit is an escape (ES) inserted when zero runs continue for a predetermined value or more.
C) A bit indicating the appearance of the code, and the 12th bit is 1
It is (EBO) indicating the end of data for a block, and the 13th bit is a code designating bit indicating whether the data is positive or negative.

Corresponding to the address map of the decoding table ROM1 shown in FIG. 7, the decoding table ROM1 is accessed based on the state transition shown in FIG. That is, from the initial state, the Huffman code of the DC component of the luminance signal is first decoded, and the bit length of the additional bit of the decoding result is supplied to the quantization coefficient decoding unit 3 in the subsequent stage. The quantization coefficient decoding unit 3 cuts out variable-length additional bits directly supplied from the ROM address generation unit 2 in the form of serial data based on the above-mentioned additional bit length, and restores the fixed-value quantization coefficient. Subsequently, the additional bit length is decoded for each of the AC components of the luminance signal, and the quantization coefficient is restored based on the additional bit length and the additional bit of the decoding result. Similarly, for the chrominance signal (C), fixed length data is first restored in the order of the DC component and then the AC component, and when the decoding of the luminance signal and the chrominance signal for one frame is completed, the initial state is restored. Will be restored.

A quantized coefficient decoding unit 3 for decoding fixed-length data from the decoded additional bit length and additional bit.
Are configured as shown in FIG. Decoder 31
Generates an all zero of a predetermined width based on the additional bit length supplied from the decoding table ROM1 at the previous stage, and synthesizes the circuit 33.
Is supplied to the first input terminal of. The second of this synthesis circuit 33
The additional bit converted into parallel data by the serial / parallel conversion circuit 32 is supplied to the input terminal of. Synthesis circuit 33
Reconstructs 11-bit width fixed length data by synthesizing all zeros supplied to the first input terminal as an upper bit group and additional bits supplied to the second input terminal as a lower bit group. This restored 11-bit wide fixed length data is output to the subsequent stage through switches 38 and 39 which are switched according to the polarity (positive / negative) of the data being restored, and whether the data being restored is an AC component or D
The quantized coefficient for which decoding has been completed is output through the switch 41 that is switched according to whether it is the C component.

The comparison circuit 36 of FIG. 10 is a counter for counting the additional bit length held in the flip-flop 34 in synchronization with the signal indicating the end of the data and the additional bit enable signal output in synchronization with the additional bit. The count value of 35 is compared, and if they are equal, the flip-flop 37
Is supplied with a latch signal to hold the synthesized fixed value data. Further, the switches 38 and 39 and the adder circuit 40 selectively add 1 to the negative data. Further, the switch 41, the adder circuit 43, and the previous block data holding circuit 42 restore the DC component represented by the difference value from the previous block.

[0013]

In the conventional variable length decoding / decoding circuit described above, regarding the AC component, the luminance signal (Y) and the chrominance signal (C) are subjected to variable length coding by the same Huffman code. Nevertheless, the area of the decoding ROM table is reserved for each. Therefore ROM
There is a problem that the capacity increases and the cost of the entire circuit increases.

Further, in the above-mentioned conventional variable length decoding circuit, the quantization coefficient decoding unit shown in FIG. 10 is provided with the counter and the comparison circuit for detecting the end of the additional bit, so that the quantization coefficient decoding is performed. The amount of hardware in the department increases,
There is also a problem that the cost of the entire decoding circuit becomes high.

[0015]

The variable length decoding circuit of the present invention for solving the above-mentioned conventional problems provides an additional bit length obtained by decoding a Huffman code included in input data and a next address fed back to an address input terminal. Quantization coefficient decoding for outputting a decoding ROM table and an additional bit following the Huffman code, and for decoding the additional bit and the additional bit length output from the decoding ROM table into a fixed length quantized DCT transform coefficient And a decryption R
The OM table has a common decoding area for the AC components of the luminance signal and the chrominance signal. The operation of the present invention will be described in detail with the following examples.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The schematic structure of a variable length code decoding circuit according to an embodiment of the present invention is basically the same as that of the conventional one shown in FIG. However, the storage area of the decoding ROM table 1 is, as shown in FIG. 1, an area for converting the additional bit length of the DC component of the Huffman-coded luminance (Y) signal into a 4-bit fixed-length code, Area for converting the additional bit length of the DC component of the Huffman-encoded color (C) signal into a 4-bit fixed-length code, and additional bits of the DC component of both the Huffman-encoded luminance signal and chrominance signal A luminance / color common area for converting the length to a 4-bit fixed length code, and an additional bit counter area that outputs only the next address as valid data while an additional bit following the Huffman code of the additional bit length appears. In that it is separated into
This is different from the address map of the conventional circuit shown in FIG.

Corresponding to the structure of the address map of the code table ROM1, the decoding table ROM1 is accessed under the state transition as shown in FIG. That is, from the initial state, the Huffman code of the DC component of the luminance signal is first decoded, and the bit length of the additional bit of the decoding result is supplied to the quantization coefficient decoding unit 3 in the subsequent stage. The quantization coefficient decoding unit 3 cuts out variable-length additional bits directly supplied from the ROM address generation unit 2 in the form of serial data based on the above-mentioned additional bit length, and restores the fixed-value quantization coefficient. Subsequently, the additional bit length is decoded for each of the AC components of the luminance signal, and the quantization coefficient is restored based on the additional bit length and the additional bit of the decoding result. Similarly, for the chrominance signal (C), fixed length data is first restored in the order of the DC component and then the AC component, and when the decoding of the luminance signal and the chrominance signal for one frame is completed, the initial state is restored. Will be restored.

As described above, as for the AC component, the code table ROM 1 includes a common area for the luminance signal and the chrominance signal, so that the ROM memory is stored as compared with the conventional variable length code decoding circuit shown in FIG. The capacity is greatly reduced, and the manufacturing cost is reduced.

When the additional bit length is determined after the decoding of the Huffman code is completed, the ROM address branches to an address smaller by the additional bit length than the address of the branch point to the decoding start address of the next Huffman code. After this, each time an additional bit appears, this 1
The address obtained by synthesizing the bit and the next address is incremented by one, and when the last bit of the additional bits appears, R
The OM address reaches the address of the branch point to the decoding start address of the next Huffman code. As a result, the additional bit counter area in the decoding table ROM1 has a function of counting the additional bits.

As described above, by newly adding the additional bit counter section in the code table ROM 1, the quantized coefficient decoding section 3 has a structure as shown in FIG. The structure of the quantized coefficient decoding unit 3 becomes simpler because the flip-flop 34, the counter 35, and the comparison circuit 36 of the conventional circuit are not necessary, as is apparent from comparison with the conventional configuration shown in FIG. Therefore, the manufacturing cost can be reduced.

Although not directly related to the gist of the present invention, the operation of the peripheral portions of FIGS. 5 and 6 will be described as follows.

In the ROM address generation unit 2 of FIG. 6, when the input data is a frame header or when the buffer memory control (BMC) unit of the previous stage is BUSY, all-zero
The 9-bit all-zeros held in the register 25 are output from the selector 24 under the control of the input signal discrimination signal. The handshake control unit 7 of FIG. 5 performs control for continuously reading data from the buffer memory control unit in the previous stage, and activates the data request (request) signal to cause the buffer memory control unit to operate. Data transfer is requested, and 136 bytes are transferred in synchronization with the strobe signal.

The counting / control unit 5 decodes the frame header, counts the number of input data, sends a continuous read end signal to the buffer memory control unit, and outputs a valid signal for each data. In addition, the counting / control unit 5 holds the screen sizes DX and DY included in the frame header, and discriminates signals of Y / C, EOC (End Of Component), and EOB (ENDOf B).
lock), various end signals such as EOF (End Of Frame) are output.

The decoding sequencer 6 creates various sequence control signals based on the control signals output from the counting / control unit 5 and the decoding ROM table 1, and the quantized coefficient decoding unit 3
And the quantization coefficient address decoding unit 4 and the like.

The quantized coefficient address decoding unit 4 decodes the decoded RO.
The 4-bit run length (code 2 in FIG. 8) output from the M table 1 is received, and the address of the quantized coefficient, that is, the arrangement in the block zigzag-scanned at the time of encoding is decoded. It should be noted that two-dimensional Huffman coding is adopted by combining a number of consecutive zero quantized coefficients and a non-zero effective quantized coefficient that appears immediately after this zero consecutive. If the zero run exceeds 15, ESC (Esca
pe) code has been replaced.

[0026]

As described above in detail, according to the variable length code decoding circuit of the present invention, since the decoding ROM table has a common decoding area for the AC components of the luminance signal and the chrominance signal, these are R compared to the conventional circuit provided separately
The OM capacity is greatly reduced, and the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a conceptual diagram for explaining an address map in a decoding table ROM which constitutes a variable length code decoding circuit according to an embodiment of the present invention.

FIG. 2 is a decoding table R having the address map of FIG.
It is a state transition diagram of the decoding process performed using OM.

FIG. 3 is a block diagram illustrating the configuration of a quantized coefficient decoding unit included in the variable length code decoding circuit according to the above embodiment.

FIG. 4 is a data format diagram for explaining a configuration of variable-length encoded data to be decoded.

FIG. 5 is a block diagram showing a schematic configuration of a variable length code decoding circuit according to the above-described embodiment and a conventional example.

6 is a block diagram showing an example of a configuration of a ROM address generation unit 2 in FIG.

FIG. 7 is a conceptual diagram for explaining an address map in a conventional decoding table ROM.

8 is a data format diagram for explaining a configuration of data output from the decoding table ROM1 of FIG.

9 is a decoding table R having the address map of FIG.
It is a state transition diagram of the conventional decoding process performed using OM.

FIG. 10 is a block diagram showing a configuration of a conventional quantized coefficient decoding unit.

[Explanation of symbols]

 1 Decoding table ROM 2 ROM address generation unit 3 Quantization coefficient decoding unit

Claims (2)

[Claims] 1. A luminance signal and a chrominance signal are separated, DCT (discrete cosine transform) is performed on each of them, quantization is performed, and the upper part of all "0" or all "1" is removed from the quantized DCT coefficient. It is a compressed image signal which is variable length coded by arranging a lower part (additional bit) behind and arranging a part obtained by converting the additional bit length indicating the width of this additional bit into a Huffman code forward In the variable-length code decoding circuit that receives as input data the converted Huffman code for both the luminance signal and the chrominance signal for the AC component of the completed DCT coefficient, and decodes this as fixed-length quantized DCT coefficient, A decoding table ROM for outputting the additional bit length obtained by decoding the Huffman code included in the data and the next address fed back to the address input terminal; A quantized coefficient decoding unit that receives an additional bit following the Huffman code and decodes the additional bit and the additional bit length output from the decoding table ROM into a quantized DCT coefficient of a fixed length. The table ROM stores A of the luminance signal and the color signal.
A variable-length code decoding circuit having a common decoding area for the C component. 2. The variable length code decoding circuit according to claim 1, wherein the decoding table ROM includes an additional bit counter area that outputs only the next address as valid data while the additional bits are being input.