JPH05206475A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To enhance the speed of a non-volatile semiconductor memory device, such as EPROM having a floating gate and a control gate. CONSTITUTION:An erasable programmable ROM (EPROM) is a memory device which has a P<+> silicon substrate 1, an SiO2-made first gate insulation film 3, an n<+> polysilicon-made floating gate insulation film 7 and a P<+> polysilicon-made floating gate 11. The floating gate 5 and the control gate 11 are opposite to each other about their conductivity where there exists a differential work function. As a result, the field intensity applied to the floating gate 5 is small, which prevents a drop in the memory holding characteristic attributable to electron leakage from the floating gate 5 to the control gate 11. It is, therefore, possible to reduce the film thickness of the second gate insulation film 7 and enhance the operating speed of the EPROM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device such as an EPROM, and more particularly to a non-volatile semiconductor memory device which is advanced without deteriorating its memory retention capacity.

[0002]

2. Description of the Related Art As an example of a non-volatile semiconductor memory device, an EPROM is exemplified. As shown in the cross section of FIG. 4, a silicon substrate 1, a first gate insulating film 3, a floating gate 5, a second gate insulating film 7 are shown. , A control gate 9, a source formation region 15 and a drain formation region 17 as diffusion layers, and a side wall 19 of SiO ₂ . The silicon substrate 1 is formed of p ^{+ type} , the floating gate 5 is formed of n ^{+ type} polysilicon to facilitate writing, and the control gate 9 is also formed of the same n ^{+ type} polysilicon as the floating gate 5.
The first gate insulating film 3 and the second gate insulating film 7 are each formed of silicon dioxide (SiO ₂ ). That is, the silicon substrate 1 and the floating gate 5 have opposite conductivity, and the floating gate 5 and the control gate 9 are formed to have the same conductivity.

As shown in the operating characteristic diagram of FIG. 2, the EPROM has a threshold voltage ΔV as seen from the control gate 9 depending on the presence or absence of electrons injected into the floating gate 5.
_{The th} is changed to correspond to the stored value "0" or "1". In FIG. 2, the horizontal axis represents the control gate voltage V _CG and the vertical axis represents the drain current _ID .

[0004]

Problem to be Solved by the Invention EPRO shown in FIG.
The energy band (energy level (level)) of M is shown in FIG.
Shown in. The symbol E _C shown by the solid line is the conduction (Cond
uction) energy level, the symbol E _V shown by the solid line shows the valence energy level _, and the symbol E _F shown by _the broken line shows the Fermi energy level. From the left side, the energy level of the silicon substrate 1, the energy level of the first gate insulating film 3 having the thickness d1, the energy level of the floating gate 5, the energy level of the thickness d2, and the control gate 9
Indicates the energy level of. FIG. 6B shows the energy band in the initial state before electron injection, and FIG. 6C shows the holding state after electron injection. In FIG. 6B, since the floating gate 5 and the control gate 9 are formed of the same n ^{+ type +} polysilicon, the energy levels before electron injection are the same. In FIG. 6C, the energy level of the floating gate 5 rises with respect to the potential of the control gate 9 by the potential ΔV1 at which the electrons e are injected, and the first gate insulating film 3 and the second gate insulating film 7 have the same energy level. , A large gradient occurs in the energy level.

In recent years, as the operating speed of EPROM has been improved, the film thickness (thickness d2) of the second gate insulating film 7 is 100Å.
It is getting thinner. When the thickness of the second gate insulating film 7 is reduced in order to increase the operation speed, electrons leak from the floating gate 5 to the control gate 11 through the second gate insulating film 7 and the memory retention of the EPROM cannot be maintained. Are encountered.

The problem of leakage of retained electrons in the floating gate 5 also occurs in another nonvolatile semiconductor memory device having a floating gate and a control gate, for example, a flash type EEPROM.

Therefore, the present invention prevents the leakage of retained electrons from the floating gate to the control gate even in the state of the non-volatile semiconductor memory device in which the second gate insulating film having a small film thickness capable of operating at high speed is used, and long-term operation is prevented. It is an object of the present invention to provide a non-volatile semiconductor memory device that enables stable memory retention.

[0008]

In order to solve the above problems and to solve the above objects, according to the present invention, a first gate insulating film formed on a semiconductor substrate and a first gate insulating film A nonvolatile semiconductor memory device having a floating gate formed on the floating gate, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, There is provided a nonvolatile semiconductor memory device in which the materials of the floating gate and the control gate are formed of materials having different work functions. Specifically, the floating gate is formed to have an opposite conductivity to the semiconductor substrate, and the control gate is formed to have the same conductivity as the semiconductor substrate.

[0009]

When the floating gate and the control gate are formed to have different work functions, a difference in energy level exists in the second gate insulating film between the floating gate and the control gate even before injecting electrons into the floating gate. To do. However, this energy level difference is small. The electric field strength applied to the second gate insulating film is small, and in this state, electrons do not leak from the floating gate to the control gate. When electrons are injected into the floating gate, a difference in energy level occurs in the second gate insulating film, but the slopes thereof are in opposite directions, and the difference in energy level is kept small by an amount corresponding to the energy gap. It
Therefore, the phenomenon that the electrons injected into the floating gate penetrate the second gate insulating film and leak to the control gate does not occur. In order to make the work functions different, the conductivity of the semiconductor substrate and the conductivity of the floating gate are reversed, and the conductivity of the control gate and the conductivity of the floating gate are reversed, in other words, the conductivity of the control gate and the semiconductor substrate. Make the same sex. With this configuration, the film thickness of the second gate insulating film can be reduced without deteriorating the memory retention characteristic, and the operation speed of the nonvolatile semiconductor memory device can be improved.

[0010]

1 is a sectional view of an EPROM as an embodiment of a nonvolatile semiconductor memory device of the present invention. EPR in Figure 1
OM is, p ⁺ form silicon substrate 1, a first gate insulating film 3 of SiO _2, n ⁺ form polysilicon floating gate 5, a second gate insulating film 7 of SiO _2, p ⁺ form polysilicon control gate 11, It has a side wall 19, a source formation region 15, and a drain formation region 17. Floating gate 5 is made into n ^{+ type} floating gate 5 by doping polysilicon (P) with phosphorus (P), for example. The control gate 11 is formed by doping polysilicon with, for example, boron (B) to form the p ^{+ -type} control gate layer 11.

The energy band of the EPROM shown in FIG. 1 is shown in FIG. As shown in FIG. 2A, from left to right,
The conduction level E _C , the Fermi level E _F , and the valence level E _V are shown. 2B is an energy band diagram before injecting electrons into the floating gate 5, FIG.
(C) shows an energy band after electrons are injected into the floating gate 5. The energy level in the silicon substrate 1 and the energy level in the floating gate 5 sandwiching the first gate insulating film 3 having the thickness d1 before electron injection are equal, but sandwiching the second gate insulating film 7 having the thickness d2. However, the energy level in the floating gate 5 and the energy level in the control gate 11 are different due to the difference in work function.

As shown in FIG. 2C, considering the energy band after electron injection, the potential ΔV2, which is the change in energy level in the second gate insulating film 7 having the thickness d2, is
It becomes smaller than the potential ΔV1 shown in FIG. 6 by a size corresponding to the energy gap of silicon. For example, the potential ΔV2 is smaller than the potential ΔV1 by about 1 eV. As a result, leakage of electrons from the floating gate 5 to the control gate 11 is prohibited and the EPROM
The loss of the value stored in the can be prevented. The operation principle of the EPROM shown in FIG. 1 follows the characteristic diagram shown in FIG.

In a nonvolatile semiconductor memory device such as an EPROM having the floating gate 5 and the control gate 11, the voltage V _FG of the floating gate 5 is increased under the write bias condition in order to improve the writing speed to the floating gate 5. There is a need. The floating gate voltage V _FG is defined by the following formula. V _FG = V _CG · C ₂ / (C ₁ + C ₂ ) ... (1) where V _CG is the voltage applied to the control gate 11, and C ₁ is the capacitance in the first gate insulating film 3. , C ₂ are capacitances in the second gate insulating film 7. By reducing the thickness d2, the floating gate voltage V _FG can be increased and the speed of the EPROM can be improved. According to this embodiment described above, even if the thickness d2 of the second gate insulating film 7 is thinned, the potential ΔV2 is low, so that the leakage of electrons can be prevented and the memory retention characteristic does not deteriorate. That is, the operation speed can be improved without deteriorating the memory retention characteristic.

Consider the effect of changing the control gate 11 from n ^{+ type} polysilicon to p ^{+ type} polysilicon. The threshold value V _{th of the} MOS transistor is expressed by the following equation. _{V th = 2φ F + φ MS} + (2ε S q / N A) 1/2 / C OX + Q / C OX ··· (2) However, phi _F is a Fermi level in the silicon substrate 1, phi _MS is Control gate 11 and silicon substrate 1
Is the work function difference with N _A is the dose concentration to the substrate, C _ox is the capacitance of the second gate insulating film 7, and Q is the fixed charge at the MOS interface. Control gate 11
Is formed of p ^{+ -type} polysilicon, the work function difference φ _{MS in} the second term of the equation (2) changes, and the threshold value V _th changes.

FIG. 3A shows the energy level of the EPROM shown in FIG. 4, and FIG. 3B shows the energy level of the EPROM shown in FIG. As energy levels in the gate oxide film when charges are injected into the floating gate 5, the energy level shown at point A in FIG.
With the energy level indicated by point B in (B), it is shifted to the plus side by about 1V. This shift can control the threshold value by adjusting the ion implantation directly below the gate. Therefore, there is no problem even if the control gate 11 is the same p ^{+ type} as the silicon substrate 1.

When the control gate 11 is polycide, the same effect as described above can be obtained by changing the base from n ^{+ type} polysilicon to p ^{+ type} polysilicon.

The nonvolatile semiconductor memory device of the present invention is not limited to the EPROM described above, but can be applied to other nonvolatile semiconductor memory devices having a floating gate and a control gate. Even in that case, the film thickness of the second gate insulating film can be reduced while maintaining the retention characteristics, and the operation speed of the nonvolatile semiconductor memory device can be improved.

[0018]

As described above, according to the present invention, the operating speed of the nonvolatile semiconductor memory device can be improved without deteriorating the memory retention characteristic.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of an EPROM as an embodiment of a nonvolatile semiconductor memory device of the present invention.

FIG. 2 is a diagram showing energy bands of the EPROM of FIG.

3 is a diagram showing energy bands of the EPROM of FIG. 1 and the EPROM of FIG. 4;

FIG. 4 is a partial cross-sectional view of a conventional EPROM.

FIG. 5 is a diagram showing operating characteristics of an EPROM.

FIG. 6 is a diagram showing an energy band of a conventional EPROM.

[Explanation of symbols]

 1 ... Silicon substrate, 3 ... First gate insulating film, 5 ... Floating gate, 7 ... Second gate insulating film, 11 ... Control gate, 15 ... Source forming region, 17 ... Drain forming region, 19 ... Side wall.

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[Procedure amendment]

[Submission date] March 31, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

As shown in the operating characteristic diagram of FIG . 5 , the EPROM has a threshold voltage ΔV seen from the control gate 9 depending on the presence or absence of electrons injected into the floating gate 5.
_{The th} is changed to correspond to the stored value “0” or “1”. In FIG. 5 , the horizontal axis represents the control gate voltage V _CG and the vertical axis represents the drain current I _D.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction content]

In recent years, as the operating speed of EPROM has been improved, the film thickness (thickness d2) of the second gate insulating film 7 is 10 to 2
It is as thin as 0 nm . When the thickness of the second gate insulating film 7 is reduced in order to increase the operation speed, electrons leak from the floating gate 5 to the control gate 11 through the second gate insulating film 7 and the memory retention of the EPROM cannot be maintained. Are encountered.

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

Claims (2)

[Claims] 1. A first gate insulating film formed on a semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and A nonvolatile semiconductor memory device having a control gate formed on the second gate insulating film, wherein the floating gate and the control gate are formed in different states of work functions. apparatus. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the floating gate is formed to have a conductivity opposite to that of the semiconductor substrate, and the control gate is formed to have a conductivity similar to that of the semiconductor substrate.