JPH05206283A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH05206283A JPH05206283A JP717192A JP717192A JPH05206283A JP H05206283 A JPH05206283 A JP H05206283A JP 717192 A JP717192 A JP 717192A JP 717192 A JP717192 A JP 717192A JP H05206283 A JPH05206283 A JP H05206283A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- metal wiring
- aluminum film
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 79
- 239000002184 metal Substances 0.000 claims abstract description 79
- 238000000059 patterning Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 32
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 32
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 11
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 9
- 238000007796 conventional method Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に半導体装置における多層金属配線の形成方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming multi-layer metal wiring in a semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置における多層金属配線の平面
図である図４，および図４のＸＸ線での断面図であり工
程順の断面図である図５，および図４のＹＹ線での断面
図であり工程順の断面図である図６を合せて参照する
と、従来の多層金属配線の製造方法は、まず、半導体基
板１上に形成された絶縁膜２の上に、スパッタ法により
膜厚０．５μｍ程度のアルミ膜３を形成する〔図５
（ａ），図６（ａ）〕。次に、アルミ膜３をパターニン
グして、アルミ膜３ａからなる第１の金属配線を形成す
る〔図４，図５（ｂ），図６（ｂ）〕。次に、全面にＣ
ＶＤ法により膜厚０．８μｍ程度の層間絶縁膜６を形成
する〔図５（ｃ），図６（ｃ）〕。次に、層間絶縁膜を
選択的にドライエッチング，およびウェットエッチング
し、層間絶縁膜６ａとなし、上部にテーパーを持ってア
ルミ膜３ａに達するスルーホール８を形成する〔図４，
図５（ｄ），図６（ｄ）〕。次に、全面にスパッタ法に
より膜厚０．８μｍ程度のアルミ膜を形成し、このアル
ミ膜をパターニングしてスルーホール８においてアルミ
膜３ａと接続するアルミ膜７からなる第２の金属配線を
形成する〔図４，図５（ｅ），図６（ｅ）〕。2. Description of the Related Art A plan view of a multi-layer metal wiring in a semiconductor device is a cross-sectional view taken along line XX in FIGS. 4 and 4, and a cross-sectional view taken in the order of steps, and cross-section taken along line YY in FIG. Referring also to FIG. 6 which is a drawing and is a cross-sectional view in the order of steps, in a conventional method for manufacturing a multilayer metal wiring, first, a film thickness is formed on an insulating film 2 formed on a semiconductor substrate 1 by a sputtering method. An aluminum film 3 having a thickness of about 0.5 μm is formed [FIG.
(A), FIG. 6 (a)]. Next, the aluminum film 3 is patterned to form a first metal wiring made of the aluminum film 3a [FIG. 4, FIG. 5 (b), FIG. 6 (b)]. Next, C on the entire surface
An interlayer insulating film 6 having a thickness of about 0.8 μm is formed by the VD method [FIGS. 5 (c) and 6 (c)]. Next, the interlayer insulating film is selectively dry-etched and wet-etched to form the interlayer insulating film 6a, and the through hole 8 reaching the aluminum film 3a is formed with a taper on the upper portion [FIG.
5 (d) and 6 (d)]. Next, an aluminum film having a thickness of about 0.8 μm is formed on the entire surface by a sputtering method, and the aluminum film is patterned to form a second metal wiring made of the aluminum film 7 connected to the aluminum film 3a in the through hole 8. [FIG. 4, FIG. 5 (e), FIG. 6 (e)].
【０００３】[0003]
【発明が解決しようとする課題】上述の従来の多層金属
配線の形成方法では、スルーホールにおける第２の金属
配線のステップカバレッジが悪く、この部分に流せる電
流密度に制限が生じ、エレクトロマイグレーションによ
る故障が起りやすくなる。また、スルーホール部におい
て第２の金属配線の窪みが形成されて平坦性が損なわれ
るため、第３の金属配線等の上層の配線に対する制約が
生じ、設計がしにくくなり，かつ集積度が低下する。加
えて、層間絶縁膜にスルーホールを形成する際のフォト
レジスト工程において、第１の金属配線の幅方向に対す
るアライメントマージンを考慮するため、スルーホール
の径が小さくなり、その分コンタクト抵抗が大きくなる
という欠点がある。In the above-described conventional method for forming a multi-layered metal wiring, the step coverage of the second metal wiring in the through hole is poor, and the current density that can be passed through this portion is limited, causing a failure due to electromigration. Is more likely to occur. Further, since the depression of the second metal wiring is formed in the through hole portion and the flatness is impaired, there is a restriction on the wiring in the upper layer such as the third metal wiring, which makes it difficult to design and lowers the degree of integration. To do. In addition, since the alignment margin in the width direction of the first metal wiring is taken into consideration in the photoresist process when forming the through hole in the interlayer insulating film, the diameter of the through hole becomes smaller and the contact resistance becomes larger accordingly. There is a drawback.
【０００４】[0004]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体装置の多層金属配線の形成において、
半導体基板上に形成された第１の絶縁膜上に第１の金属
膜，第２の金属膜，および第３の金属膜からなる積層金
属膜を形成する工程と、この積層金属膜を第１の金属配
線形状にパターニングする工程と、この第１の金属配線
形状の積層金属膜において、第２の金属配線との接続部
にのみ第３の金属膜を残して他の部分の第３の金属膜を
除去し、第１の金属膜，および第２の金属膜からなる第
１の金属配線を形成する工程と、全面に第２の絶縁膜を
形成し、この第２の絶縁膜のエッチバックを行ない、第
３の金属膜の上面を露出させる工程と、全面に第４の金
属膜を形成してこの第４の金属膜をパターニングし、第
３の金属膜を介して第１の金属配線と接続する第４の金
属膜からなる第２の金属配線を形成する工程と、を有し
ている。According to the method of manufacturing a semiconductor device of the present invention, in forming a multilayer metal wiring of a semiconductor device,
A step of forming a laminated metal film including a first metal film, a second metal film, and a third metal film on a first insulating film formed on a semiconductor substrate; Patterning into the metal wiring shape, and in the laminated metal film having the first metal wiring shape, the third metal film is left only in the connection portion with the second metal wiring, and the third metal in other portions. A step of removing the film and forming a first metal wiring consisting of the first metal film and the second metal film, and forming a second insulating film on the entire surface, and etching back the second insulating film. And exposing the upper surface of the third metal film, forming a fourth metal film on the entire surface and patterning the fourth metal film, and then forming a first metal wiring through the third metal film. And a step of forming a second metal wiring made of a fourth metal film connected to the.
【０００５】[0005]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【０００６】半導体装置における多層金属配線の平面図
である図１，および図１のＸＸ線での断面図であり工程
順の断面図である図２，および図１のＹＹ線での断面図
であり工程順の断面図である図３を合せて参照すると、
本発明の一実施例では、まず、半導体基板１上に形成さ
れた絶縁膜２の上に、スパッタ法により膜厚約０．５μ
ｍのアルミ膜３を形成し，このアルミ膜３上にスパッタ
法により膜厚約０．１μｍのタングステンシリサイド膜
４を形成し、このタングステンシリサイド膜４上にスパ
ッタ法により膜厚約０．８μｍのアルミ膜５を形成する
〔図２（ａ），図３（ａ）〕。1 is a plan view of a multi-layered metal wiring in a semiconductor device, and FIG. 2 is a cross-sectional view taken along line XX of FIG. 1 and is a cross-sectional view in the order of steps. FIG. 2 is a cross-sectional view taken along line YY of FIG. Referring also to FIG. 3, which is a cross-sectional view in the order of steps,
In one embodiment of the present invention, first, the film thickness of about 0.5 μm is formed on the insulating film 2 formed on the semiconductor substrate 1 by the sputtering method.
m aluminum film 3 is formed, a tungsten silicide film 4 having a film thickness of about 0.1 μm is formed on the aluminum film 3 by a sputtering method, and a tungsten silicide film 4 having a film thickness of about 0.8 μm is formed on the tungsten silicide film 4. An aluminum film 5 is formed [FIG. 2 (a), FIG. 3 (a)].
【０００７】次に、フォトレジスト膜（図示せず）をマ
スクにした異方性エッチングにより、アルミ膜５，タン
グステンシリサイド膜４，およびアルミ膜３からなる積
層金属膜をパターニングして、第１の金属配線形状を有
したアルミ膜５ａ，タングステンシリサイド膜４ａ，お
よびアルミ膜３ａからなる積層金属膜を得る〔図２
（ｂ），図３（ｂ）〕。次に、第１の金属配線と第２の
金属配線とを接続する部分のみ上記フォトレジスト膜を
残し、このフォトレジスト膜をマスクにしてアルミ膜５
ａの異方性エッチングを行ない、アルミ膜５ｂを残し、
このフォトレジスト膜を除去する。この工程により、タ
ングステンシリサイド膜４ａ，およびアルミ膜３ａから
なる第１の金属配線が形成される〔図１，図２（ｃ），
図３（ｃ）〕。Next, the laminated metal film composed of the aluminum film 5, the tungsten silicide film 4, and the aluminum film 3 is patterned by anisotropic etching using a photoresist film (not shown) as a mask to form a first film. A laminated metal film having an aluminum film 5a having a metal wiring shape, a tungsten silicide film 4a, and an aluminum film 3a is obtained [FIG.
(B), FIG. 3 (b)]. Next, the above-mentioned photoresist film is left only in a portion connecting the first metal wiring and the second metal wiring, and the aluminum film 5 is used as a mask.
a is anisotropically etched to leave the aluminum film 5b,
This photoresist film is removed. By this step, the first metal wiring composed of the tungsten silicide film 4a and the aluminum film 3a is formed [FIG. 1, FIG. 2 (c),
FIG. 3 (c)].
【０００８】次に、全面にＣＶＤ法により例えばシリコ
ン酸化膜からなる膜厚約０．８μｍの層間絶縁膜６を形
成する〔図２（ｄ），図３（ｄ）〕。次に、層間絶縁膜
６のエッチバックを行ない、アルミ膜５ｂの上面を露出
させた層間絶縁膜６ａを形成する〔図１，図２（ｅ），
図３（ｅ）〕。Next, an interlayer insulating film 6 made of, for example, a silicon oxide film and having a thickness of about 0.8 μm is formed on the entire surface by a CVD method [FIG. 2 (d), FIG. 3 (d)]. Next, the interlayer insulating film 6 is etched back to form an interlayer insulating film 6a exposing the upper surface of the aluminum film 5b [FIG. 1, FIG. 2 (e),
FIG. 3 (e)].
【０００９】次に、全面にスパッタ法により膜厚約０．
８μｍのアルミ膜を形成し、これをパターニングして、
アルミ膜５ｂを介して第１の金属配線と接続するアルミ
膜７からなる第２の金属配線を形成する〔図１，図２
（ｆ），図３（ｆ）〕。Next, a film thickness of about 0.
Form an 8μm aluminum film, pattern this,
A second metal wiring consisting of the aluminum film 7 connected to the first metal wiring via the aluminum film 5b is formed [FIGS. 1 and 2].
(F), FIG. 3 (f)].
【００１０】ここで、アルミ膜３の代りに、シリコン入
りアルミ膜，銅およびシリコン入りアルミ膜を用いても
よい。さらに第１の金属配線が半導体基板１と接続され
る場合には、この第１の金属配線の下層にタングステン
シリサイド膜，窒化チタン膜等を敷いてもよい。加え
て、タングステンシリサイド膜４は、窒化チタン膜に代
えることもできる。また、絶縁膜２，層間絶縁膜６ａ
は、シリコン酸化膜，シリコン酸化窒化膜，シリコン窒
化膜のいずれかである。Here, instead of the aluminum film 3, an aluminum film containing silicon, an aluminum film containing copper and a silicon film containing silicon may be used. Further, when the first metal wiring is connected to the semiconductor substrate 1, a tungsten silicide film, a titanium nitride film or the like may be laid under the first metal wiring. In addition, the tungsten silicide film 4 can be replaced with a titanium nitride film. Also, the insulating film 2 and the interlayer insulating film 6a
Is a silicon oxide film, a silicon oxynitride film, or a silicon nitride film.
【００１１】なお、本実施例は２層金属配線を例にした
が、本発明の趣旨は２層に限定されるものではなく、３
層，４層とさらに拡張して適用できることは言うまでも
ない。In this embodiment, the two-layer metal wiring is taken as an example, but the gist of the present invention is not limited to the two-layer metal wiring.
Needless to say, it can be applied by further expanding the number of layers to four.
【００１２】[0012]
【発明の効果】以上説明したように本発明は、３層から
なる積層金属膜の第１層と第２層との金属膜の積層膜に
より第１の金属配線を形成し、３層の積層金属膜の最上
層の金属膜によりコンタクトプラグを形成するため、第
１の金属配線と第２の金属配線との接続部における第２
の金属配線のステップカバレッジが良好になり、エレク
トロマイグレーションによる故障が抑制される。また、
この接続部において第２の金属配線の窪みは形成されず
平坦性が保たれるため、第３の金属配線等の上層の配線
に対する制約はなく、設計がしやすくなり，かつ集積度
が向上する。加えて、このようにして形成した接続部で
は、従来のスルーホールを設けて接続する方法に比較し
て、コンタクト抵抗が小さるなるという利点を有する。As described above, according to the present invention, the first metal wiring is formed by the laminated film of the first layer and the second layer of the laminated metal film composed of three layers, and the laminated structure of three layers. Since the contact plug is formed by the uppermost metal film of the metal film, the second metal layer is formed at the connection portion between the first metal wiring and the second metal wiring.
The step coverage of the metal wiring is improved, and failures due to electromigration are suppressed. Also,
Since the recess of the second metal wiring is not formed in this connection portion and the flatness is maintained, there is no restriction on the wiring in the upper layer such as the third metal wiring, the design is easy, and the integration degree is improved. .. In addition, the connection portion thus formed has an advantage that the contact resistance becomes smaller than that in the conventional method of providing a through hole for connection.
【図１】本発明の一実施例を説明するための平面図であ
る。FIG. 1 is a plan view for explaining an embodiment of the present invention.
【図２】図１のＸＸ線における断面図であり、上記一実
施例を説明するための工程順の断面図である。2A to 2C are cross-sectional views taken along the line XX of FIG. 1, which are cross-sectional views in the order of processes for explaining the one embodiment.
【図３】図１のＹＹ線における断面図であり、上記一実
施例を説明するための工程順の断面図である。3A to 3C are cross-sectional views taken along the line YY of FIG. 1, which are cross-sectional views in the order of processes for explaining the one embodiment.
【図４】従来の多層金属配線の製造方法を説明するため
の平面図である。FIG. 4 is a plan view for explaining a conventional method for manufacturing a multilayer metal wiring.
【図５】図４のＸＸ線における断面図であり、従来の多
層金属配線の製造方法を説明するための工程順の断面図
である。5A to 5C are cross-sectional views taken along line XX of FIG. 4, which are cross-sectional views in order of steps for explaining a conventional method for manufacturing a multilayer metal wiring.
【図６】図４のＹＹ線における断面図であり、従来の多
層金属配線の製造方法を説明するための工程順の断面図
である。6A to 6C are cross-sectional views taken along the line YY of FIG. 4, which are cross-sectional views in the order of steps for explaining a conventional method for manufacturing a multilayer metal wiring.
１ 半導体基板 ２ 絶縁膜 ３，３ａ，５，５ａ，５ｂ，７ アルミ膜 ４，４ａ タングステンシリサイド膜 ６，６ａ 層間絶縁膜 ８ スルーホール 1 Semiconductor Substrate 2 Insulating Film 3, 3a, 5, 5a, 5b, 7 Aluminum Film 4, 4a Tungsten Silicide Film 6, 6a Interlayer Insulating Film 8 Through Hole
Claims (1)
上に第１の金属膜，第２の金属膜，および第３の金属膜
からなる積層金属膜を形成する工程と、 前記積層金属膜を第１の金属配線形状にパターニングす
る工程と、 前記第１の金属配線形状の前記積層金属膜において、第
２の金属配線との接続部にのみ前記第３の金属膜を残し
て他の部分の前記第３の金属膜を除去し、前記第１の金
属膜，および前記第２の金属膜からなる第１の金属配線
を形成する工程と、 全面に第２の絶縁膜を形成し、前記第２の絶縁膜のエッ
チバックを行ない、前記第３の金属膜の上面を露出させ
る工程と、 全面に第４の金属膜を形成し、前記第４の金属膜をパタ
ーニングし、前記第３の金属膜を介して前記第１の金属
配線と接続する前記第４の金属膜からなる第２の金属配
線を形成する工程と、を有することを特徴とする半導体
装置の製造方法。1. A step of forming a laminated metal film comprising a first metal film, a second metal film and a third metal film on a first insulating film formed on a semiconductor substrate, and the lamination. A step of patterning a metal film into a first metal wiring shape; and a step of leaving the third metal film only in a connection portion with the second metal wiring in the laminated metal film having the first metal wiring shape. The step of removing the third metal film in the portion of, and forming a first metal wiring composed of the first metal film and the second metal film; and forming a second insulating film on the entire surface. Etching the second insulating film to expose the upper surface of the third metal film; forming a fourth metal film on the entire surface; patterning the fourth metal film; A third metal film which is connected to the first metal wiring via a third metal film. The method of manufacturing a semiconductor device, characterized in that it comprises a step of forming a metal wiring, a.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP717192A JPH05206283A (en) | 1992-01-20 | 1992-01-20 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP717192A JPH05206283A (en) | 1992-01-20 | 1992-01-20 | Manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05206283A true JPH05206283A (en) | 1993-08-13 |
Family
ID=11658639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP717192A Pending JPH05206283A (en) | 1992-01-20 | 1992-01-20 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05206283A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08111460A (en) * | 1994-08-16 | 1996-04-30 | Nec Corp | Structure of multilayer wiring and fabrication thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6158256A (en) * | 1984-08-29 | 1986-03-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
-
1992
- 1992-01-20 JP JP717192A patent/JPH05206283A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6158256A (en) * | 1984-08-29 | 1986-03-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08111460A (en) * | 1994-08-16 | 1996-04-30 | Nec Corp | Structure of multilayer wiring and fabrication thereof |
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| A02 | Decision of refusal |
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