JPH05204959A - Arithmetic unit - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to an arithmetic device, and an object of the present invention is to provide an arithmetic device that prevents deviation of processed data due to a speed difference between an arithmetic unit and an input / output unit. An input / output unit for inputting / outputting data to / from the outside based on an external synchronizing signal, an arithmetic unit for performing a predetermined arithmetic operation based on data obtained through the input / output unit, and a control signal from the outside Based on the input / output means and a control means for controlling the arithmetic means, the control means, when the input / output means causes a shift in operation timing with the arithmetic means due to an external factor, The timing of both is adjusted by controlling the operation of the arithmetic means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit, and more specifically, for example, a super computer, a super EWS
The present invention relates to an arithmetic device suitable for use in fields such as (Engineering Work Station) and for performing vector processing at high speed. In recent years, in scientific calculation, etc., it is necessary to perform arithmetic processing at high speed. Therefore, for example, many arithmetic devices have been developed to improve the performance of arithmetic units inside processors by using methods such as superscalar, VLIW, and vectorization. Has been done.

Among these, particularly in the fields of image processing, simulation, etc., the same arithmetic operation is frequently repeated, so that a vector processor for performing repeated arithmetic operation at high speed is widely used. The vector processor is optimized for, for example, a DO loop in the FORTRAN language, that is, an iterative operation represented by DO 10 I = 1,100 C (I) = A (I) * B (I) 10 CONTINUE. Have a different architecture.

A process for repeating a certain calculation on a plurality of data is called a vector process, and in an arithmetic unit which performs a large number of repetitive calculations, it is necessary to execute the vector process at high speed.

[0004]

2. Description of the Related Art As a conventional arithmetic unit of this type, there is an arithmetic unit called a vector processor. Here, in a general MPU (Micro Processing Unit), when the above-described iterative multiplication is given 100 times, the multiplication instruction MUL is expanded 100 times. In this case, the instruction Fetching, decoding, reading and writing of operands, etc. are repeated 100 times.

On the other hand, in the vector processor, when multiplication, other operation, input / output instruction, etc. are given as vector instructions, the number of repetitions (vector length) designated in advance by the register is processed continuously by one instruction. Therefore, 99 instruction fetches, decode times, etc. can be omitted. Therefore, by performing the vector processing using the vector processor, the calculation can be performed with high efficiency, and the total calculation time can be greatly shortened.

Further, since the vector processor has a plurality of arithmetic units so that other instructions existing in the same loop and input / output instructions can be executed in parallel, for example, the DO loop in the FORTRAN language described above is used. If an addition instruction is added inside the table, that is, DO 10 I = 1,100 C (I) = A (I) * B (I) F (I) = D (I) + E (I) 10 CONTINUE If the repeated calculation is performed, the efficiency of the calculation is further improved.

[0007]

However, in general, the operation of the vector processor is performed in synchronization with the clock input from the outside, and the number of clocks required for one operation in the arithmetic unit is It is determined by the processor and is constant, but in the input / output device, the number of clocks is not always constant, depending on the speed of the connected memory and external factors.

That is, when each operation and the input / output device are operated in parallel in the same loop, the number of clocks required for one loop processing is determined by the number of clocks of the input / output device. In this case, when the operation unit is faster than the input / output unit, there is a problem that the relationship with the data is deviated. This will be described with reference to FIG.

FIG. 8 is a diagram showing the timing when the input / output device operates in 3 clocks and the multiplier operates in 2 clocks in the conventional vector processor. First, the multiplier performs the operation 1. In this case, since the input / output device outputs the data of the array 1 as the output 1 in synchronization with the data, the correct operation is performed. Then, since the output of the input / output device is still the output 1, the array for supplying the data is also the array 1, and the operation is performed with the same data as the operation 1 as it is.

In order to prevent such a problem, for example, the memory used is provided with specifications such as only two clock operation,
It may be possible to optimize by limiting the external memory speed, or to synchronize the operation unit with the operation of the I / O unit. In this case, in the former example, the degree of freedom of the system becomes narrow. In the latter example, complicated hardware is required because complicated control is required.
There arises a new problem that the high speed of the arithmetic unit cannot be utilized.

[Purpose] Therefore, an object of the present invention is to provide an arithmetic unit for preventing deviation of processed data due to a speed difference between an arithmetic unit and an input / output unit.

[0012]

In order to achieve the above-mentioned object, an arithmetic unit according to the present invention is obtained through an input / output unit for inputting / outputting data to / from the outside based on an external synchronization signal, and the input / output unit. The control means includes an arithmetic means for performing a predetermined arithmetic operation on the basis of data, an input / output means based on a control signal from the outside, and a control means for controlling the arithmetic means. When a difference occurs in the operation timing with the arithmetic means due to a factor, the timings of both are adjusted by controlling the operation of the arithmetic means.

As a method of controlling the operation of the arithmetic means by the control means, a method of controlling a synchronization signal supplied to the arithmetic means can be considered.

[0014]

According to the present invention, even when there is a difference in processing speed between the input / output means and the arithmetic means, when the input / output means is delayed with respect to the arithmetic means, the control means controls the input / output means. By stopping the operation of the calculating means by the amount of delay, the input / output means and the calculating means are synchronized with each other even if no special control is applied to the calculating means.

That is, the deviation of the processed data due to the speed difference between the arithmetic unit and the input / output unit is prevented.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. 1 to 3 are diagrams showing an embodiment of an arithmetic unit according to the present invention, FIG. 1 is a block diagram showing a schematic configuration of the arithmetic unit of the present embodiment, and FIG. 2 is an overall configuration of a vector processor of the present embodiment. FIG. 3 is a block diagram showing the configuration of the main part of FIG.

First, the structure will be described. The vector processor 1 which is the arithmetic unit of the present embodiment is roughly divided into an input / output unit 2 which is an input / output unit, an arithmetic unit 3, and a control unit 4, and the arithmetic unit 3 is an array vector register 5,
It is composed of a multiplier 6 and an adder 7. Incidentally, 8 is an external memory.

The input / output unit 2 is a load / store pipe (L / S pipe) for inputting / outputting, and when executing a load instruction, the data stored in the external memory 8 is stored in the array vector register (VR) 5. When transferring and executing the store instruction,
The data stored in the array vector register 5 is transferred to the external memory 8. It should be noted that 2 during continuous operation
The transfer is performed in the clock cycle, but the operation changes depending on the speed of the external memory 8.

The calculating means 3 is a multiplier (M
UL pipe) 6 and an adder (ADD pipe) 7 that performs addition processing. Each arithmetic unit 6, 7 performs an arithmetic operation based on the data stored in the array vector register 5 and outputs the arithmetic result. For writing into the vector register 5 for use. The arithmetic units 6 and 7 operate independently of each other in parallel,
In continuous operation, the calculation is performed in units of one clock.

The memory 8 is an externally provided memory and is required to operate in two clocks when it is optimized for the input / output device 2. As shown in FIG. 4, the control means 4 comprises a vector processor control circuit 9 and a clock control circuit 10, and the vector processor control circuit 9
Is a control circuit of the vector processor 1, which controls the input / output unit 2 and each of the arithmetic units 6 and 7 and controls the interface with the outside by an instruction given from the outside.

The clock control circuit 10 operates on the basis of the control signal from the vector processor control circuit 9 to determine each of the arithmetic units 6, 6.
It controls the clock signal supplied to 7. In the figure, BS # is a bus start signal, DS # is a data strobe signal, A31-00 is an address signal, and DC #.
Is a data complete signal, T1, Ti, T2, T2W
Is an internal state signal output by the vector processor control circuit 9.

FIG. 5 is a state transition diagram of the internal state.
The state Ti is an idle cycle of the bus and indicates a state in which the input / output device 2 is stopped, and is in this state when the vector processor 1 is reset by the initialization signal. State T1 indicates the activation state of the bus,
When the operation of the input / output device 2 is started by an input / output signal or the like, the transition shown in FIG.
Output of address A31-00 and bus start signal B
Assert S # and so on.

The state T2 indicates a data access state of the bus and is used for data transfer by the external memory 8 and the data bus. In this case, when the data strobe signal DS # is asserted, the data complete signal DC # is received from the outside, and the assertion of the data complete signal DC # is detected in this state, if the input and output are continuous, When the data complete signal DC # is in the negated state, the transition as shown in e is performed and the state T1 is returned to the state T1. To state T2W.

The state T2W indicates the wait state of the bus, and the loop shown in i in the figure is repeated until the data complete signal DC # is asserted. When the data complete signal DC # is asserted, the state T2W is reached. Make the same transition as. The input / output unit 2 operates in synchronization with the above-mentioned state signal. When the external memory 8 can operate in two clocks, the data complete signal DC # is asserted in the state T2 and the internal state is T1. , T2 are repeated.

When the memory operates in three clocks, the assertion of the data complete signal DC # is delayed by one clock, so that the three states of T1, T2 and T2W are repeated. In this case, since the arithmetic units 6 and 7 are operating in units of one clock, the input / output unit 2 is operating.
The period of the states T2 and T2W is recognized as a shift at the time of repetition.

In the control circuit 4, the array vector register 5 which is the arithmetic means 3 and the respective arithmetic units 6 and 7 are internally masked with the external clock by the logical sum of the states T2 and T2W in the clock control circuit 10. Clock I
Supply CLK. Next, the operation will be described. FIG. 6 is a timing chart for explaining the internal operation when a memory that operates with two clocks is connected.

In FIG. 5, an external clock CL of 5 clocks is used.
With respect to K, the input / output device 2 has a loss corresponding to two in the state T2, but since the internal clock ICLK is advanced by only 3 clocks, the arithmetic means 3 operating by the internal clock ICLK is in phase as a whole. The gap does not occur. FIG. 7 is a timing chart for explaining the internal operation when a memory operating with 3 clocks is connected.

In FIG. 7, the external clock CL of 7 clocks is used.
For K, the input / output device 2 has a loss of 4 clocks corresponding to two of the state T2 and the state T2W, but since the internal clock ICLK advances only 3 clocks, in this case also, the above 2 clocks are used. As in the case where the operating memory is connected, the arithmetic means 3 does not shift in phase as a whole.

As described above, in the present embodiment, even if there is a speed difference between the input / output unit and the arithmetic unit in the vector processor, the operation can be performed without data shift. Further, since no special control circuit is added to the arithmetic unit, it is possible to operate independently of the input / output unit without impeding the performance of the arithmetic unit. Furthermore, since the speed difference is controlled by the data complete signal DC # which is generally used for bus control, a memory of any speed can be connected without requiring a special circuit as an external circuit.

Although the above embodiment has been described by taking the case of being applied to the vector processor as an example, the present invention is not limited to this, and for example, a DSP (Digital Signal Process) of FIFO format is used.
r), etc., can be applied to general systems in which an external memory or the like is synchronized with an internal arithmetic unit or the like.

[0031]

According to the present invention, even when there is a difference in processing speed between the input / output means and the arithmetic means, when the delay of the input / output means with respect to the arithmetic means occurs, the control means is used. By stopping the operation of the calculating means by the amount of delay of the input / output means, the input / output means and the calculating means can be synchronized with each other without special control of the calculating means.

Therefore, it is possible to prevent the deviation of the processed data due to the speed difference between the arithmetic unit and the input / output unit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an arithmetic unit of this embodiment.

FIG. 2 is a block diagram showing an overall configuration of a vector processor of this embodiment.

FIG. 3 is a block diagram showing a main configuration of FIG.

FIG. 4 is a diagram showing a configuration of a main part of a calculation means of the present embodiment.

FIG. 5 is a state transition diagram of internal states.

FIG. 6 is a timing chart for explaining an internal operation when a load instruction is executed when a memory that operates with two clocks is connected.

FIG. 7 is a timing chart for explaining an internal operation at the time of executing a load instruction when a memory that operates with three clocks is connected.

FIG. 8 is a diagram for explaining a problematic operation of a conventional vector processor.

[Explanation of symbols]

 1 vector processor 2 input / output unit (input / output unit) 3 arithmetic unit 4 control unit 5 array vector register 6 multiplier 7 adder 8 memory 9 vector processor control circuit 10 clock control circuit

Claims (2)

[Claims] 1. Input / output means for inputting / outputting data to / from the outside based on an external synchronizing signal, arithmetic means for performing a predetermined arithmetic operation based on data obtained through the input / output means, A control means for controlling the input / output means and the arithmetic means based on a control signal, wherein the input / output means causes a shift in an operation timing between the input / output means and the arithmetic means. In the case of the above, the arithmetic device is characterized in that the timings of the both are adjusted by controlling the operation of the arithmetic means. 2. The arithmetic unit according to claim 1, wherein the control unit controls the operation of the arithmetic unit by controlling a synchronizing signal supplied to the arithmetic unit.