JPH0520352A - Adder circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide an adder circuit that can reduce the area when integrated into an IC with a simple circuit configuration and that can calculate a vector amount at high speed. A high-order or low-order n / 2 bit is selected by high-order / low-order switching selectors 21-26 from registers 11-16 holding respective components of two vector quantities each of which has n bits. The addition input selectors 27 to 30 select the n / 2-bit component input to each of the adders 31 and 32. First, the lower side n / 2 is added by the adders 31 and 32.
The bits are added, and then the upper n / 2 bits are added in consideration of the carry of the addition result of the lower n / 2 bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder circuit for calculating a new vector amount by adding each component of a vector amount represented by a large number of bits (n bits).

[0002]

2. Description of the Related Art Conventionally, an adder circuit has been used in which an algorithm for adding new vector quantities to obtain a new vector quantity is configured by hardware. FIG. 3 is a diagram schematically showing an example of such a conventional adder circuit. here,
Each component is represented by n bits. A = (x ₁ , y ₁ , z ₁ ) ... (1) The vector quantity and each component are also represented by n bits. B = (x ₂ , y ₂ , z ₂ ) ... (2) The vector quantity is added to obtain C = (X, Y, Z) ... (3) where X = x ₁ + x ₂ In order to obtain a new vector amount C of Y = y ₁ + y ₂ Z = z ₁ + z _2, three adders 51, 52, 53 for adding n-bit data or the like are provided, and each adder 51, X ₁ + at 52 and 53 respectively
The addition operations x ₂ , y ₁ + y ₂ , and z ₁ + z ₂ are performed in parallel. As a result, addition is performed for each component, and a new vector amount C is obtained.

[0003]

The above adder circuit is provided with, for example, only one n-bit adder, x ₁ + x ₂ , y ₁
This has the advantage of being able to perform operations at higher speed than an adder circuit that performs + y ₂ , z ₁ + z ₂ operations in sequence, but on the other hand, three adders are required and the circuit configuration becomes very complicated However, there is a problem that it becomes a large-area adder circuit when it is converted.

Further, when each component of the vector is a numerical value represented by a large number of bits such as n = 32 bits or n = 64 bits, the carry propagation speed in the addition operation is simply a large number of bits. It is much slower than the ratio of, so that the circuit configuration is complicated and the large area IC is used.
There is also a problem that the processing speed is not so high in comparison with the addition circuit of.

The present invention has been made in view of the above circumstances, and provides an adder circuit capable of reducing an area when integrated into an IC with a simple circuit configuration and capable of calculating a vector quantity at high speed. The purpose is that.

[0006]

In order to achieve the above object, the adder circuit according to the present invention adds a first vector amount and a second vector amount in which each component is represented by n bits, for each component. In the adder circuit for obtaining the third vector quantity by doing so, a plurality of adding means for adding the data of n / 2 bits each, and the plurality of adding means are first used to calculate the first and second vector quantities. The lower n / 2 bits of each component are added together, and then the upper n / 2 bits of the first and second vector quantities are considered in consideration of the carry of the operation result of the lower n / 2 bits. Data control means for controlling the data so as to add the load is provided.

[0007]

The adder circuit of the present invention is provided with a plurality of adder means for adding n / 2 bits, and each component represented by n bits is divided into upper n / 2 bits and lower n / 2 bits. Since the lower n / 2 bits are first added and then the upper n / 2 bits are added, the carry propagation speed at the time of the addition operation is considerably high, and therefore the operation processing is performed at high speed. It can be performed. Further, the adder circuit of the present invention requires a smaller number of adder means as compared with the conventional one, as shown in an embodiment to be described later, so that when added to an IC, a smaller area than the conventional one is sufficient.

[0008]

1 is a block diagram of an adder circuit according to an embodiment of the present invention, and FIG. 2 is a time chart thereof. The adder circuit according to the present embodiment has registers 11 to 16 for holding components of two vector quantities each of which has n bits, and an upper or lower one of the n-bit components held in the registers 11 to 16. Upper / lower switching selectors 21 to 26 for selecting n / 2 bits, and an addition input selector 2 for selecting n / 2-bit components input to the adders 31 and 32.
7 to 30 and an adder 31 for adding the n / 2-bit components selected by the addition input selectors 27 to 30,
32, carry registers 33 to 35 for holding carry signals of addition results, phase matching registers 36 to 39 for temporarily holding addition results of n / 2 bits, and n bits of each vector amount of the addition results. The registers 42 to 44 for holding the components. In addition, the adder circuit of this embodiment has two vector quantities A = (x ₁ , y ₁ , z ₁ ) and B = (x ₂ , y ₂ , z ₂ ) and vector quantity C =
(X, Y, Z) (where X = x ₁ + x ₂ , Y = y ₁ +
y ₂ , Z = z ₁ + z ₂ ) is obtained.

Next, the operation of the adder circuit of this embodiment will be described. First, at the timing of clock 0 shown in FIG. 2, the components x ₁ , x _2, y ₁ , y ₂ ,
z ₁ and z ₂ are input and held. Each of these components is represented by n bits. Along with that, the upper / lower switching selectors 21 to 26 are used to register each register 11.
The lower n / 2 of 16 are selected.

Further, at the timing of clock 0, the lower n / 2 bits of x ₁ and x ₂ are selected by the addition input selectors 27 and 28, respectively, and the addition input selectors 29 and 29 are selected.
Is lower n / 2 bits select the In 30 respectively y _1, y _2, thereby each of the adders 31 and 32 for adding the n / 2-bit data, x _1, x ₂ of the lower n / 2 Bits, the lower n / 2 bits of y ₁ and y ₂ are input, and x ₁ (lower n / 2 bits) + x ₂ (lower n / 2 bits) and y ₁ (lower n / Two
The operation of (bit) + y ₂ (lower n / 2 bits) is performed.

Next, at the timing of clock 1, x ₁ (lower n / 2 bits) + x ₂ (lower n / 2 bits) and y ₁
Carry signals x _c and y _c by (lower n / 2 bits) + y ₂ (lower n / 2 bits) are input to carry registers 33 and 34, respectively, and phase adjustment registers 36 and
X (lower side n / 2 bits) and Y (lower side n / 2 bits) are input to 37 and held respectively. At the timing of this clock 1, the carry y _c is input to the adders 31 and 32 via the lower n / 2 bits of z ₁ and z ₂ , the upper n / 2 bits of y ₁ and y ₂ , and the carry selector 41. And z ₁ (lower n / 2 bits) + z ₂ (lower n / 2 bits), y ₁ (upper n / 2 bits) + y ₂ (upper n / 2 bits) + y _c are respectively calculated.

Next, at the timing of the clock 2, the carry signal z _c by z ₁ (lower n / 2 bits) + z ₂ (lower n / 2 bits) is input to the carry register 35, and also to the phase adjustment registers 38 and 39. Y (upper side n / 2 bits) and Z (lower side n / 2 bits) are input and held respectively. Further, at the timing of this clock 2, the upper n / 2 bits of x ₁ and x ₂ are added to the adders 31 and 32, z ₁ ,
upper n / 2 bits of z ₂ and carry selector 40,
Carries x _c and z _c are input via 41, and x ₁ (upper n / 2 bits) + x ₂ (upper n / 2 bits) + x _c , z ₁ (upper n / 2 bits) + z ₂ (upper), respectively. n
(/ 2 bits) + z _c is calculated.

Further, at the timing of the clock 3, the adder 3
X (upper n / 2 bits), Z output from 1, 32
(Upper n / 2 bits) are registers 42 and 44, respectively.
To the phase adjustment register 3
Inputs X (lower n / 2 bits), Y (upper n / 2 bits + lower n / 2 bits), Z (lower n / 2 bits) to registers 42, 43 and 44 from 6, 37, 38 and 39, respectively. As a result, each component of the vector amount C = (X, Y, Z) is formed in the registers 42, 43, 44.

As described above, in the present embodiment, two n / 2-bit adders 31 and 32 are provided, and even if the additional circuits are included, they are integrated into an IC as compared with the case of the conventional example described above. The area is reduced.

Further, since the addition of n / 2 bits is performed here, the propagation of the carry during the operation is faster than the case where the addition of n bits is performed, so that a high-speed addition circuit is realized. it can.

[0016]

As described above, according to the present invention, when each component of the vector amount to be added is represented by n bits, a plurality of adding means for adding data of n / 2 bits or so. And is configured to add n / 2 bits of the lower side of each component of the vector quantity, and then add n / 2 bits of the upper side using this adding means. As a result, it is possible to provide an adder circuit which, when integrated into an IC, has a smaller area than a conventional one and can perform high-speed processing.

[Brief description of drawings]

FIG. 1 is a block diagram of an adder circuit according to an embodiment of the present invention.

FIG. 2 is a time chart of the adder circuit shown in FIG.

FIG. 3 is a diagram schematically showing an example of a conventional adder circuit.

[Explanation of symbols]

 11 to 16 registers 21 to 26 upper / lower switching selector 27 to 30 addition input selector 31, 32 adder 33 to 35 carry register 36 to 39 phase adjustment register 40, 41 carry selector 42 to 44 register

Claims (1)

Claim: What is claimed is: 1. An adder circuit for obtaining a third vector amount by adding a first vector amount and a second vector amount in which each component is represented by n bits, for each component. In a plurality of addition means for adding data of n / 2 bits or so, and in the plurality of addition means, first, the lower n / 2 bits of each component of the first and second vector quantities And then carry out the carry of the operation result between the lower n / 2 bits and the upper n / 2 of the first and second vector quantities.
An adder circuit comprising: a data control unit that controls data so as to add bits bit by bit.