JPH0519988B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor three-dimensional circuit element, in which a semiconductor three-dimensional circuit element is manufactured by sequentially laminating a single crystal semiconductor film and a single crystal insulating film.

[Conventional technology]

In general, semiconductor thin films for active layers, thin films for electrodes and wiring, and thin films for insulation are sequentially laminated to form three-dimensional circuit elements in order to increase the density and integration of circuits. For example, in order to obtain semiconductor three-dimensional circuit elements with excellent characteristics,
As described in the specification and drawings of No. 229763, attempts have been made to use single-crystal materials for each of the materials constituting the circuit element, and to laminate each material in the single-crystal state. .

Conventionally, a semiconductor three-dimensional circuit element having, for example, a pn junction type photo sensor in the uppermost layer and a MOS transistor in the lower layer is manufactured according to the following procedure. First, as shown in FIG. 2a, impurities are diffused onto, for example, an n-type single crystal silicon film 1 using a silicon oxide film as a diffusion mask to form a p-type source region 2 and a drain region 3. After removing the oxide film, a single crystal spinel film 4 is formed as a gate insulating film by the CVD method, and the interface between the silicon film 1 and the spinel film 4 is oxidized through the formed spinel film 4 to form a silicon oxide film 5. Then, a double gate insulating film 6 of a spinel film 4 and a silicon oxide film 5 is formed, a contact hole 7 is formed in the insulating film 6 on the source region 2 and drain region 3, and then a contact hole 7 is formed on the spinel film 4 by CVD method. A single crystal silicon film is then formed in the contact hole 7 and selectively etched to form a gate electrode 8 and a wiring layer 9 in a predetermined pattern.

Next, as shown in FIG. 2b, a single crystal spinel film 10 as an interlayer insulating film is formed on the spinel film 4, the electrode 8 and the wiring layer 9 by CVD method,
As shown in figure c, after forming a single crystal silicon film 11 on the spinel film 10 by CVD method,
By selective etching, a through hole 12 was formed in the silicon film 11 and spinel film 10 on the wiring layer 9, and as shown in FIG. The upper surface of the wiring layer 9 is oxidized to form a silicon oxide film 13, and the silicon oxide film 13 on the silicon film 11 is partially removed to form the silicon film 11.
Using the remaining silicon oxide film 13 as a diffusion mask, 10 ¹⁸ ~
A diffusion layer 14 is formed by diffusing impurities at a concentration of ^{10 20} cm ^-3 , and a pn junction 15 is formed at the boundary between the silicon film 11 and the diffusion layer 14 .

At this time, during the formation process of the diffusion layer 14, the upper surface of the diffusion layer 14 is oxidized to form the silicon oxide film 16, so after the formation of the diffusion layer 14 and the silicon oxide film 16, as shown in FIG. At the same time, the silicon oxide film 13 on the wiring layer 9 exposed in the through hole 12 is removed by selective etching, and a contact hole 17 is formed in the silicon oxide film 16.
form.

Furthermore, as shown in FIG. 2e, an aluminum wiring layer 18 is formed on the silicon oxide films 13 and 16 and in the through holes 12 and contact holes 17, and the silicon film 1, the source region 2, the drain region 3, and the insulating film are formed. 6. A lower layer MOS transistor consisting of an electrode 8 and a wiring layer 9 and a pn junction type photo sensor consisting of a silicon film 11 and a diffusion layer 14 are electrically connected by a wiring layer 18, and a silicon oxide film 16 for antireflection is connected. p-n junction 1 via
A photocurrent generated by the incident light on 5 is transmitted to a MOS transistor or the like.

Although not shown in FIG. 2, the lower layer of the silicon film 1 is provided with a shift register for driving the aforementioned MOS transistors and an arithmetic circuit section for signal comparison, thereby forming a three-dimensional circuit element. There is.

[Problem that the invention seeks to solve]

However, in the method described above, since the pn junction 15 is formed by diffusion, the impurity concentration of the diffusion layer 14 is as high as 10 ¹⁸ to 10 ²⁰ cm ^-3 , and the light absorption coefficient of the diffusion layer 14 becomes large, resulting in an increase in the height of the photo sensor. There is a limit to the sensitivity, and furthermore, when forming the through hole 12, it is necessary to etch the silicon film 11 and the spinel film 10 under different conditions. There are problems in that the end point of the through hole 12 must be detected separately, and the formation of the through hole 12 becomes very complicated.

Further, the wiring layer 18 connecting the lower layer MOS transistor and the upper layer photo sensor is connected to the p-n junction 15.
Since the photo sensor is formed so as to cover a part of the through hole 12 and space must be secured for the through hole 12, the effective light receiving area of the photo sensor is limited and a large photocurrent cannot be extracted. When forming a solid-state image sensor by arranging a large number of pixels in a shape, in order to obtain a high-precision solid-state image sensor with excellent resolution, it is necessary to make each pixel area smaller and increase the number of pixels as much as possible. Due to the effective light-receiving area of the photo sensor of the three-dimensional circuit element corresponding to each pixel, a problem arises in that the photo sensor cannot be miniaturized beyond a certain level and the number of pixels cannot be increased.

[Means for solving problems]

The present invention has been made with the above points in mind, and aims to simplify the process of forming through holes and expand the pn junction region, and provides a semiconductor element having a pn junction on a semiconductor element formed in a single crystal semiconductor film. A method for manufacturing a semiconductor three-dimensional circuit element comprising the steps of forming a single crystal insulating film to cover the semiconductor element, and forming a through hole in the single crystal insulating film for connecting with a part of the semiconductor element. forming a p-type or n-type first single-crystal semiconductor film on the single-crystal insulating film and in the through hole; This is a method for manufacturing a semiconductor three-dimensional circuit element, comprising the steps of: stacking second single crystal semiconductor films of a shape to form a pn junction.

[Effect]

Therefore, in the present invention, a through hole is formed in a single crystal insulating film, a p-type or n-type first single crystal semiconductor film is formed on the single crystal insulating film and in the through hole, and then a first p-type or n-type single crystal semiconductor film is formed. A second n-type or p-type single crystal semiconductor film is formed on the single crystal semiconductor film, and there is no need to form a through hole in the single crystal semiconductor film, and the through hole forming process is simplified. The first single crystal semiconductor film within the through hole is used as a wiring layer between the pn junction and the lower layer device, eliminating the need for a new wiring layer between the upper and lower layers, and expanding the pn junction area to the maximum extent.

Furthermore, the pn junction is formed by stacking the second single crystal semiconductor films instead of by diffusion, and the impurity concentration of the second single crystal semiconductor film on the upper layer side is significantly reduced compared to the case of diffusion.

〔Example〕

Next, the present invention will be explained in detail with reference to FIG. 1, which shows one embodiment of manufacturing a semiconductor three-dimensional circuit element having a pn junction type photo sensor in the uppermost layer and a MOS transistor in the lower layer.

First, as shown in FIG. 1A, as in the case of FIG. After forming the region 20 and the drain region 21 and removing the silicon oxide film, a double gate insulating film 2 consisting of a single crystal spinel film 22 and a silicon oxide film 23 formed by oxidation of the interface between the silicon film 19 and the spinel film 22 is formed.
4, and a contact hole 25 is formed in the insulating film 24 on the source and drain regions 20 and 21.
Thereafter, a p-type single crystal silicon film is formed on the spinel film 22 and in the contact hole 25 and selectively etched to form a gate electrode 26 and a wiring layer 27 in a predetermined pattern, thereby forming a lower layer MOS transistor 28.

Next, as shown in FIG. 1b, the spinel film 22, electrode 26 and wiring layer 27 are
A single-crystal spinel film 29 as an interlayer insulating film is formed on top, and a through hole 30 is formed in the spinel film 29 by selective etching as shown in figure c, and then a through hole 30 is formed by CVD method as shown in figure d. ,
A p-type single crystal silicon film 31, which is the first single crystal semiconductor film, was deposited on the spinel film 29 and in the through hole 30 at a temperature of 950° C. using diborane [B ₂ H ₆ ] gas as a doping gas for 10 ¹⁸ cm ^- The silicon film ³¹ is formed to a thickness of 3 μm while doping with boron [B] at a concentration of 3 μm, and the doped silicon film 31 is selectively etched into a predetermined shape.

Furthermore, as shown in FIG. 1e, an n-type single crystal silicon film 32, which is a second single crystal semiconductor film, is deposited on the silicon film 31 at a temperature of 950° C. by the CVD method.
was formed to a thickness of 5 μm while doping phosphorus [P] at a concentration of 10 ¹⁵ cm ⁻³ using phosphine [PH ₃ ] gas as a doping gas, and both silicon films 31, 3
After forming a pn junction 33 at the boundary between the doped silicon films 32 and 2, the top surface of the doped silicon film 32 is mirror-polished to make it flat, and then the top surface of the silicon film 32 is oxidized to form a silicon oxide film 34 as an antireflection film. The uppermost pn junction type photo sensor 35 is formed.

Although not shown in FIG. 1, in the lower layer of the silicon layer 19, there is a shift register for driving the MOS transistor 28 and an arithmetic circuit section for signal comparison, etc., as in the case of FIG. 2 described above. A three-dimensional circuit element is constituted by the three-dimensional circuit element.

Therefore, since the MOS transistor 28 and the photo sensor 35 are electrically connected by the silicon film 31 in the through hole 30, there is no need to provide an aluminum wiring layer 18 as in the conventional case.
Moreover, it is only necessary to form the through hole 30 in the spinel film 29, which simplifies the process of forming the through hole 30 compared to the conventional case, and eliminates the need for a wiring layer or through hole on the photo sensor 35 side. It is possible to expand the pn junction 33 area to the maximum, and it can be formed on the same area of the substrate.
As a result of comparing the photocurrents output from the pn junction 33 and the conventional pn junction 15, the former is about 25% higher than the latter, and the high output photo sensor 35
can be obtained.

Furthermore, the pn junction 33 is connected to both silicon films 31, 3.
Since it is formed by lamination using the CVD method in step 2,
The impurity concentration of the silicon film 32 on the incident side can be significantly reduced compared to conventional diffusion, and the quantum efficiency of the silicon film 32 on the incident side has increased from 78% to 93% at the luminous efficiency peak wavelength λ = 555 nm. At the same time, the wavelength λ of the silicon film 32 is 555 nm.
The light absorption coefficient for incident light is also about 7×10 ³ cm ⁻¹ , which is smaller than that of the conventional photo sensor 35, making it possible to increase the sensitivity and miniaturize the photo sensor 35.

In addition, the setting of the spectral sensitivity of the photo sensor 35 is
This can be easily done by adjusting the junction depth of the pn junction 33 by adjusting the thickness of the silicon film 32.

〔Effect of the invention〕

As described above, according to the method of manufacturing a semiconductor three-dimensional circuit element of the present invention, the process of forming the through hole 30 can be simplified, and the pn junction 33 area can be expanded to the maximum to allow the photo sensor 35
It is possible to expand the effective light-receiving area of the
pn junction 33 is not diffused but silicon film 31,3
Since it is formed by lamination using the CVD method in step 2,
It is possible to reduce the light absorption coefficient of the silicon film 32 on the incident side of the photo sensor 35, and the photo sensor 35 can be made highly sensitive and miniaturized. The effect is very noticeable.

[Brief explanation of the drawing]

1A to 1E are cross-sectional views showing the manufacturing process of one embodiment of the method for manufacturing a semiconductor three-dimensional circuit element of the present invention;
FIGS. 2a to 2e are cross-sectional views showing the manufacturing process of a conventional semiconductor three-dimensional circuit element. 19, 31, 32... Single crystal silicon film, 29
...Single crystal spinel film, 30...Through hole,
33... pn junction.

Claims (1)

[Claims] 1. On a semiconductor element formed on a single crystal semiconductor film
A method for manufacturing a semiconductor three-dimensional circuit element in which a semiconductor element having a pn junction is formed includes a step of forming a single crystal insulating film to cover the semiconductor element, and forming a through hole for connecting with a part of the semiconductor element. a step of forming a p-type or n-type first single crystal semiconductor film on the single crystal insulating film and in the through hole; and a step of forming the first single crystal semiconductor film on the single crystal insulating film and in the through hole. A method for manufacturing a semiconductor three-dimensional circuit element, comprising the step of laminating a second n-type or p-type single crystal semiconductor film thereon to form a pn junction.