JPH05198769A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] It is an object of the present invention to provide a method for manufacturing a semiconductor device in which an interlayer insulating film is planarized when there is a large difference in height between a capacitor and another region. [Structure] On a silicon substrate 12, a stack type capacitor 14 composed of a storage electrode 18 and a counter electrode 22 sandwiching a capacitor dielectric film 20 is formed. Then CVD
A SiO ₂ film 24 as an interlayer insulating film is deposited on the entire surface by using the method. At this time, the silicon substrate 1 of the capacitor 14
2 The thickness of the SiO ₂ film 24 is made sufficiently thicker than the height from the surface. Then, using the RIE method, Si at a predetermined position
By selectively etching the O ₂ film 24, the silicon substrate 1
After opening the contact holes 26a and 26b reaching the second surface, the entire surface of the SiO ₂ film 24 is polished by a normal polishing method to flatten the surface of the SiO ₂ film 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of planarizing an interlayer insulating film in a manufacturing process of a semiconductor memory device having a stack type capacitor. A semiconductor memory device represented by a DRAM (Dynamic Randam Access Memory) is widely used in the world. The functions are increasing year by year due to the increase in the degree of integration, the increase in processing speed, and the market is increasing.

[0002]

2. Description of the Related Art A conventional method of flattening an interlayer insulating film in a manufacturing process of a semiconductor memory device will be described with reference to FIG. On the silicon substrate 52, the convex portion 54 made of, for example, a studder type capacitor is formed. Then, PSG containing 8 to 12 wt% of P (phosphorus) on the silicon substrate 52 and the convex portion 54 by the CVD method.
(Phosphorus glass) 56 is formed as an interlayer insulating film. The shape of the PSG 56 surface at this time is shown by a broken line in the figure.

The PSG 56, which is in a glass state, has a significantly low softening point and can flow at a temperature of 1000 ° C. or lower. Therefore, after the PSG 56 is formed, the shape of the surface of the PSG 56 is changed by performing heat treatment at a predetermined temperature.
The PSG is transformed from the broken line in the figure to that shown by the solid line.
56 The surface can be flattened. This method is a method that can easily planarize the interlayer insulating film when the height of the convex portion 54 is relatively small. Note that, as the interlayer insulating film, BSG (boron glass) containing B (boron) may be used instead of PSG 56 to perform planarization by this method.

[0004]

In the future, as the semiconductor memory device becomes finer, it is required to reduce the occupied area of the capacitor. Would require a capacitance of about 30 fF. Stack type fin-shaped capacitors have been proposed to meet the demand to reduce the occupied area of such capacitors and to secure the desired capacitance (Taiji Ema, "64M DRAM Process Technology" Monthly Semiconductor World 1991.7 p. See .146).

In this fin-shaped capacitor, as shown in FIG. 25, a storage electrode 66 having a plurality of conductive layers extending in a fin shape is formed on a semiconductor substrate 62 via a contact hole formed in an insulating film 64. This storage electrode 66
A counter electrode 70 is formed on the capacitor dielectric film 68. Therefore, in such a structure, the height h of the capacitor is inevitably higher than that of other regions on the semiconductor substrate 62.

When further reduction of the capacitor area is required due to the progress of miniaturization, a large capacitance can be secured by increasing the number of fins and multiplexing, but on the other hand, such fin multiplexing is not possible. The height h of the capacitor will be increased more and more. When the height h of the capacitor becomes higher as compared with other regions on the semiconductor substrate due to the miniaturization of the semiconductor memory device, glass having a low melting point such as PSG is deposited as an interlayer insulating film,
In the conventional flattening method for flattening the surface of the interlayer insulating film by heat treatment, it is difficult to secure the flatness necessary for forming the wiring layer on the interlayer insulating film without causing disconnection or the like. There is.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device in which the interlayer insulating film is flattened when the height difference between the capacitor and other regions is large.

[0008]

The inventors of the present invention have proposed a method of flattening an interlayer insulating film by polishing instead of the conventional flattening method when the height difference between the capacitor and other regions becomes extremely large. I thought it would be effective. Then, the following experiment was conducted to examine the effectiveness of this method. That is, the first experiment is for clarifying the problems in the flattening method by polishing, and the second experiment is for solving the revealed problems.

FIGS. 1 and 2 are process diagrams for explaining the flattening method according to the first experiment and graphs showing the experimental results, and FIGS. 3 and 4 are for explaining the flattening method according to the second experiment. 2 is a graph showing the process chart of FIG.
In the first experiment, CVD (Chemical Vapor Depos
ition) method, the film thickness is 1.0 μm on the silicon substrate 2.
Si ₃ N ₄ film (silicon nitride film) is deposited and then patterned to form a convex Si ₃ N ₄ film 4 having a height of 1.0 μm.
a, 4b, 4c were formed. Then, using the CVD method,
SiO ₂ film (silicon oxide film) with a film thickness of 2.0 μm on the entire surface
6 was deposited (see FIG. 1 (a)).

Next, the SiO ₂ film 6 was polished so that the final film thickness was about 1 μm, and the film surface was flattened (see FIG. 1B). Then, in the region where only the SiO ₂ film 6 exists, the SiO ₂ film 6 is selectively etched by the RIE (Reactive Ion Etching) method to aim at 1.1 μm to form holes 8a and 8b (see FIG. See c)). This assumes the formation of contact holes in device fabrication.

In the process of the first experiment described above, FIG.
Before and after polishing shown in (a) and (b), Si ₃
The region where the N ₄ films 4a, 4b, 4c exist, and Si ₃ N ₄
The distances of the respective film surfaces from the silicon substrate surface in the regions where the films 4a, 4b and 4c were not present and only the SiO ₂ film 6 was present were measured. The result is shown in the graph of FIG.

In the regions where the Si ₃ N ₄ films 4a, 4b and 4c exist, the distance from the surface of the silicon substrate 2 before polishing to the film surface was 2.95 to 3.05 μm, whereas after polishing Are distributed in the range of 0.85 to 1.05 μm. Here, there is a value smaller than 1.0 μm,
It is shown that the Si ₃ N ₄ films 4a, 4b and 4c are also polished. This is because the ratio of the polishing rates of the Si ₃ N ₄ films 4a, 4b, 4c and the SiO ₂ film 6 cannot be made large, so that the Si ₃ N ₄ films 4a, 4b, 4c are also slightly scraped. Because.

On the other hand, in the region where only the SiO ₂ film 6 is present, the distance from the surface of the silicon substrate 2 to the film surface before polishing was 1.95 to 2.05 μm, whereas it was 0 after polishing. The variation was 0.55 to 1.05 μm. This shows that when the planarization method by polishing is used for actual device fabrication, the height of the SiO ₂ film after polishing in the region where only the SiO ₂ film exists varies in the plane of the semiconductor substrate. There is. However, even if the height of the SiO ₂ film varies, the height difference at the adjacent points is small and no sharp unevenness occurs. Therefore, the formation of the wiring layer on the SiO ₂ film after polishing is comparatively difficult. You can easily.

Further, the hole 8a shown in FIG. 1 (c),
8b was investigated. S remaining in holes 8a and 8b
When the film thickness of the iO ₂ film 6 is set to a positive value and the etching depth of the silicon substrate 2 is set to a negative value, the graph shown in FIG. 2B is obtained. From the graph of FIG. 2B, SiO
₂ There is no region where the film 6 remains, but it can be seen that there is a region where the silicon substrate 2 is etched to a depth of 0 to 0.25 μm. This indicates that it is difficult to form the contact hole with good controllability when the contact hole is opened in the SiO ₂ film whose thickness is varied by polishing.

Therefore, in the process of manufacturing a semiconductor device having a structure in which the height of the capacitor is increased, the interlayer insulating film is simply flattened by polishing. This is because when the contact hole is opened in the flattened interlayer insulating film. In addition, there arises a problem that the contact hole cannot be formed with good controllability. Next, in a second experiment, a CVD method is used to form a film having a thickness of 1.2 μm and a film thickness of 0.1 μm on the silicon substrate 2.
An uneven Si ₃ N ₄ film 4 having a thickness of 2 μm was formed.
Then, using a CVD method, a 2.0 μm thick Si film is formed on the entire surface.
The O ₂ film 6 was deposited (see FIG. 3A).

Then, a Si ₃ N ₄ film 4 having a thickness of 0.2 μm is formed.
2.1 μm in the region where
The SiO ₂ film 6 and the Si ₃ N ₄ film 4 were selectively etched to form holes 10a and 10b (FIG. 3).
(See (b)). This assumes the formation of contact holes in device fabrication. Next, the SiO ₂ film 6 was polished so that the final film thickness was about 1 μm, and the film surface was flattened (see FIG. 3C).

Then, the Si ₃ N ₄ film 4 remaining in the holes 10a and 10b is removed by hot phosphoric acid (FIG. 3).
(See (d)). At this time, since hot phosphoric acid hardly etches Si, the surface of the silicon substrate 2 is hardly etched. In the above second experiment, the holes 10a and 10b shown in FIG. 3B were examined. Hall 1
0a, 10b remaining Si ₃ N ₄ film 4 and SiO ₂
When the film thickness of the film 6 is set to a positive value and the etching depth of the silicon substrate 2 is set to a negative value, the graph shown in FIG.

From the graph of FIG. 4 (a), the Si ₃ N ₄
It was confirmed that the film 4 remained 0.0 to 0.1 μm and that the silicon substrate 2 was not etched. This means that the contact hole can be formed with good controllability. Thus, the Si ₃ N ₄ film 4 is remaining, Si ₃ N _4/5 film 4 is because the slower etch rate than SiO ₂ film 6, also remain are Si ₃ N
_The reason why the thickness of the ₄ film 4 is almost uniform over the entire surface of the silicon substrate is considered to be because the film thickness of the SiO ₂ film 6 deposited by the CVD method is uniform over the entire surface of the silicon substrate 2.

Further, FIG. 3 (b), the anteroposterior polishing shown (c), the a region the Si ₃ N ₄ film 4 having a film thickness of 0.2μm is present, the thickness of 1.2 [mu] m Si ₃ N ₄ The distance between each film surface and the silicon substrate surface in the region where the film 4 is present was measured. The result is shown in the graph of FIG. In the region where the Si ₃ N ₄ film 4 having a film thickness of 1.2 μm exists, the distance from the surface of the silicon substrate 2 to the film surface before polishing was 3.15 to 3.25 μm, whereas after polishing, , 1.0 to 1.2 μm. Here, SiO ₂ is smaller than 1.2 μm.
Since the ratio of the polishing rate with the film 6 cannot be made large, it is shown that the Si ₃ N ₄ film 4 is also slightly scraped.

On the other hand, Si having a film thickness of 0.2 μm₃N_FourMembrane 4
In the existing region, the surface of the silicon substrate 2 before polishing
The distance from the film surface to the film surface is 2.15 to 2.25 μm.
On the other hand, after polishing, it varies from 0.70 to 1.2 μm.
I was there. This variation is caused by the SiO 2 in FIG.₂Membrane 6 only
Is almost the same as in the region where
It That is, SiO₂In the area where the membrane occupies most
By polishing SiO₂Variation in film height
It is shown that. However, in this case as well,
The height difference was small, and there was no sharp unevenness.
Therefore, after polishing SiO ₂It is relatively easy to form a wiring layer on the film.
Easy to do.

Further, as shown in FIG. 3 (d), Si
After polishing the O ₂ film 6, the Si ₃ N ₄ film 4 remaining in the holes 10a and 10b was removed by hot phosphoric acid, but at this time, the surface of the silicon substrate 2 was hardly etched by the hot phosphoric acid. This means that the contact hole can be formed with good controllability. Therefore, from the above first and second experiments, the following was revealed.

That is, in order to adopt the flattening method by polishing as the flattening method of the interlayer insulating film in the production of the device having the structure in which the height of the capacitor becomes high, the technique of forming the contact hole with good controllability. Development is essential. This problem is that when a stacked type capacitor higher than other regions is provided on the semiconductor substrate, an interlayer insulating film having a thickness larger than the height of the capacitor is formed on the semiconductor substrate and the capacitor, and the interlayer insulating film is formed. This is achieved by selectively etching and forming contact holes, and then polishing the interlayer insulating film to planarize the surface. A polishing level flatness can be obtained and contact holes can be formed with good controllability. it can.

Further, it is desirable to form a protective film between the semiconductor substrate and the interlayer insulating film, and by this protective film,
Further, contact holes can be formed with good controllability, and contamination of the surface of the semiconductor substrate during polishing can be prevented.

[0024]

According to the present invention, in a method of manufacturing a semiconductor device having a stack type capacitor on a semiconductor substrate, an interlayer insulating film is formed on the semiconductor substrate and the capacitor, and then the interlayer insulating film is polished to remove its surface. By selectively etching the interlayer insulating film with a uniform film thickness before planarization to form a contact hole, it is possible to form a contact hole in the uniform interlayer insulating film before the film thickness is varied by polishing. Therefore, the flatness at the polishing level can be obtained, and the contact hole can be formed with good controllability.

Further, by forming a protective film between the semiconductor substrate and the interlayer insulating film, it becomes a stopper during the etching of the interlayer insulating film, so that the contact hole can be formed with higher controllability, or during the polishing. It serves as a protective film on the surface of the semiconductor substrate and can prevent contamination.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on illustrated embodiments. 5 and 6 are process diagrams for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention. A stack type fin capacitor 14 is formed on the silicon substrate 12. That is, a storage electrode 18 having a plurality of conductive layers extending like fins is formed on the silicon substrate 12 in the contact hole opened in the insulating film 16, and the Si ₃ N ₄ film and the SiO ₂ film are formed on the storage electrode 18. The counter electrode 22 is formed through the capacitor dielectric film 20 including the film (see FIG. 5A).

Then, a SiO ₂ film 24 as an interlayer insulating film is deposited on the entire surface by the CVD method. At this time, the SiO ₂ film 24 has a thickness of 2 μm, and the capacitor dielectric film 20 is sandwiched between the storage electrode 18 and the counter electrode 22.
It is made sufficiently thicker than the height of the capacitor 14 made of the above from the surface of the silicon substrate 12 (see FIG. 5B). Then, the SiO ₂ film 24 at a predetermined position is selectively etched by using the RIE method to open contact holes 26a and 26b reaching the surface of the silicon substrate 12 (FIG. 6).
(See (a)).

Next, using a normal polishing method, the entire surface of the SiO ₂ film 24 is polished to flatten the surface of the SiO ₂ film 24 (see FIG. 6B). Thus, according to this embodiment, S
To flatten the iO ₂ film 24 by polishing, SiO ₂
Flatness that facilitates wiring on the film 24 can be realized. In addition, before polishing the SiO ₂ film 24,
_{Since the} contact holes 26a and 26b are opened in the _two films 24, the contact holes 26a and 26b are polished.
Even if the film thickness of the SiO ₂ film 24 near b is slightly varied, it does not adversely affect the formation of the contact holes 26a and 26b. Therefore, Si as an interlayer insulating film
The flatness of the polishing level of the O ₂ film 24 can be realized, and the contact holes 26a and 26b can be formed with good controllability.

Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to the process charts shown in FIGS. The same components as those shown in FIGS. 5 and 6 are designated by the same reference numerals and the description thereof will be omitted. Figure 5
In the same manner as (a), the stack type fin-shaped capacitor 14 is formed on the silicon substrate 12 (see FIG. 7A).

Next, the Si ₃ N ₄ film 28 having a film thickness of 0.20 μm is deposited as a protective film on the entire surface by the CVD method (see FIG. 7B). Then, using the CVD method, S
On the i ₃ N ₄ film 28, a SiO ₂ film 25 as an interlayer insulating film having a film thickness of 1.5 μm is deposited sufficiently thicker than the height of the capacitor 14 from the surface of the silicon substrate 12. However,
When the SiO ₂ film 25 is polished to planarize the surface in a later step, this polishing is performed on the Si ₃ N ₄ film 2 on the capacitor 14.
Therefore, the thickness of the SiO ₂ film 25 may be smaller than that of the SiO ₂ film 24 in the first embodiment (see FIG. 7C).

Next, by using the RIE method, S at a predetermined position
The iO ₂ film 25 is selectively etched to open contact holes 26a and 26b. At this time, Si ₃ N ₄
By using the film 28 as an etching stopper,
This selective etching of the SiO ₂ film 25 can be performed with good controllability. Then, the RIE method or the hot phosphoric acid method is used to expose the Si exposed in the contact holes 26a and 26b.
_{The 3} N ₄ film 28 is removed by etching so that the contact holes 26a and 26b reach the surface of the silicon substrate 12 (see FIG. 8A).

Then, using a normal polishing method, the entire surface of the SiO ₂ film 25 is polished to flatten the surface of the SiO ₂ film 25. At this time, the polishing of the SiO ₂ film 25 is performed by the capacitor 1
4 stops on the Si ₃ N ₄ film 28 (see FIG. 8B).
As described above, according to the present embodiment, since the polishing of the SiO ₂ film 25 is stopped by the Si ₃ N ₄ film 28 on the capacitor 14, the film thickness distribution of the SiO ₂ film 25 as the interlayer insulating film is the same as in the first embodiment. Better than the example. Also the Si ₃ N ₄ film 28 is formed under the SiO ₂ film 25 as an interlayer insulating film, contact holes 26a, SiO ₂ for opening 26b
By using it as an etching stopper during the selective etching of the film 25, the controllability of the etching of the SiO ₂ film 25 is improved, so that the contact holes 26a and 26b are formed with better controllability than in the first embodiment. be able to.

Next, a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to the process charts shown in FIGS. The same components as those shown in FIGS. 7 and 8 are designated by the same reference numerals and the description thereof will be omitted. Figure 7
After the stack type fin-shaped capacitor 14 is formed on the silicon substrate 12 in the same manner as in (a) to (c), CV is performed.
By the D method, a Si ₃ N ₄ film 28 as a protective film and a SiO ₂ film 25 as an interlayer insulating film are formed on the entire surface of the capacitor 1
No. 4 is thicker than the height from the surface of the silicon substrate 12 (see FIG. 9A).

Then, the Si ₃ N ₄ film 2 is formed by the RIE method.
8 as an etching stopper, and S at a predetermined position
The iO ₂ film 25 is selectively etched to open contact holes 26a and 26b (see FIG. 9B). Then, with the Si ₃ N ₄ film 28 left in the contact holes 26a and 26b, SiO _{2 is formed} by a normal polishing method.
The entire surface of the film 25 is polished to flatten the surface of the SiO ₂ film 25 (see FIG. 10A).

Then, the hot phosphoric acid method is used to etch away the Si ₃ N ₄ film 28 remaining in the contact holes 26a and 26b so that the contact holes 26a and 26b reach the surface of the silicon substrate 12 (see FIG. 10
(See (b)). Thus, according to this embodiment, the second
It is possible to obtain the same effect as that of the above-mentioned embodiment, and since the SiO ₂ film 25 is polished while leaving the Si ₃ N ₄ film 28 in the contact holes 26a and 26b, Si ₃
The N ₄ film 28 serves as a protective film on the surface of the silicon substrate 12,
It is possible to prevent the surface of the silicon substrate 12 from being contaminated during polishing.

Next, a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention will be described with reference to the process charts shown in FIGS. The same components as those shown in FIGS. 5 and 6 are designated by the same reference numerals and the description thereof will be omitted. In the same manner as in FIGS. 5A to 6A, the silicon substrate 12
After the stack-type fin-shaped capacitor 14 is formed thereon, the SiO ₂ film 2 as an interlayer insulating film is formed by the CVD method.
4 is deposited sufficiently thicker than the height of the capacitor 14, and the SiO ₂ film 24 is selectively etched by the RIE method to open the contact holes 26a and 26b (see FIG. 11A).

Then, a Si ₃ N ₄ film 30 as a protective film having a film thickness of 0.01 μm is deposited on the entire surface by the CVD method (see FIG. 11B). Then, the entire surface of the SiO ₂ film 24 is polished by a normal polishing method to flatten the surface of the SiO ₂ film 24. At this time, the contact hole 26
The surface of the silicon substrate 12 in a and 26b is covered with the Si ₃ N ₄ film 30 (see FIG. 12A).

Then, the hot phosphoric acid method is used to etch the Si ₃ N ₄ film 30 in the contact holes 26a and 26b so that the contact holes 26a and 26b reach the surface of the silicon substrate 12 (FIG. 12B). )reference). As described above, according to this embodiment, the same effects as those of the first embodiment can be obtained, and the contact hole 2
6a, for polishing a SiO ₂ film 24 in a state where the silicon substrate 12 surface in 26b is covered with the Si ₃ N ₄ film 30, so the Si ₃ N ₄ film 30 and the protective film of the silicon substrate 12 surface, polished In this case, the surface of the silicon substrate 12 can be prevented from being contaminated.

Next, a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention will be described with reference to the process charts shown in FIGS. The same components as those shown in FIGS. 7 and 8 are designated by the same reference numerals and the description thereof will be omitted. In the same manner as in FIGS. 7A to 8A, the silicon substrate 12
After the stack type fin-shaped capacitor 14 is formed on the upper surface, a Si ₃ N film as a protective film is formed on the entire surface by the CVD method.
_{The 4} film 28 and the SiO ₂ film 25 as an interlayer insulating film are deposited sufficiently thicker than the height of the capacitor 14 from the surface of the silicon substrate 12, and the SiO ₂ film 25 and the Si ₃ N ₄ film 28 are etched step by step. Then, the contact holes 26a and 26b are opened (see FIG. 13A).

Then, a Si ₃ N ₄ film 30 as a protective film having a film thickness of 0.01 μm is deposited on the entire surface by the CVD method (see FIG. 13B). Then, the surface of the silicon substrate 12 in the contact holes 26a and 26b is covered with Si ₃ N ₄
With the film 30 covered, the S
iO ₂ film 25 by polishing the entire surface to flatten the SiO ₂ film 25 surface (see FIG. 14 (a)).

Next, the hot phosphoric acid method is used to etch away the Si ₃ N ₄ film 30 in the contact holes 26a and 26b so that the contact holes 26a and 26b reach the surface of the silicon substrate 12 (see FIG. See b)). As described above, according to this embodiment, the effects of the second embodiment and the effects of the fourth embodiment can be combined.

Next, a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention will be described with reference to the process diagrams shown in FIGS. The same components as those shown in FIGS. 5 and 6 are designated by the same reference numerals and the description thereof will be omitted. In the same manner as in FIGS. 5A to 6A, the silicon substrate 12
After the stack-type fin-shaped capacitor 14 is formed thereon, the SiO ₂ film 2 as an interlayer insulating film is formed by the CVD method.
4 is deposited sufficiently thicker than the height of the capacitor 14, and the SiO ₂ film 24 is selectively etched by RIE to open contact holes 26a and 26b (see FIG. 15A).

Next, a conductive material containing, for example, Cu (copper) is deposited on the entire surface, and the contact holes 26a and 26b are filled with this conductive material. Then, the contact hole 26 is formed by using, for example, the lithography technique.
The conductive material on the SiO ₂ film 24 is selectively removed except for the peripheral portions of the contact holes 26a and 26b.
Embedded electrodes 32a, 3 connected to the silicon substrate 12 inside
2b are respectively formed (see FIG. 15B).

Incidentally, here, the buried electrodes 32a, 32
A conductive material containing Cu was used as the material of b.
Without limitation, for example, Al (aluminum), W
(Tungsten), Ti (Titanium), Au (Gold), Ag
Any conductive material such as (silver) may be used. Also, SiO
₂The selective removal of the conductive material deposited on the film 24 must always be performed.
You don't have to. In any case, Si
O₂The conductive material on the film 24 has contact holes 26a,
SiO which is performed in a later step except for the inside of 26b. ₂Membrane 24
This is because it is removed during polishing.

Then, the SiO ₂ film 2 is formed by a normal polishing method.
4 The entire surface is polished to flatten the surface of the SiO ₂ film 24.
At this time, the upper portions of the buried electrodes 32a and 32b in the contact holes 26a and 26b are also polished at the same time, and the upper surfaces thereof are exposed on the surface of the SiO ₂ film 24 (see FIG. 16). As described above, according to this embodiment, the same effect as that of the first embodiment can be obtained, and the SiO ₂ film 24 is polished after the buried electrodes 32a and 32b are formed in the contact holes 26a and 26b. As a result, the surface of the silicon substrate 12 is not exposed during polishing, so that the surface of the silicon substrate 12 can be prevented from being contaminated. At the same time that the SiO ₂ film 24 is flattened by polishing, the bottom surface is connected to the silicon substrate 12 and the top surface is SiO ₂ film.
Since the buried electrodes 32a and 32b exposed on the surface of the film 24 are formed, a flattened SiO ₂ film formed in a later step is formed.
Wiring on the film 24 becomes extremely easy.

Next, a method of manufacturing a semiconductor device according to a seventh embodiment of the present invention will be described with reference to the process charts shown in FIGS. The same components as those shown in FIGS. 7 and 8 are designated by the same reference numerals and the description thereof will be omitted. In the same manner as in FIGS. 7A to 8A, the silicon substrate 12
After the stack type fin-shaped capacitor 14 is formed on the upper surface, a Si ₃ N film as a protective film is formed on the entire surface by the CVD method.
_{The 4} film 28 and the SiO ₂ film 25 as an interlayer insulating film are deposited sufficiently thicker than the height of the capacitor 14 from the surface of the silicon substrate 12, and the SiO ₂ film 25 and the Si ₃ N ₄ film 28 are etched step by step. Then, the contact holes 26a and 26b are opened (see FIG. 17A).

Next, a conductive material containing, for example, Cu is deposited on the entire surface, and the contact hole 2 is formed by this conductive material.
After filling 6a and 26b, the contact hole 26
The conductive material on the SiO ₂ film 25 is selectively removed except for the peripheral portions of the contact holes 26a, 26b.
embedded electrodes 32a connected to the silicon substrate 12 in b,
32b are formed respectively (see FIG. 17B).

Then, the SiO ₂ film 2 is formed by a normal polishing method.
5 The entire surface is polished to flatten the surface of the SiO ₂ film 25, and the upper portions of the embedded electrodes 32a and 32b in the contact holes 26a and 26b are also polished at the same time. At this time, the Si ₃ N ₄ film 28 formed on the capacitor 14 functions as a polishing stopper, and the polishing is completed when the surface of the SiO ₂ film 25 becomes almost equal to the height of the capacitor 14 (FIG. 18). reference).

As described above, according to this embodiment, the effects of the second embodiment and the effects of the sixth embodiment can be combined. Next, a method of manufacturing a semiconductor device according to an eighth embodiment of the present invention will be described with reference to the process charts shown in FIGS. The same components as those shown in FIGS. 5 and 6 are designated by the same reference numerals and the description thereof will be omitted.

This embodiment is applied when a larger capacitance is required for the stack type fin capacitor.
That is, as the number of fins is increased in order to increase the capacity, the height of the capacitor becomes higher, and when an interlayer insulating film having a film thickness thicker than this height is deposited, the opening of the contact hole by the RIE method becomes It will be difficult. Even if the contact hole is opened, if a metal wiring layer connected to the semiconductor substrate is formed through such a deep contact hole, disconnection due to step breakage or the like is likely to occur. Therefore, the interlayer insulating film is flattened and the contact holes are opened by the following method.

In the same manner as in FIG. 5A, the silicon substrate 1
A stack-type fin-shaped capacitor 34 is formed on the surface 2. However, the height of the capacitor 34 including the storage electrode 38 and the counter electrode 40 with the capacitor dielectric film 36 sandwiched therebetween from the surface of the silicon substrate 12 is shown in FIG. The height is higher than the height of the capacitor 14 (see FIG. 19A).

Next, a SiO ₂ film 42a as an interlayer insulating film having a film thickness of 1.2 μm is deposited on the entire surface by the CVD method (see FIG. 19B). Next, the RIE method is used to selectively etch the SiO ₂ film 42a at a predetermined position to open a contact hole reaching the surface of the silicon substrate 12. Then, a conductive material containing, for example, Cu is deposited on the entire surface, and the inside of the contact hole is filled with this conductive material.
The conductive material on the iO ₂ film 42a is selectively removed to form buried electrodes 44a and 44b connected to the silicon substrate 12 in the contact holes (see FIG. 20A).

Then, again using the CVD method, a layer is formed on the entire surface.
SiO as an insulating film₂The film 42b is deposited. to this
From the silicon substrate 12 and the capacitor 34,
iO ₂S as an interlayer insulating film composed of the films 42a and 42b
iO₂Membrane 42 has embedded electrodes 44a, 44b therein.
It will be formed by embedding. And again, this S
iO₂The film thickness of the film 42 is more than the height of the capacitor 34
To be thicker (see FIG. 20 (b)).

Then, the embedded electrode 44 is formed by the RIE method.
The SiO ₂ film 42b on a and 44b is selectively etched to open contact holes 46a and 46b reaching the upper surfaces of the embedded electrodes 44a and 44b (see FIG. 21A). Then, the entire surface of the SiO ₂ film 42 is polished by a normal polishing method to flatten the surface of the SiO ₂ film 42 (FIG. 21).
(See (b)).

As described above, according to this embodiment, since the contact holes 46a and 46b are opened before polishing the SiO ₂ film 42, the same effect as that of the first embodiment can be obtained. At the same time, the following effects can be achieved. That is, in order to increase the capacity, the capacitor 3
4 is extremely high, Si as an interlayer insulating film
O ₂ film 42 is formed in two steps with the SiO ₂ film 42a and SiO ₂ film 42b, for opening respective separate contact hole in the SiO ₂ film 42a and SiO ₂ film 42b, the SiO ₂ film as a whole Even if the film thickness of 42 is very large, the contact hole can be easily formed with good controllability.

Further, when the SiO ₂ film 42 is polished, the surface of the silicon substrate 12 in the contact hole is covered with the embedded electrodes 44a and 44b, so that the surface of the silicon substrate 12 can be prevented from being contaminated. .. Furthermore, 1
Since the buried electrodes 44a and 44b are formed in the contact holes opened in the SiO ₂ film 42a for the second time, the contact holes 46a, 46b opened in the _second SiO ₂ film 42b on the buried electrodes 44a, 44b are formed. Since the depth does not become so deep, the embedded electrodes 44a, 44
It is possible to prevent the occurrence of disconnection due to step breakage or the like when forming the metal wiring layer connected to the silicon substrate 12 via b.

Next, a method of manufacturing a semiconductor device according to a ninth embodiment of the present invention will be described with reference to the process charts shown in FIGS. The same components as those shown in FIGS. 19 to 21 are designated by the same reference numerals and the description thereof will be omitted. Like the eighth embodiment, this embodiment is also effective when the height of the stack type fin capacitor is extremely high.

Similar to FIG. 19A, a stack type fin-shaped capacitor 34 is formed on the silicon substrate 12 (see FIG. 22A). Then, using the CVD method,
The entire surface is covered with Si ₃ N ₄ as a protective film with a thickness of 0.20 μm.
A film 48 is deposited (see FIG. 22 (b)). Then Si
An O ₂ film 42a is deposited, and this SiO ₂ film 42a and Si
After the contact holes are opened at predetermined positions by etching the ₃ N ₄ film 28 in stages, the buried electrode 4 connected to the silicon substrate 12 is provided in the contact holes.
4a and 44b are embedded, and the SiO ₂ film 42b is further formed on the entire surface.
By depositing, SiO ₂ film 42a, a SiO ₂ film 42 as an interlayer insulating film consisting 42b formed to be sufficiently thicker than the height of the capacitor 34 (see FIG. 23 (a)).

21 (a) to 21 (b), contact holes 46a and 46b reaching the upper surfaces of the embedded electrodes 44a and 44b are opened in the SiO ₂ film 42b, and then the entire surface of the SiO ₂ film 42 is opened. Polished and SiO ₂ film 4
2 The surface is flattened (see FIG. 23 (b)). As described above, according to the present embodiment, the effect of the second embodiment and the sixth embodiment can be obtained.
The effects of the above embodiment can be combined.

[0060]

As described above, according to the present invention, in a method of manufacturing a semiconductor device in which a stack type capacitor formed on a semiconductor substrate is higher than other regions, a stack type capacitor is formed on the semiconductor substrate and the capacitor. An interlayer insulating film is formed, the interlayer insulating film is selectively etched to form a contact hole, and then the interlayer insulating film is polished to planarize its surface, thereby obtaining a polishing level flatness. The contact hole can be formed with good controllability.

Further, by forming the protective film between the semiconductor substrate and the interlayer insulating film, the contact hole can be formed with higher controllability, and the surface of the semiconductor substrate can be prevented from being contaminated during polishing. Further, after forming the embedded electrode in the contact hole, the interlayer insulating film is polished to planarize the surface thereof, and the embedded electrode is exposed on the surface of the interlayer insulating film, so that the surface of the semiconductor substrate during polishing can be improved. Contamination can be prevented and wiring on the planarized interlayer insulating film can be extremely facilitated.

[Brief description of drawings]

FIG. 1 is a process drawing for explaining a first experiment for clarifying a problem of a flattening method by polishing.

FIG. 2 is a graph showing the results of the first experiment shown in FIG.

FIG. 3 is a process drawing for explaining a second experiment for solving the problem of the flattening method by polishing.

FIG. 4 is a graph showing the results of the second experiment shown in FIG.

FIG. 5 is a process chart (1) for explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a process diagram (No. 2) for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a process diagram (1) for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a process diagram (No. 2) for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a process diagram (1) for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 10 is a process diagram (No. 2) for explaining the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a process chart (1) for explaining the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 12 is a process diagram (No. 2) for explaining the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 13 is a process diagram (1) for explaining the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.

FIG. 14 is a process diagram (No. 2) for explaining the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 15 is a process drawing (1) for explaining the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention.

FIG. 16 is a process diagram (No. 2) for explaining the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention.

FIG. 17 is a process diagram (1) for explaining the method for manufacturing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 18 is a process diagram (No. 2) for explaining the method for manufacturing the semiconductor device according to the seventh embodiment of the present invention.

FIG. 19 is a process diagram (1) for explaining the method for manufacturing a semiconductor device according to the eighth embodiment of the present invention.

FIG. 20 is a process diagram (No. 2) for explaining the method for manufacturing the semiconductor device according to the eighth embodiment of the present invention.

FIG. 21 is a process drawing (3) for explaining the method for manufacturing a semiconductor device according to the eighth embodiment of the present invention.

FIG. 22 is a process chart (1) for explaining the method for manufacturing a semiconductor device according to the ninth embodiment of the present invention.

FIG. 23 is a process diagram (No. 2) for explaining the method for manufacturing the semiconductor device according to the ninth embodiment of the present invention.

FIG. 24 is a diagram for explaining a conventional flattening method.

FIG. 25 is a cross-sectional view showing a semiconductor memory device having a stack type fin capacitor.

[Explanation of symbols]

2 ... silicon substrate 4a, 4b, 4c, 4 ... Si 3 N 4 film 6 ... SiO ₂ film 8a, 8b, 10a, 10b ... hole 12 ... silicon substrate 14 ... stacked type fin-shaped capacitor 16 ... insulating film 18 ... storage Electrode 20 ... Capacitor dielectric film 22 ... Counter electrode 24, 25 ... SiO ₂ film 26a, 26b ... Contact hole 28, 30 ... Si ₃ N ₄ film 32a, 32b ... Buried electrode 34 ... Stack type fin capacitor 36 ... Capacitor dielectric Film 38 ... Storage electrode 40 ... Counter electrode 42a, 42b, 42 ... SiO ₂ film 44a, 44b ... Buried electrode 46a, 46b ... Contact hole 48 ... Si ₃ N ₄ film 52 ... Silicon substrate 54 ... Convex portion 56 ... PSG 62 ... Semiconductor substrate 64 ... Insulating film 66 ... Storage electrode 68 ... Capacitor dielectric film 70 ... Counter electrode

Claims (10)

[Claims] 1. A step of forming a stack type capacitor in a first region on a semiconductor substrate, a step of forming an interlayer insulating film having a thickness larger than the height of the capacitor on almost the entire surface, Selectively etching the insulating film to form a contact hole in the second region on the semiconductor substrate and exposing the semiconductor substrate in the contact hole; polishing the interlayer insulating film; And a step of flattening the surface of the interlayer insulating film. 2. A step of forming a stack type capacitor in a first region on a semiconductor substrate, a step of forming a protective film on substantially the entire surface, and a step of forming a protective film on the protective film with a thickness greater than the height of the capacitor. A step of forming an interlayer insulating film having a film thickness, and the interlayer insulating film is selectively etched by using the protective film as a stopper to form a contact hole in a second region on the semiconductor substrate, and then exposed. A semiconductor device comprising: a step of removing the protective film by etching to expose the semiconductor substrate in the contact hole; and a step of polishing the interlayer insulating film to flatten the surface of the interlayer insulating film. Manufacturing method. 3. A step of forming a stack type capacitor in a first region on a semiconductor substrate, a step of forming a protective film on substantially the entire surface, and a step of forming a protective film on the protective film with a thickness greater than the height of the capacitor. A step of forming an interlayer insulating film having a thickness; a step of selectively etching the interlayer insulating film using the protective film as a stopper to form a contact hole in a second region on the semiconductor substrate; A step of polishing an insulating film to flatten the surface of the interlayer insulating film; and a step of etching and removing the protective film in the contact hole to expose the semiconductor substrate in the contact hole. A method of manufacturing a semiconductor device, which is characterized. 4. A step of forming a stack type capacitor in a first region on a semiconductor substrate, a step of forming an interlayer insulating film having a film thickness thicker than the height of the capacitor on almost the entire surface, A step of selectively etching the insulating film to form a contact hole in a second region on the semiconductor substrate and exposing the semiconductor substrate in the contact hole; and the semiconductor substrate exposed in the contact hole A step of forming a protective film thereon, a step of polishing the interlayer insulating film to flatten the surface of the interlayer insulating film, and an etching removal of the protective film in the contact hole to remove the protective film in the contact hole. And a step of exposing the semiconductor substrate, the method for manufacturing a semiconductor device. 5. A step of forming a stack type capacitor in a first region on a semiconductor substrate, a step of forming a first protective film on substantially the entire surface, and a step of forming a first protective film on the first protective film. Forming an interlayer insulating film thicker than the height of the capacitor; selectively etching the interlayer insulating film using the first protective film as a stopper to contact a second region on the semiconductor substrate. After the hole is formed, the exposed first protective film is removed by etching to expose the semiconductor substrate in the contact hole, and a second protective film is formed on the semiconductor substrate exposed in the contact hole. A step of forming a film; a step of polishing the interlayer insulating film to flatten the surface of the interlayer insulating film; and a step of etching away the second protective film in the contact hole to remove the contact. And a step of exposing the semiconductor substrate in the hole. 6. A step of forming a stack type capacitor in a first region on a semiconductor substrate, a step of forming an interlayer insulating film having a film thickness thicker than the height of the capacitor on almost the entire surface, Selectively etching the insulating film to form a contact hole in the second region on the semiconductor substrate and exposing the semiconductor substrate in the contact hole; and filling a conductive material in the contact hole, Forming a buried electrode connected to the semiconductor substrate; polishing the interlayer insulating film to planarize the surface of the interlayer insulating film, and exposing the buried electrode in the contact hole to the surface of the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: 7. A step of forming a stack type capacitor in a first region on a semiconductor substrate, a step of forming a protective film on almost the entire surface, and a step of forming a protective film on the protective film with a thickness greater than the height of the capacitor. A step of forming an interlayer insulating film having a film thickness, and the interlayer insulating film is selectively etched by using the protective film as a stopper to form a contact hole in a second region on the semiconductor substrate, and then exposed. A step of etching away the protective film to expose the semiconductor substrate in the contact hole; a step of burying a conductive material in the contact hole to form a buried electrode connected to the semiconductor substrate; Polishing to planarize the surface of the interlayer insulating film and expose the embedded electrode in the contact hole to the surface of the interlayer insulating film. The method of manufacturing a semiconductor device according to claim. 8. A step of forming a stack type capacitor in a first region on a semiconductor substrate, a step of forming a first interlayer insulating film over substantially the entire surface, and selecting the first interlayer insulating film. Etching to form a first contact hole in a second region on the semiconductor substrate and expose the semiconductor substrate in the contact hole, and a conductive material is provided in the first contact hole. embedded,
A step of forming a buried electrode connected to the semiconductor substrate, a step of forming a second interlayer insulating film on substantially the entire surface, and a step of selectively etching the second interlayer insulating film on the buried electrode, Forming a second contact hole and exposing the buried electrode; and polishing the second and first interlayer insulating films to planarize the surfaces of the second and first interlayer insulating films. A method of manufacturing a semiconductor device, comprising: 9. A step of forming a stack type capacitor in a first region on a semiconductor substrate, a step of forming a protective film on substantially the entire surface, and a step of forming a first interlayer insulating film on the protective film. And a step of forming the interlayer insulating film selectively using the protective film as a stopper to form a first region in the second region on the semiconductor substrate.
Forming a contact hole, and exposing the exposed protective film by etching to expose the semiconductor substrate in the first contact hole; and embedding a conductive material in the first contact hole.
A step of forming a buried electrode connected to the semiconductor substrate, a step of forming a second interlayer insulating film on substantially the entire surface, and a step of selectively etching the second interlayer insulating film on the buried electrode, Forming a second contact hole and exposing the buried electrode; and polishing the second and first interlayer insulating films to planarize the surfaces of the second and first interlayer insulating films. A method of manufacturing a semiconductor device, comprising: 10. The method for manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film, the first interlayer insulating film, or the second interlayer insulating film.
The interlayer insulating film is made of a silicon oxide film, the protective film, the first protective film, or the second protective film is made of a silicon nitride film, and the buried electrode is made of Al, Cu, W, or Ti. , Au, Ag
A method for manufacturing a semiconductor device, comprising a substance containing any of the above.