JPH0519799A - Voice synthesizing circuit - Google Patents

Abstract

PURPOSE:To reproduce a faithful waveform and improve sound quality by expanding the lower limit (or upper limit) of the dynamic range of the amplitude level of voice synthesis. CONSTITUTION:If the lower limit (or upper limit) of the dynamic range is exceeded in a process wherein difference value data is accumulated by an adder 11 for decoding, underflow (overflow) information as internal arithmetic information is outputted to the outside from an UDF flag 19 (OVF flag 20) and then a subtracting (adding) circuit which is provided outside expands the dynamic range of the voice output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speech synthesizing circuit using a differential coding system which is a kind of waveform coding system, and in particular, a simple external circuit allows a wide dynamic range of waveform amplitude to be obtained and a high quality speech system. A speech synthesis integrated circuit capable of outputting

[0002]

2. Description of the Related Art First, two typical DPs of a differential encoding method used in a conventional speech synthesis integrated circuit.
CM (Differential Pulse Cod)
e Modulation) method and ADPCM (A
daptive Differential Pulses
The e Code Modulation method and the dynamic range of the waveform amplitude will be described.

FIGS. 6A to 6C are waveform diagrams of 3-bit, 4-bit and 5-bit PCM signals. When a voice signal is handled by a digital code, first, as shown in FIG. 6A, sampling is performed at a certain cycle T, each sampled value is quantized, and a code corresponding to the quantized value is replaced. PCM (Pulse Code Mo
The output value of the A / D converter is a PCM code. The shaded portion in FIG. 6 is an error due to quantization, which is called a quantization error.
In this encoding method, if an attempt is made to encode an analog signal with less quantization error, the encoding method shown in FIG.
As shown in (c), the number of bits is as large as 4 bits and 5 bits, and the amount of information increases.

The DPCM method was conceived as an improvement of the sound quality and a reduction of the amount of information in the PCM method, which utilizes the correlation of the audio signals and makes a difference from the previous audio signal as shown in FIG. 7 (a). The value is PCM-encoded. That is, if the number of bits is the same, better quality voice can be synthesized by assigning to the difference value, and conversely, if the sound quality is similar, the DPCM code bit can be reduced and voice data information can be obtained. It can also be compressed.

In this DPCM system, since it is PCM with respect to the difference value, the quantization width for quantization is constant, and in the case of an abrupt audio signal amplitude change or an excessively slow audio signal. Appears as distortion and noise (these are called overload distortion and granular noise).

Further, the ADPCM system is a system in which the concept of adaptive coding is introduced to DPCM to code a voice signal with higher efficiency.

This ADPCM method is a method of determining the quantization width Δ _i of the difference signal value from the previous sample value. That is, assuming that the quantization width of the previous sample is Δ _i−1 , the next sample quantization width Δ _i is determined by k · Δ _i−1 . The value of this quantized coefficient k is defined as a function of the amplitude value of the previous sample.

For example, the following Table 1 shows how to give the quantization count k when performing quantization with 3 bits.

[0009]

[Table 1]

When quantizing with 3 bits, the most significant one digit is assigned as a sign bit, and the remaining 2 bits indicate the absolute value of the amplitude. Then, in the 2-bit amplitude value, when encoded into a code having an amplitude value equal to or larger than the half value of the value indicated by the arrow in the table, k of k is set so as to increase the quantization width of the next sample. Make the value greater than 1. On the other hand, when the amplitude value is smaller than the amplitude value corresponding to the half value, k is set to 1 in order to reduce the amplitude value from the previous quantization width.
Make it smaller. However, in ADPCM, it is necessary to determine the maximum and minimum values of the quantization width so that the quantization width does not become unnecessarily small and vice versa.

Basically, the quantization result by the adapted quantization width Δ is set so that the absolute value is always in the vicinity of the center of the permissible level, and the overload distortion state (the state near the upper limit of the permissible level). ) And granular noise (a state near the lower limit of the allowable level). FIG. 7B shows a state in which Δ is changed and encoded. Table 2 shows the commonly used quantized coefficients for 2 to 5 bits.

[0012]

[Table 2]

The above is a description of speech coding. However, in speech synthesis, it is realized by decoding by the reverse operation of the above-described coding, and the quantization coefficient is the same as the value used for coding. Decrypt by using the value.

Next, the dynamic range of the waveform amplitude will be described. Data RO that stores difference value data
The difference value of M must be within the dynamic range of the waveform amplitude, as shown in FIG.

If a waveform that does not fall within the lower limit of the dynamic range of the waveform amplitude is analyzed and stored, generally speech is synthesized as a waveform as shown in FIG. 8 (b). In addition, since the harmonic components in FIG. 8 (b) are considerably high, as a modification thereof, as shown in FIG. 8 (c), the maximum amplitude level is fixed only when the lower limit of the dynamic range is exceeded. Some have. When the upper limit of the dynamic range of the waveform amplitude is exceeded, the waveforms shown in (d) to (f) of FIG.
It becomes a waveform like.

A conventional example of the voice synthesis integrated circuit of the DPCM system will be described with reference to the block diagram of FIG. This circuit includes an adder 11 used for DPCM decoding.
a, an accumulator 12 that accumulates the added output, and a D / A that converts the digital signal of the cumulative calculation force into an analog signal.
The converter 13, the working register 14 for temporarily storing the cumulative calculation force, and the difference value register 15 for temporarily storing the difference value
And a data ROM 16 storing difference value data,
A memory address register 17 indicating the data address of the data ROM 16 and the memory address register 1
And an incrementer 18 for incrementing the value of 7.

The difference data at the address of the data ROM 16 constituted by a read-only memory or the like pointed to by the memory address register 17 is read and this difference data is temporarily stored in the difference value register 15. The stored difference value data is added to the previous decoded value stored in the work register 14 using the adder 11a. The addition result is transferred to the work register 14 and the D / A converter 13 as a new decoded value, and is converted from the digital decoded signal to the analog decoded signal by the D / A converter 13 and output. Further, the memory address register 17 is incremented by the incrementer 18, the next address data is set, and this operation is sequentially repeated to perform voice synthesis.

Next, the operation of the conventional speech synthesis integrated circuit using the ADPCM code will be described with reference to the block diagram of FIG. This circuit includes an adder / subtractor 51a used for ADPCM decoding processing, an accumulator 12 that accumulates the added / subtracted output, and a D / A converter 13 that converts a digital signal of the cumulative calculation power into an analog signal. , A work register 52 for temporarily storing an adjustable output, a code register 53 for temporarily storing an ADPCM code, a data ROM 16 for storing ADPCM, a memory address register 17 for indicating a data address of the data ROM 16, and a memory address An incrementer 18 that increments the value of the register 17, a quantized coefficient selector 54 that selects a quantized coefficient based on the value of the code register 53, a quantized coefficient table 55 that stores the quantized coefficient, Quantization coefficient register 56 for temporarily storing the quantized count, the quantized coefficient and the amount used in the previous decoding process. A multiplier 57 for multiplying process between the step size and the quantization coefficients, the work register 58 for temporarily storing the multiplication output consists multiplication register 59. for storing the multiplication result.

The ADPCM code data at the address of the data ROM 16 constituted by a read-only memory or the like designated by the memory address register 17 is read, and the ADPCM code data is temporarily stored in the code register 53. Stored A
The negative sign portion (S) of the DPCM code is sent to the adder / subtractor 51a as a control signal for addition / subtraction switching control corresponding to the determination of whether the amplitude level is positive or negative.

Amplitude information other than the negative sign part (S) of ADPCM is sent as a selection control signal of the quantization coefficient selector 54, and the quantization coefficient selector 54 uses the signal sent from the code register 53 as a basis. Then, the corresponding quantized coefficient is selected from the quantized coefficient table 55. The selected quantized coefficient is stored in the quantized coefficient register 56.

Since the quantization width used in the previous decoding process is already stored in the working register 58, the multiplier 57 is used to multiply the contents of the quantization coefficient register 56 and the working register 58, and a new value is obtained. Quantization width multiplication register 59
To store.

AD is performed using the adder / subtractor 51a, accumulator 12 and work register 52 with the value of the multiplication register 59 as a reference.
Accumulation and decoding are performed by repeating addition / subtraction for the number of times based on the data of the PCM code. The decoded digital signal is converted into an analog decoded signal by the D / A converter 13 and output. Further, the memory address register 17 is incremented by the incrementer 18, the next address data is set, and this operation is sequentially repeated to perform voice synthesis.

[0023]

As described above, the speech synthesis integrated circuit using the conventional differential encoding method is always within the dynamic range of the waveform amplitude level of the speech synthesis integrated circuit when the differential code is decoded. Since the difference code was used to analyze so that it would fit, even if the amplitude level of the waveform to be speech-synthesized was small at most of the time, if there was a high level at a certain point, that value would cause the dynamic range of the entire amplitude level to change. It was not decided, and the power component of the voice was small as a whole, and it was difficult to achieve good voice synthesis.

An object of the present invention is to solve the above problem and to provide a speech synthesis circuit which can perform faithful waveform decoding and obtain good sound quality.

[0025]

According to the present invention, a storage means for storing a differential code, a reading means for reading out the differential code from the storage means, and a composite audio signal from the read differential code are combined. In a voice synthesizing circuit including an adding / subtracting means and an output means for converting an output of the adding / subtracting means into an analog signal and outputting a synthesized waveform, a dynamic of a waveform amplitude level in an operation of decoding the differential code from an output of the adding / subtracting means Computation information output means for outputting an over output indicating that the lower limit or upper limit of the range has been exceeded,
It is characterized in that an analog signal adding means for adding the over output of the calculation information output means and the output of the output means is added.

[0026]

1 (a) and 1 (b) are a block diagram of an embodiment of the present invention and a circuit diagram of its external circuit.
2 shows a circuit for expanding the dynamic range of a waveform amplitude level in a speech synthesis integrated circuit by the M coding method. 2 (a) and 2 (b) show an original waveform diagram before encoding and a waveform diagram after decoding according to the present embodiment.

This embodiment is a circuit in which a UDF flag 19 is added to the conventional example shown in FIG. That is, D
Adder 11 used for PCM decoding and accumulator 12
And a D / A that converts a digital signal to an analog signal
The converter 13, the work register 14, the difference value register 15 for temporarily storing the difference value, the data ROM 16 storing the difference value, the memory address register 17 indicating the data address of the data ROM 16, and the memory address register Incrementer 1 for incrementing 17
8 and a UDF flag 19 which holds information on a state where the adder 11 underflows during calculation.

FIG. 1 (b) is a circuit diagram of the external circuit of FIG. 1 (a). The voice integrated circuit 21 of FIG. 1 (a) has a resistor R1.
˜R4 and an operational amplifier A1 are added. If only the subtraction is considered, the resistors R1 to R4 need only have the same resistance value. To realize the gain at the same time as the subtraction operation, the resistors R1 and R3 have the same value, and the resistance R2 is further set. , R4 are made equal and the values of these two are made different, the gain can be obtained at the same time.

First, a normal speech synthesis (DPCM decoding) without expanding the dynamic range of the waveform amplitude level will be described. The difference data at the address of the data ROM 16 designated by the memory address register 17 is read, and this difference data is temporarily stored in the difference value register 15. The adder 11 adds the stored difference value data and the previous decoded value stored in the work register 14. The addition result is added to the work register 14 and the D / A as a new decoded value.
The data is transferred to the converter 13, converted into an analog signal by the D / A converter 13, and output.

During normal speech synthesis, the adder 11
Since it is assumed that the calculation result of (1) always falls within the dynamic range of the waveform amplitude, underflow does not occur and the UDF flag 19 always holds the logical value "0" (value of GND potential). is doing. That is, G
The subtraction output of the ND potential and the AVO potential is realized by the external circuit of FIG.

Next, the expansion of the dynamic range of the waveform amplitude level of this embodiment will be described. Here, in FIG.
As shown in (a), a waveform whose waveform amplitude level does not fall within the lower limit of the dynamic range is stored in the data ROM.
16 is written. When the waveform amplitude level is within the dynamic range, the operation is the same as when the waveform amplitude level dynamic range is not adjusted. However, if it is decoded outside the dynamic range of the waveform amplitude level (that is, if the difference data is forced to be added), the output of the adder 11 will cause an underflow, and the UDF flag 19 will have a logical value of "1". ”
(Value of Vdd potential) is held and output.

The AOUT output waveform in this case is shown in FIG.
It becomes as shown in (b). Since the potential of the AOUT signal and the potential Vdd of the UDF signal are subtracted by the subtractor shown in FIG. 1B, the output OUT of the external circuit outputs a faithful waveform in which the overflow portion is superimposed. To be done. The release of the UDF flag 19 is performed by overflow. However, the power supply voltages + Vcc and -Vcc of the operational amplifier A1 in FIG. 1B are | Vcc |> | 2.V
dd |.

FIGS. 3A and 3B are a block diagram of the second embodiment of the present invention and a circuit diagram of its external circuit,
The case where the OVF flag 20 is used instead of the UDF flag 19 of the first embodiment is shown. That is, the OVF flag 20 holds information on a state in which the adder 11 overflows during calculation.

FIG. 3 (b) is composed of the voice integrated circuit 21 of FIG. 3 (a) including resistors R1, R2 and R5 and an operational amplifier A1. It is configured by adding an inverting addition circuit. here,
The resistors R1, R2, and R5 all have the same resistance value if only addition is considered, but in order to realize the gain at the same time as the addition operation, the resistors R1 and R5 have the same value and the resistor R2 has the same value. If the values are different, the gain can be obtained at the same time. Further, when it is desired to perform the low-pass filtering operation, it can be realized by simply adding a capacitor in parallel with the resistor R2.

First, normal speech synthesis (DPCM decoding) without expanding the dynamic range of the waveform amplitude level will be described. The difference data at the address of the data ROM 16 designated by the memory address register 17 is read, and the difference data is temporarily stored in the difference value register 15. The adder 11 adds the stored difference value data and the previous decoded value stored in the work register 14. The addition result is transferred to the work register 14 and the D / A converter 13 as a new decoded value, converted from a digital signal to an analog signal and output. In addition, memory address register 1
7 is incremented by the incrementer 18, the next address data is set, and the above operation is sequentially repeated to perform voice synthesis.

However, during normal speech synthesis, it is premised that the calculation result of the adder 11 is always within the dynamic range of the waveform amplitude, so that overflow does not occur, so that the OVF flag 20 is set. It always holds the logical value "0" (value of GND potential). That is, the addition output of the GND potential and the AVO potential is realized by the external circuit shown in the figure.

Next, the extension of the dynamic range of the waveform amplitude level of the embodiment will be described. Here, FIG.
As shown in (a), the waveform that does not fit within the upper limit of the dynamic range of the waveform amplitude level is stored in the data ROM.
16 is written. In this case, if it is decoded outside the dynamic range of the waveform amplitude level,
The output of the adder 11 causes an overflow, and the OVF flag 20 has a logical value "1" (value of Vdd potential).
Will be held and output.

The AOUT output waveform in this case is shown in FIG.
It becomes as shown in (b). Since the potential of the AOUT signal and the potential Vdd of the OVF signal are added by the inverting adder in FIG. 3B, the output OUT of the external circuit is
A faithful waveform with the overflow portions superimposed is output. The release of the OVF flag 20 is performed by an underflow. However, the power supply voltages + Vcc and -Vcc of the operational amplifier A1 shown in FIG. 3B are | Vcc |> |
2 · Vdd |

FIG. 5 is a block diagram of a third embodiment of the present invention, showing a case where the dynamic range of the waveform amplitude level of the voice synthesis integrated circuit by the ADPCM coding system is expanded, and its external circuit. 1 uses a circuit similar to that shown in FIG.

This embodiment is different from the conventional example (FIG. 10) in that
The same UDF flag 19 as in FIG. 1A is added. That is, the adder / subtractor 51, the accumulator 12, and the D / A converter 1 used for the ADPCM decoding process.
3, a work register 52, a code register 53 for temporarily storing an ADPCM code, a data ROM 16 storing ADPCM, a memory address register 17 indicating a data address of the data ROM 16, and a value of the memory address register 17. The incrementer 18, the quantization coefficient selector 54 that selects the quantization coefficient based on the value of the code register 53, the quantization coefficient table 55 that stores the quantization coefficient, and the quantization coefficient. Quantization coefficient register 56 for temporary storage, multiplier 57 for multiplying the quantized coefficient by the quantization width used in the previous decoding processing, working register 58, and multiplication register 59 for storing the multiplication result. And a UDF flag 19 which holds information on a state in which the adder / subtractor 51 underflows during calculation.

First, normal speech synthesis (ADPCM decoding) will be described. Data RO composed of a read-only memory or the like indicated by the memory address register 17
The ADPCM code data of the address of M16 is read and AD
The PCM code data is temporarily stored in the code register 53.
The negative sign portion (S) of the stored ADPCM code is sent to the adder / subtractor 51 as a control signal for addition / subtraction switching control corresponding to determination of whether the amplitude level is positive or negative.

Amplitude information other than the negative sign part (S) of ADPCM is sent as a selection control signal of the quantization coefficient selector 54, and the quantization coefficient selector 54 uses the signal from the sign register 52 to quantize. The corresponding quantization coefficient is selected from the quantization coefficient table 55. The selected quantized coefficient is stored in the quantized coefficient register 56. Since the quantization width used in the previous decoding process is already stored in the work register 58, the multiplier 57 is used to multiply the contents of the quantization coefficient register 56 and the work register 58 to multiply the new quantization width. Store in register 59.

Using the value of the multiplication register 59 as a reference, the adder / subtractor 51, the accumulator 12 and the work register 52 are used for ADP.
Accumulation and decoding are performed by repeating addition / subtraction for the number of times based on the CM code data. The decoded digital signal is converted into an analog signal by the D / A converter 13 and output. Further, the memory address register 17 is incremented by the incrementer 18, the next address data is set, and the above operation is sequentially repeated to perform voice synthesis.

However, since it is premised that the arithmetic result of the adder / subtractor 51 always falls within the dynamic range of the waveform amplitude during normal speech synthesis, underflow cannot occur, so the UDF flag is not generated. 19
Always holds the logical value "0", that is, the GND potential and AO
The subtraction output of the UT potential is realized by the external circuit of FIG.

Next, the extension of the dynamic range of the waveform amplitude level will be described. Here, as shown in FIG. 2A, it is assumed that a waveform that does not fall within the lower limit of the dynamic range of the waveform amplitude level is written in the data ROM 16. When decoding is performed below the lower limit of the dynamic range of the waveform amplitude level, the adder / subtractor 51
Output will cause underflow and UDF
The flag 19 holds and outputs the logical value "1" Vdd potential value). At this time, the AOUT output waveform is as shown in FIG.
It becomes as shown in (b). The potential of the AOUT signal and the potential Vdd of the UDF signal are subtracted by the subtractor shown in FIG. 1B, and the output OUT of the external circuit outputs a faithful waveform in which the overflow portions are superimposed. The release of the UDF flag 19 is performed by overflow.

Further, in the case where a waveform which does not reach the upper limit is input to the speech synthesis circuit based on the ADPCM coding system, the UDF flag 19 in FIG.
The OVF flag 20 of (b) can be used.

Further, in these embodiments, the case where the UDF flag 19 and the OVF flag 20 are used independently has been described, but when both are added at the same time, the upper and lower limits of the dynamic range of the waveform amplitude level can be expanded simultaneously. Obviously, it will be a circuit.

[0048]

As described above, according to the present invention, by outputting the internal operation information to the terminal of the voice synthesis integrated circuit for decoding the differential code and connecting the simple external circuit,
The lower limit or the upper limit of the dynamic range of the waveform amplitude level can be expanded, and high-quality speech synthesis can be performed. Also, as the external circuit in the present invention, the conventional one required a circuit such as an amplifier and a filter, but it is possible to add only a small amount of parts such as a resistor for addition, and the circuit configuration is simple. Can be converted.

[Brief description of drawings]

1A and 1B are a block diagram of an embodiment of the present invention and a circuit diagram of an external circuit thereof.

2A and 2B are waveform diagrams showing respective signals before and after encoding according to FIG.

3A and 3B are a block diagram of a second embodiment of the present invention and a circuit diagram of an external circuit thereof.

4 (a) and 4 (b) are waveform diagrams showing respective signals before encoding and after decoding according to FIG.

FIG. 5 is a block diagram of a third embodiment of the present invention.

6A to 6C are general PCM of 3 to 5 bits.
Signal waveform diagram.

7A and 7B are a general DPCM system and A
The waveform diagram explaining a DPCM system.

8A to 8F are waveform charts for explaining a dynamic range of a signal according to a conventional example.

FIG. 9 is a block diagram of a conventional DPCM-based voice synthesis circuit.

FIG. 10 is a block diagram of a speech synthesis circuit according to a conventional ADPCM method.

[Explanation of symbols]

11,11a adder 12 Accumulator 13 A / D converter 14,52,58 work registers 15 Difference register 16 data ROM 17 Memory address register 18 Incrementer 19 UDF flag 20 OVF flag 21,21a Speech synthesis integrated circuit 51,51a adder / subtractor 53 code register 54 Quantization coefficient selector 55 Quantization coefficient table 56 Quantization coefficient register 57 multiplier 29 multiplication register A1 operational amplifier

Claims (2)

[Claims] 1. A storage means for storing a difference code, a reading means for reading the difference code from the storage means, an addition / subtraction means for combining the read difference code into an audio signal, and an output of the addition / subtraction means. In a voice synthesis circuit including an output means for converting to an analog signal and outputting a synthesized waveform, it is detected that the lower limit or the upper limit of the dynamic range of the waveform amplitude level is exceeded in the decoding operation of the differential code from the output of the adding / subtracting means. A voice synthesizing circuit comprising: an arithmetic information output means for outputting an over output to notify, and an analog signal adding means for adding the over output of the arithmetic information output means and the output of the output means. 2. The differential code is a DPCM code or ADPC
The speech synthesis circuit according to claim 1, which is an M code.