JPH0519796B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A memory circuit equipped with a hysteresis type differential amplifier circuit for detecting read data, which discharges data by a clock to bring both data bus lines to the same predetermined voltage level. This enables high-speed reading by setting the amplifier circuit to an active state before data reading.

[Industrial application field]

The present invention relates to a memory circuit, and particularly to a memory circuit that enables high-speed data reading.

[Conventional technology]

One conventional method for detecting the differential voltage on a data bus line (DB,) due to data read from a cell is to use a conventional differential amplifier. However, the amplification factor of a normal differential amplifier is not very large, so in order to amplify the tiny input voltage difference on the data bus line to the required level, it must pass through several more stages of differential amplifiers, which takes a long time to read out. The problem was that it was long.

To solve this problem, there is a method using a hysteresis type differential amplifier. According to this method, since the amplification factor is very large, sufficient amplification can be achieved with one stage of amplifier.

[Problem that the invention seeks to solve]

However, in the case of a hysteresis type differential amplifier, its characteristic is the hysteresis characteristic, that is, the input threshold voltage when transitioning from a low level to a high level.
VTH(H) shifts to high level side, while input threshold voltage VTH(L) when transitioning from high level to low level
has the characteristic of shifting to the lower level side, so the detection start difference voltage is larger than that of a normal differential amplifier.
Therefore, it takes a long time to detect the differential voltage. That is, although it has the advantage of being amplified at an extremely high amplification rate after detection, it takes a long time to start detection, resulting in a problem that high-speed readout cannot be achieved.

The present invention was created in view of the problems of the prior art, and aims to provide a memory circuit equipped with a hysteresis type differential amplifier that enables faster data reading.

[Means for solving problems]

The memory circuit of the present invention has two different input threshold voltages, as illustrated in FIGS. In a memory circuit equipped with a hysteresis type differential amplifier 7 for amplifying a differential voltage, a circuit 9 generates a clock pulse in response to a transition of an address signal, and a circuit 9 generates a clock pulse in response to the transition of an address signal, and a circuit 9 generates a clock pulse in response to the clock pulse. a circuit 4 for shorting the data bus line pair (DB,) in response to the clock pulse;
circuits 5 and 6 for discharging the voltage to a state where the voltage is lower than the intermediate voltage obtained by the short circuit and the sensitivity of the hysteresis type differential amplifier is higher; The present invention is characterized in that the differential voltage can be detected after the input is completed.

According to the memory circuit of the present invention, the data bus line pair is short-circuited and rapidly discharged in response to a clock pulse generated by detecting a transition of an address signal.

Therefore, the voltage of the data bus line pair is set to the voltage at which the hysteresis type amplifier is most likely to operate (threshold voltage VTH(L) and threshold voltage VTH(H) of the hysteresis type amplifier).
The time required to set the voltage to approximately midway between
It can be significantly shorter than when only short circuits are used.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a memory circuit according to an embodiment of the present invention.

In the figure, QB1, QB2, QB7, and QB8 are N-channel MOS transistors for bit line loads, and 1 is a cell with load resistors R ₁ and R ₂ , N-channel MOS transistors for driving, QB5, QB6, and N-channel MOS for reading/writing. It is composed of transistors QB3 and QB4.
X ₀ to _{X o-1} are word lines, Y ₀ to _{Y o-1} are bit line selection lines, and QB9 to QB12 are bit line selection transistors. Further, 2 and 3 are data bus lines (DB) and ().

5 is connected to the data bus line ( DB ) while the inverted clock of the address clock CP, which will be described later, is input.
This is a circuit that discharges 3 to the low level side, and is an N channel.
Similarly, 6 is a circuit that discharges the data bus line (DB) 2 while the inverted address clock is input, and is composed of an N-channel MOS transistor QB17.
It's getting more familiar. 4 is the address clock CP
While inputting, the paired data bus lines 2 and 3
This circuit short-circuits the P-channel MOS transistor QB15. Furthermore, P channel
MOS transistors are marked with white circles in the figure to distinguish them from N-channel MOS transistors.

In addition, 7 has data bus lines 2 and 3 as two inputs,
It is a hysteresis type differential amplifier that outputs S, and has load resistances RL1 to RL4 and N channels.
It consists of MOS transistors Q18 to Q23.

Next, the operation of reading data from the cells of the circuit according to the embodiment of the present invention shown in FIG. 1 will be explained with reference to the waveform diagram shown in FIG. For convenience of explanation,
Before new data is read from a cell, the state of data bus line (DB) 2 is set to high level, and the state of data bus line (DB) 3 is set to low level.

When the address signal changes in such a state, the address clock generation circuit described later detects the change in the arbitrary address signal and generates the address clock.
Generates CP and its inverse clock. As a result, N-channel MOS transistor QB1
6. QB17 and P channel MOS transistor QB15 are turned on, data bus lines 2 and 3 are short-circuited and rapidly fall, and when the address clock ends, both data bus lines 2 and 3 are set to the same predetermined voltage level. Ru. As a result, the N-channel MOS transistors QB18 to QB23 of the hysteresis type differential amplifier 7 are in a half-on state, that is, in an active state. In this way, the hysteresis type differential amplifier 7 is already in the active state even when no differential voltage is generated at the input.

On the other hand, the decoder output has already been determined at the end of the address clock. Therefore, upon completion of the address clock, the P channel MOS transistor QB15 and the N channel MOS transistor
When the QBs 16 and 17 are turned off and a minute voltage difference due to read data appears at the input of the hysteresis differential amplifier 7, the output of the hysteresis differential amplifier 7, which is already in an active state, is thereby rapidly inverted.

As described above, according to the embodiment circuit of the present invention, the voltage difference between the data buses is eliminated in advance using a high-speed address clock, and the hysteresis type differential amplifier is set to the activated state. When a voltage difference occurs between the data buses due to read data, it can be immediately detected, and therefore data read can be read out at a significantly faster speed.

Next, an address clock generation circuit according to an embodiment of the present invention will be explained. Figure 3 is a circuit diagram of an address transition detection circuit and an address clock generation circuit. Similarly to Figure 1, transistors marked with white circles represent P-channel MOS transistors, and transistors without marks represent N-channel MOS transistors. It represents a MOS transistor.

In the figure, 8 is an address transition detection circuit, and 9 is an address clock generation circuit.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the waveform diagram shown in FIG. 4. N1 to N5 in Figure 4
indicates each node, CP indicates an address clock, and CP indicates an inverted clock of the address clock CP.

First, assume that address signal _A0 changes from low level to high level. Inverter circuit (P channel MOS transistor QA3 and N channel MOS
Consists of transistor QA4. ) output N1 is
MOS resistor (P channel MOS transistor QA
1 and an N-channel MOS transistor QA2. ), so the level changes from high to low after a certain period of time. By the way, the address signal _A0 is directly input to the gate of the N-channel MOS transistor QA5. Therefore, the N-channel MOS transistor QA5 outputs a pulse whose pulse width is this delay time.

On the other hand, at the same time, address signal ₀ changes from high level to low level, but the inverter circuit (P channel MOS transistor QA8 and N channel MOS transistor
The output N2 of the MOS transistor QA9 (consisting of MOS transistor QA9) is
MOS resistor (P channel MOS transistor QA
6 and N-channel MOS transistor QA7), the high level changes from high level to low level with a delay. By the way, N-channel MOS transistor
Address signal ₀ is directly input to the gate of QA10. Therefore, in this case, N-channel MOS
Transistor QA10 does not output a pulse. However, when A ₀ changes from high level to low level, a pulse is output from the N-channel MOS transistor QA10 side. That is, whenever the address signal _A0 changes, a pulse is output to N3. This pulse turns on the N-channel MOS transistor QA11.

Since each address transition detection circuit 8 outputs a low-level pulse even when other address signals Ai change, a low-level pulse as an overlap of the output pulses of each address transition detection circuit 8 is output to N4. .

Next, when this pulse changes from a high level to a low level, a four-stage inverter circuit (the first stage consists of a P channel MOS transistor QA15 and an N channel MOS transistor QA16; the second stage consists of a P channel MOS transistor QA17 and an N channel MOS transistor QA17) Consists of channel MOS transistor QA18.The third stage is P channel MOS transistor QA19 and N
It consists of a channel MOS transistor QA20.
The 4th stage is a P channel MOS transistor QA21
and an N-channel MOS transistor QA21. ), the waveform is shaped and output. on the other hand,
This change from high level to low level is caused by P channel MOS transistor QA12 and N channel.
An inverter circuit consisting of a MOS transistor QA13 provides an output of N5. As a result, the N-channel MOS transistor QA14 is turned on during the rise of the output of N5, and the next stage inverter circuit (consisting of the P-channel MOS transistor QA17 and the N-channel MOS transistor QA18) is turned on.
input to low level. In this way, the output of the final stage inverter circuit changes from high level to low level. That is, the pulse width of the address clock CP as the final output is determined by the rise time of the output N5 and the threshold voltage of the N-channel MOS transistor QA14, and is not dependent on the pulse width of N4.
In addition, when N4 rises, N channel MOS
Since transistor QA14 is turned off, address clock CP is not generated at this time. Further, the inverted clock of the address clock CP can be obtained from the output of the third stage.

〔Effect of the invention〕

As explained above, according to the present invention, the voltage difference between the data buses is eliminated in advance by using a high-speed address clock, and the hysteresis type differential amplifier is set to the activated state, so that the read data Therefore, when a voltage difference occurs between the data buses, it can be detected immediately, and data reading can be performed at a significantly faster speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory circuit according to an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of the embodiment circuit of FIG. FIG. 3 is a circuit diagram of an address transition detection circuit and an address clock generation circuit according to an embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining the operation of the embodiment circuit of FIG. 1... Cell, 2, 3... Data bus line, 4...
Short circuit, 5, 6...Discharge circuit, 7...Hysteresis type differential amplifier, 8...Address transition detection circuit, 9...Address clock generation circuit.

Claims (1)

[Claims] 1. A hysteresis-type differential amplifier having two different input threshold voltages and amplifying a voltage difference generated between a pair of data bus lines (DB,) by data read from a cell. The memory circuit includes: a circuit that generates a clock pulse in response to a transition of an address signal; a circuit that shorts the data bus line pair (DB,) in response to the clock pulse; and a circuit that shorts the data bus line pair (DB,) in response to the clock pulse; and a circuit for discharging the bus line pair (DB,) and setting the voltage to a state lower than the intermediate voltage obtained by the short circuit and in which the sensitivity of the hysteresis type differential amplifier is higher. and a memory circuit that makes it possible to detect the differential voltage after the input of the clock pulse ends.