JPH05197939A - Track bend detecting device - Google Patents

Abstract

PURPOSE:To precisely detect the bend quantity of a track by delaying one side signal of specific signals regenerated by respective heads and detecting a regenerative time difference with other specific signal. CONSTITUTION:This device is provided with a first specific signal separation means 15 separating the first specific signal from a regenerative signal regenerated by a first magnetic head 2 and a second specific signal separation means 16 separating a second specific signal from the regenerative signal regenerated by a second magnetic head 3. Further, this device is provided with a delaying means 17 delaying hourly the first specific signal and a time difference detection means 18, as well detecting a time difference between the first specific signal and the second specific signal after delayed. By delaying the first specific signal by a time corresponding to the attaching interval of respective heads 2, 3 constituting a pair heads 8 and measuring the regenerative time difference with the second specific signal regenerated in the time, the specific signals on the same position on the recording track are compared and the bend quantity of the track is detected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a track bend detecting device for a magnetic recording / reproducing apparatus.

[0002]

2. Description of the Related Art As a track bending amount detecting device,
There is one in which two types of specific signals recorded on a track are reproduced and the reproduction time difference between these specific signals is used as a tracking error signal.

This method will be described first. FIG. 7 is a diagram showing recording tracks on the magnetic tape. In the figure, 1 is a magnetic tape, which is transported in the direction of arrow A.
Reference numerals 2 and 3 denote first and second magnetic heads having different azimuth angles, which are fixed on the rotating drum at a constant distance B. The magnetic heads 2 and 3 formed of these groups will be hereinafter referred to as a pair head. C indicates the scanning direction of each head. Recording tracks 4 and 5 are recorded by the magnetic heads 2 and 3. If the recording start time of the signal to be recorded by the second magnetic head 3 is delayed by a time corresponding to the interval b for recording, as shown in FIG. 7, the end portions of the recording tracks 4 and 5 are aligned on the magnetic tape 1. Can be recorded. 6
Reference signals 7 and 7 are specific signals. The specific signals 6 and 7 are, for example, a horizontal synchronizing signal in the analog VTR and a sync signal added to each signal block in the digital VTR. Then, the specific signals 6 and 7 are usually recorded on one recording track by about 200 to 300 pieces.

FIG. 8 is a diagram showing a relative positional relationship between a recording track and a pair head. In the figure, 8 (8
A, 8B, 8C) are pair heads composed of magnetic heads 2 and 3 having different azimuth angles, and scan in the direction of arrow C. In FIG. 8, the gap B between the magnetic heads 2 and 3 forming the pair head described in FIG. 7 is shown as zero. Reference numerals 4 and 5 are recording tracks recorded by the pair heads. Reference numerals 6 and 7 denote recording positions of specific signals, and a plurality of specific signals are recorded on one track. Pair head 8
A indicates a state in which the recording tracks 4 and 5 are on-track. 8B and 8C are also pair heads, and show a state of mistracking to the right and left of the recording track, respectively.

When the pair head 8 having such a relative positional relationship reproduces and scans a recording track, the reproduction time differs even for signals recorded at the same time. For example, at the scanning position of the pair head 8A, the specific signals 6 and 7 are reproduced by the magnetic heads 2 and 3 at the same time,
At the head scanning position of the pair head 8B, the time when the specific signal 6 is reproduced by the first magnetic head 2 is shorter than the time when the specific signal 7 is reproduced by the second magnetic head 3.
Further, at the head scanning position of the pair head 8C, the time for the specific signal 6 to be reproduced by the first magnetic head 2 is later than the time for the specific signal 7 to be reproduced by the second magnetic head 3. Therefore, the track deviation amount can be known by examining the reproduction time difference between the specific signals 6 and 7 reproduced by the respective magnetic heads 2 and 3 which form the pair head 8. The AC component of this track deviation amount is equal to the track bending amount.

FIG. 9 shows the track deviation amount and the pair head 8.
FIG. 6 is a diagram showing a relationship with the reproduction time difference of the specific signals 6 and 7 reproduced by the magnetic heads 2 and 3 constituting the above. The horizontal axis indicates the track shift amount, and the vertical axis indicates the reproduction time difference. The position indicated by 0 is the on-track position. The relationship between the track shift amount and the reproduction time difference is represented by D.

A specific method for detecting the amount of track bending using the above principle is disclosed in, for example, Japanese Patent Laid-Open No. 12114/1990.
No. 8 publication. This conventional method is a method of measuring the reproduction time difference of each reproduced specific signal in real time each time.

[0008]

By the way, as shown in FIG. 7, the magnetic heads 2 and 3 constituting the pair head 8 are attached with a space B therebetween. This is due to a physical limitation that the two magnetic heads 2 and 3 cannot be installed side by side. The value obtained by measuring the reproduction time difference between the specific signals 6 and 7 reproduced by the pair head 8 in real time does not represent the true track bending amount.

FIG. 10 is a diagram showing a relative positional relationship between a recording track and a head scanning locus. In this example, the head scanning locus will be described as having a track bend as shown in FIG. In the figure, solid lines 4 and 5 are recording tracks, and broken lines 9 and 10 are head scanning loci. The magnetic heads 2 and 3 forming the pair head 8 scan in the direction of arrow C, and the magnetic heads 2 and 3 are at positions separated by a distance B. Reference numerals 6a, 6b and 7a indicate recording positions of the specific signals 6 and 7.

When the reproduction time difference between the specific signals 6 and 7 reproduced by the pair head 8 having the constant interval B is measured in real time, the tracking error amount obtained as a result does not mean that the true track bending is detected. This is because the track bending amount at the recording position E is not obtained until the reproduction time difference between the specific signal 6a and the specific signal 7a is detected, but in the pair head 8 shown in FIG. 10, the specific signal 6b and the specific signal 7a are obtained. The difference in playback time between and will be measured. Therefore, the reproduction time difference at the recording position E should originally be zero, but it has a value influenced by the amount of bending during the constant interval B, and the true amount of track bending cannot be measured. become.

The present invention solves the above problems, and an object of the present invention is to provide a track bend detecting device capable of measuring a true track bend amount.

[0012]

In order to solve the above problems, a first means of the present invention is a first specific signal for separating a first specific signal from a reproduced signal reproduced by a first magnetic head. Separation means, second specific signal separation means for separating the second specific signal from the reproduction signal reproduced by the second magnetic head, delay means for delaying the first specific signal in time, and delay It is provided with a time difference detecting means for detecting a time difference between the subsequent first specific signal and the second specific signal.

The second means of the present invention comprises, as the delay means in the first means, N kinds of clocks (N is a natural number of 2 or more) and N shift registers operating at each clock. However, the output signal of the arbitrary natural number i-th shift register is connected to the input of the (i + 1) -th shift register, and the signal input to the first shift register is delayed by a predetermined time.

A third means of the present invention is a shift register for shifting an input signal with a constant clock signal,
Sawtooth wave generating means that is reset at the cycle of the clock signal and sample and hold means that samples and holds the output value of the sawtooth wave generating means at the edge of the input signal are provided. The configuration is such that the shift time of the input signal is corrected.

[0015]

According to the above-mentioned first means, the first specific signal is delayed by the time corresponding to the mounting interval of the heads constituting the pair head, and the reproduction time difference from the second specific signal reproduced at that time is delayed. Therefore, the specific signals at the same position on the recording track can be compared, and the true track bending amount can be detected.

Further, according to the second means, it is possible to reduce the number of stages of the D-FF circuit forming the shift register. Furthermore, according to the third means, it is possible to set a highly accurate delay time with a simple configuration.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a track bend detecting device according to an embodiment of the present invention, and FIG. 2 is a diagram showing waveforms at respective parts in FIG.

As shown in FIG. 1, the track bend detecting device includes first and second magnetic heads 2 and 3 which form a pair head 8 and signals a and which are reproduced from the respective magnetic heads 2 and 3.
First and second amplifier circuits 11 and 12 for amplifying b
And the amplified signals c and d as video signals e at the terminal 1
3, the video signal processing circuit 14 for outputting to 3, the first and second specific signal separating means 15 and 16, and the specific signal delaying means 17.
And a reproduction time difference detecting means 18 and a track bending delay means 19.

First and second specific signal separating means 15, 16
Is for separating the specific signal from the reproduced signal, and the first specific signal separating means 15 separates the first specific signal f shown in FIG. 2 (b) from the reproduced signal c, and the second specific signal separating means. 16
Separates the second specific signal g shown in FIG. 2 (c) from the reproduced signal d. The reproduction time of the second specific signal g is reproduced with a delay of time t1 corresponding to the mounting interval B of the magnetic heads 2 and 3 from the reproduction time of the first specific signal f.

The specific signal delay means 17 has the above-mentioned time t1.
Only the first specific signal f is delayed, and the delayed specific signal h
Is output. Details of the specific signal delay means 17 will be described later.

The reproduction time difference detecting means 18 outputs the reproduction time difference between the second specific signal g1 and the delayed first specific signal h1 to obtain the level indicated by i1 in FIG.
The operation of comparing the specific signal g2 of (1) with the delayed first specific signal h2 to obtain the level of i2 is repeated. With the configuration of the reproduction time difference detection means 18, for example, the time difference between the second specific signal g and the delayed first specific signal h1 can be measured by counting a constant clock signal.
The reproduction time difference detecting means 18 outputs a voltage level according to the amount of track bending as shown in FIG. 2 (f), for example.
The waveform of FIG. 2 (e) shows the regular track bending amount k. The output i of the reproduction time difference detection means 18 is output with a delay of time t1 from the regular track bending amount k shown in (e) of FIG.

The track bend delay means 19 delays the output signal i from the reproduction time difference detection means 18 by a time t2 and outputs a signal j. The signal j is H.264 for a regular track bend amount k. The SW signal 1 is output with a delay of a half cycle. Therefore, H.264. The signal k indicating the half-cycle track bending amount of the SW signal 1 is output at the time position m.

In the magnetic recording / reproducing apparatus, the linearity of the recording track recorded on the magnetic tape depends on the mechanical accuracy and running system peculiar to the magnetic recording / reproducing apparatus. The bending shape and the bending amount of each recording track do not change abruptly. Therefore, the signal k indicating the track bending amount is set to H.264. There is no problem even if it is used after being delayed by a half cycle of the SW signal 1.

The output signal of the track bending delay means 19 can be supplied to an electromechanical conversion element composed of, for example, a piezoelectric element equipped with a reproducing magnetic head and used as a track bending correction signal during reproduction.

Further, the bending signal j after the delay can be used for adjusting the traveling system which is necessary when manufacturing the equipment. In order to improve compatibility between devices, when manufacturing devices, it is necessary to adjust the running system so as to minimize the amount of track bending peculiar to the devices. At this time, if the signal j indicating the accurate track bending amount can be obtained, the signal j is monitored while the master tape having the small track bending amount is reproduced, and the change range of the level of the signal j is minimized. It will be possible to adjust the traveling system in real time.

Next, details of the specific signal delay means 17 will be described. As a means for delaying the specific signal, a method using a fixed delay line, a method using a monostable multivibrator, a method using a shift register, or the like can be considered. Here, a method using a shift register will be described. Further, the specific signal delay means 17 has a small number of stages of the shift register and can obtain an accurate delay time.

The shift register transmits the state of the D flip-flop circuit (D-FF circuit) at the previous stage to the next stage every time a clock signal is input. Therefore, if the signal to be delayed is input to the data input terminal of the D-FF circuit and the clock signal of an appropriate frequency is input to the clock terminal of the D-FF circuit, the number of stages of the D-FF circuit that constitutes the shift register is reduced. The input signal can be delayed by an amount multiplied by the period of the clock signal. The accuracy of the delay amount at this time is determined by the frequency of the clock signal input to the shift register. Therefore, in order to delay the input signal with high accuracy, it is necessary to use a signal having a high frequency as the clock signal. On the contrary, the higher the clock signal is, the more the D-FF circuit of the D-FF circuit can obtain a constant delay amount. You will have to increase the number of steps.

The specific signal delay means 17 of the present invention is devised so that the number of stages of the shift register can be reduced as much as possible and the signal can be delayed accurately. FIG. 3 is a block diagram of a specific signal delay means in the track bend detecting device of the present invention, and FIG. 4 is a diagram showing waveforms of respective parts of FIG.

As shown in FIG. 3, the specific signal delay means 17
Is composed of a flip-flop circuit (FF circuit) 20, six D-FF circuits 21 to 26, a frequency dividing circuit 27, and both edge detection circuits 28. Note that the block portions surrounded by broken lines respectively include three D-FF circuits 21 to 21.
Shift registers 29, 3 composed of 23, 24-26
0, 31 is a terminal for inputting the signal f from the first specific signal separating means 15, 32 is a clock signal CL1
Is a terminal to which is input, and 33 is a terminal which outputs the signal h from the both-edge detection circuit 28. Here, in this embodiment, 3
Although the shift registers 29 and 30 of stages are described as an example, the number of stages of the shift registers may be increased as necessary.

The first specific signal f is input from the terminal 31, and the FF circuit 20 outputs the signal n. Terminal 32
The clock signal CL1 is input from and is used as the clock signal of the shift register 29. The clock signal CL1 is also divided into 1 / n by the frequency dividing circuit 27 and used as the clock signal CL2 of the shift register 30. The frequency divider circuit 27 outputs the output signal o of the shift register 29.
Are reset at both edges of, and the output signal becomes a signal indicated by CL2. The both-edge detecting circuit 28 extracts both edges of the output signal p of the shift register 30 and outputs the signal h. Both edge detection circuits 28 are D-FF circuits 21-2.
By taking the exclusive OR of the signal obtained by delaying the input signal p by 1 clock signal by using 6 and the input signal p, the pulse signal can be output at the timing of both edges of the input signal p.

The basic structure of the delay means according to the present invention is composed of a shift register 29 which operates by the clock signal CL1 and a shift register 30 which operates by a clock signal CL2 obtained by dividing the clock signal CL1. in this way,
Shift registers 29 having different clock signal frequencies,
By connecting 30 in cascade, the number of stages of the D-FF circuits 21 to 26 forming the shift registers 29 and 30 can be reduced as compared with the case where the delay circuit is formed only of the shift register using only the clock signal having the high frequency. be able to. Further, by arranging the shift register 29 that operates with the high-frequency clock signal CL1 in the front stage and the shift register 30 that operates with the low-frequency clock signal CL2 in the rear stage, the accuracy of the overall delay time can be increased. The accuracy can be determined by the clock signal CL1.

This will be described with reference to FIGS. 3 and 4. When the first specific signal f shown in (a) of FIG. 4 is input to the FF circuit 20, the output signal n of the FF circuit 20 becomes
It becomes the form shown in (b). This output signal n is transferred to the D-FF circuit 2
If it is input to the data input terminal 1, the clock signal CL1
The input signal is latched at the rising edge of
Becomes The time difference t3 between the signal n and the signal n1 is an error in the delay time that occurs because the signal n and the clock signal CL1 are not synchronized. The maximum value of this error time is one cycle of the clock signal CL1. The signal n1 becomes the signal o via the D-FF circuits 22 and 23. The time difference t4 between the signal n1 and the signal o is exactly twice the cycle of the clock signal CL1. The clock signal CL2 is a signal obtained by dividing the frequency of the clock signal CL1, and the frequency dividing circuit 27 is reset at both edges of the signal o. If the signal o is input to the shift register 30 that operates with the clock signal CL2, (e) in FIG.
The signal p is delayed by the time t5 as shown in FIG. This delay time t5 is exactly 2.5 of the clock signal CL2.
Doubled. By using the shift registers 29 and 30 described above, the first specific signal f can be delayed by the delay time t6 including the error time t3.

In the present embodiment, the configuration using two types of shift registers 29 and 30 having different clock signals has been described as an example, but any N types (N is a natural number of 3 or more).
Obviously, N kinds of shift registers which operate with the clock signal may be used.

Next, the specific signal delay means 17 according to another embodiment of the present invention will be described. FIG. 5 shows a specific signal delay means 17 and a reproduction time difference detection means 18 according to another embodiment.
FIG. 6 is a block diagram showing a waveform, and FIG. 6 is a diagram showing a waveform of each part of FIG.

As shown in FIG. 5, the specific signal delay means 17
Includes an FF circuit 41, a shift register 42 having an arbitrary number of stages to shift the input signal q by the clock signal CL3, a sawtooth wave generation circuit 43 reset at the cycle of the clock signal CL3, and the sawtooth waveform. A sample and hold circuit 44 that samples and holds the output value (signal r) of the wave generation circuit 43 at the edge of the input signal q, an A / D conversion circuit 45, and a conversion circuit 46 are provided.

Here, 47 to 49 are terminals for inputting the second specific signal g, the first specific signal f, and the clock signal CL3, 50 is an adder, and the output signal i from the adder 50 is shown in FIG. Is input to the track bending delay means 19.

The signal q output from the FF circuit 41 shown in FIG. 6 (a) is asynchronous with the clock signal CL3 shown in FIG. 6 (c). Therefore, the signal q and the shift register 4
Time difference s with the signal (signal corresponding to the signal n1 in FIG. 4 (c)) obtained through the first D-FF circuit constituting
Has an error of one cycle of the maximum clock signal CL3. This error is due to the sawtooth wave generation circuit 43, the sample hold circuit 44, the A / D conversion circuit 45, and the conversion circuit 4.
It is corrected by the circuit consisting of 6.

The sawtooth wave generating circuit 43 generates a clock signal C.
It is reset at the rising edge of L3 and is charged with constant current in the other period. The output signal r of the sawtooth wave generation circuit 43 is input to the sample hold circuit 44, sampled and held at both edges of the signal q, and (d) and (e) of FIG.
As shown in, the sampled voltage r1 is held as the voltage level u1. Sample and hold circuit 4
The output signal u from 4 is input to the A / D conversion circuit 45,
Further, it is input to the conversion circuit 46. The conversion circuit 46 converts the value corresponding to the time s from the hold voltage and outputs it. Since the level r2 corresponding to the cycle of the clock signal CL3 is known, the level of the hold potential r1 is subtracted from this known level r2 and converted into time to obtain the time s. Then, by the adder 50, the reproduction time difference detecting means 1
The output signal of the conversion circuit 46 is added to the output signal of 8,
The first specific signal f is accurately delayed by a predetermined delay time.

If the output signal of the conversion means 46 is an analog signal, the output signal of the reproduction time difference detection circuit 44 is
An analog signal is output, and if the output signal of the reproduction time difference detection circuit 44 is a digital signal, it is output as a digital signal. In the delay means shown in FIG. 5, if the resolution of the A / D conversion circuit 45 is, for example, 8 bits, then 25 clock signals are used.
The delay time can be set with a precision of 6 times.

[0040]

As is apparent from the above description, according to the present invention, even if the heads constituting the pair head are installed at a fixed distance, one of the specific signals reproduced by each head is By delaying and detecting the reproduction time difference from other specific signals, it is possible to accurately detect the track bending amount.

Further, by using N kinds of shift registers operating with clock signals of N kinds of frequencies as delay means for the specific signal, the shift register D is constructed.
-The number of stages of the FF circuit can be reduced.

Furthermore, at both edges where the specific signal changes,
By correcting the error amount of the delay time due to the asynchronousness of the specific signal and the clock signal from the level of sample-holding the sawtooth wave signal that changes in the cycle of the clock signal,
It is possible to set a highly accurate delay time with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a track bend detection device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a waveform of each part of the track bend detection device.

FIG. 3 is a block diagram of a specific signal delay means of the track bend detection device.

FIG. 4 is a diagram showing a waveform of each part of the specific signal delay means.

FIG. 5 is a block diagram of a specific signal delay means according to another embodiment of the track bend detection device.

FIG. 6 is a diagram showing a waveform of each part of the specific signal delay means.

FIG. 7 is a diagram showing recording tracks on a magnetic tape.

FIG. 8 is a diagram showing a relative positional relationship between a recording track and a pair head.

FIG. 9 is a diagram showing a relationship between a track deviation amount and a reproduction time difference of each specific signal reproduced by each head forming a pair head.

FIG. 10 is a diagram showing a relative positional relationship between a recording track and a head scanning locus.

[Explanation of symbols]

 2 1st magnetic head 3 2nd magnetic head 8 Pair head 15 1st specific signal separation means 16 2nd specific signal separation means 17 Specific signal delay means 18 Reproduction time difference detection means 19 Track bending delay means 20,41 Flip-flop Circuits 21 to 26 D-flip-flop circuit 27 Frequency divider circuit 28 Both edge detection circuits 29, 30, 42 Shift register 43 Sawtooth wave generation circuit 44 Sample hold circuit 45 A / D conversion circuit 46 Conversion circuit 50 Adder f 1st Specific signal of g Second specific signal

Claims (3)

[Claims] 1. A first specific signal separating means for separating a first specific signal from a reproduction signal reproduced by a first magnetic head, and a second specification from a reproduction signal reproduced by a second magnetic head. Second specific signal separating means for separating signals, delay means for delaying the first specific signal in time, and detecting a time difference between the delayed first specific signal and the second specific signal. A track bend detection device comprising time difference detection means. 2. The delay means is composed of N types of clocks (N is a natural number of 2 or more) and N shift registers operating at each clock, and an output signal of an arbitrary natural number i-th shift register is output. The track bend detecting device according to claim 1, wherein the track bend detecting device is connected to an input of the (i + 1) th shift register and delays a signal input to the first shift register for a predetermined time. 3. As a delay means, a shift register for shifting an input signal by a constant clock signal, a sawtooth wave generating means reset at a cycle of the clock signal, and an output value of the sawtooth wave generating means. Provided with a sample and hold means for sample and hold at the edge of the input signal,
2. The track bend detecting device according to claim 1, wherein the shift time of the input signal is corrected by the output value of the sample hold means.