JPH05183010A - Laminated type semiconductor package - Google Patents

Abstract

PURPOSE: To provide a semiconductor package which is made extremely thin by making good use of TAB technology and C-4 bonding technology by adhering solder bumps of bare chips to both the surfaces of the inner lead of a TAB tape and joining the top and bottom bare chips with solder. CONSTITUTION: The solder bumps 33 and 35 of the top and reverse bare chips 33 and 34 are adhered to both the flanks of the inner lead of the TAB tape 31. Further, the top and bottom bare chips 32 and 34 are joined with the solder 36 to form a chip set C. Further, the outer lead of the TAB tape 31 adhered to the chip set C is adhered to lead frames 37 and 37' respectively to laminate the two bare chips 32 and 34. For example, the TAB tape 31 having both the flanks coated with adhesives is used and after the inner lead of the TAB tape 31 is bonded, the top and bottom bare chips 32 and 34 are joined by thermocompression bonding.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip semiconductor package in which a plurality of semiconductor chips are stacked to improve the degree of integration.
For example, the TAB technology (Tape Automated bonding)
The present invention relates to a stacked semiconductor package intended for ultra-thin devices by utilizing technology) and C-4 bonding technology.

[0002]

2. Description of the Related Art Recently, semiconductor packages have been gradually, lightly and simply made to be mounted on a paddle in order to reduce an area and a volume occupied by a bare chip inside the package. Plastic packaging
L) that leads are mounted on the chip from the
It has been gradually changed to OC (Lead-On-Chip) technology. Therefore, from the technology of mounting one bare chip in one semiconductor package, a plurality of chips may be stacked in a piggy-bag type, or
A technique of stacking a plurality of chips inside an individual semiconductor package (Nikkei Micro Devices, 1
991sus April issue) has been developed, and the following laminated semiconductor packages have been put into practical use. That is ,. Figure 6
As shown in FIG. 3, a plurality of semiconductor packages 2 and 3 are sequentially stacked on the lower semiconductor package 1 as a piggybag-type stacked semiconductor package, and the outlead 2a is bonded to the upper semiconductor packages 2 and 3. , 3a
Are joined to and electrically connected to the out leads 1a and 2a adhered to the lower semiconductor packages 1 and 2, respectively, and the out leads 1a of the lower semiconductor package 1 are SOJ.
A semiconductor package configured to be mounted in a memory module or a board level by being inwardly formed into a (Small Outline J-Lead) type has been put into practical use.

In addition ,. As shown in FIG. 7, two bare chips 3 and 4 are mounted on the inner side of one semiconductor package, but bumps 7 are formed on the pad portions on the outer side surfaces of the bare chips 3 and 4, respectively. , 8 are bonded, and the inner leads of the TAB tapes 5, 6 are bonded to the bumps 7, 8, respectively.
After the out leads of the above are bonded to the lead frames 9 and 9 ', respectively, the mold portion 10 is formed of epoxy resin, and the two bare chips 3 and 4 are laminated inside one semiconductor package. The package was put into practical use. In addition, a stacked semiconductor package in which four bare chips are stacked on the inner side of one semiconductor package by a similar method has been put into practical use. That is, as shown in FIG. 8, both upper and lower bare chips 11 and 12 on the upper side.
Bumps 13 and 14 are adhered to the upper and lower surfaces of the TAB tape 15, and inner leads of the TAB tapes 15 and 16 are respectively bonded to the bumps 13 and 14, and out leads are sequentially bonded to the lead frames 17 and 17 '. Bumps 18 and 19 are adhered to the upper and lower surfaces of the upper and lower bare chips 11a and 12a, respectively, and the inner leads of the TAB tapes 20 and 21 are bonded to the bumps 18 and 19, respectively, and the outer leads are lead frames 17 and 17. ’After being sequentially bonded,
A mold portion 22 is formed of epoxy resin, and four bare chips 11 and 1 are provided on the inner side of one semiconductor package.
It had a structure in which 2, 13, and 14 were respectively laminated.

[0004]

However, in the conventional stacked type semiconductor package having such a structure, in the case of the form described in the above paragraph, a plurality of individually formed semiconductor packages 1, 2, 3 are formed. Are stacked and wire-bonded to each of the semiconductor packages 1, 2, and 3, so that the height of the wire loop and the thickness of the molding portion of the epoxy resin increase the overall thickness to reduce the thickness of the device. There was a disadvantage that I couldn't get it.
In the case of the type described in the above item, since the inner leads of the TAB tapes are bonded to the bumps bonded to the upper and lower surfaces of the bare chips, respectively, the heights of the upper and lower TAB tapes are increased. There is a disadvantage that the overall thickness of the package becomes thick. And T
There is a disadvantage that the number of AB tapes used increases, the cost increases, and the manufacturing process is complicated. Further, since the inner lead bonding between each bare chip and each TAB tape is performed around those bare chips, there is a disadvantage that the length of each TAB tape becomes short and bonding and handling thereof become difficult. As a result, the inventors of the present invention have conducted extensive research to solve such problems, and as a result, intend to provide the following stacked semiconductor package.

[0005]

The object of the present invention is to provide a TAB.
It is an object of the present invention to provide a stacked semiconductor package which is intended to be ultra thinned by utilizing the technology and the C-4 bonding technology of the flip-chip concept. And, such an object of the present invention is TAB.
Solder bumps of the upper and lower bare chips are bonded to both sides of the inner leads of the tape, and the upper and lower bare chips are joined by solder to form a chipset, and the TAB tape out leads of the chipset are lead frames. This is achieved by providing a laminated semiconductor package in which each bare chip is laminated by being adhered to each other.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings. As shown in FIG. 1, the LOC-TSOP (T of one embodiment of the stacked semiconductor package according to the present invention is shown.
hin Small Outline Packag
In e), a solder bump 33 of a pad portion of the upper bare chip 32 is bonded to the upper side surface of the inner lead of the TAB tape 31,
The solder bumps 35 on the pad portion of the lower bare chip 34 are formed on the lower side surface of the inner lead of the TAB tape 31.
Are bonded, the upper and lower bare chips 32 and 34 are bonded by a solder 36, and the out leads of the TAB tape 31 are bonded to the lead frames 37 and 37 ', respectively. In the figure, an unexplained reference numeral 38 is a molding part.

The method of manufacturing the laminated semiconductor package having the above structure according to the present invention will be described below. First, the inner lead of the TAB tape 31 is bonded to the upper bare chip 32, and the bonding is performed by the C-4 using the solder bump 33.
It is performed by bonding. Therefore, bare chip 3
Since No. 2 is self-aligned, it is not necessary to perform fine alignment separately. Then, cover the other bare chip 34 and attach the solder bump 35 to the TAB tape 3
The inner lead 1 is C-4 bonded, and then the solder 36 is C-4 bonded to the inner side of the TAB tape 31. In this case, the TAB tape 31 on both sides of which adhesive is applied is used for LOC.
After the inner lead of the TAB tape 31 is bonded, the upper and lower bare chips 32 and 34 are made to function as the polyimide of the package.
Thermocompression bonding (thermo-compress)
Sion bonding) is performed to bond them. Two upper and lower bare chips 32, 3 joined in this way
Since 4 is regarded as one chipset C, the chipset C is referred to as SOP (Small Outline).
Package) or SOJP (SmallOutli)
ne J-Lead Package) and the out leads of the TAB tape 31 of the chip set C are bonded to the lead frames 37 and 37 'by thermocompression bonding, and then the upper and lower chips 32 and 3
Mold in encapsulation (mold enc)
application). In this case, if a test is performed before the out leads of the TAB tape 31 are bonded to the lead frames 37 and 37 ', the packaging cost can be reduced. In the stacked semiconductor package according to the embodiment of the present invention, one TAB tape 31 is used to bond two upper and lower bare chips 32 and 34 at the same time to reduce the package thickness. It is made into a mold so that the capacity can be doubled. In the embodiment of the present invention, the case of LOC-TSOP has been described, but the present invention is not limited to this case of LOC-TSOP, but LOC-TS.
OJ, LOC-SOI type package, LOC-TSO
It can also be applied to various types of semiconductor packages such as P.

As another embodiment of the present invention, as shown in FIG. 2, lead frames 37 and 37 'are inserted between two bare chips 32 and 34 by a predetermined length. The TAB tapes 31 and 31 are adhered to the inner end portions of the lead frames 37 and 37 ', respectively, and the leads of the TAB tapes 31 and 31 are formed on the pad portions of the upper and lower bare chips 32 and 34. The lead bumps 3 are attached to the solder bumps 33 and 35, respectively.
The bare chips 32, 34 are formed by mold incapsulation so that the other ends of the 7, 37 'are exposed.

In another embodiment of the present invention as described above, each pad of the upper and lower bare chips 32, 34 is bonded to the end portion of the lead frame 37, 37 'by T bonding.
The leads of the AB tapes 31 and 31 are bonded to each other. The solder bump 3 is used as the bonding method.
The C-4 bonding method using 3,35 is used.
After that, the upper and lower bare chips 32 and 34 and the lead frames 37 and 37 'inserted between the upper and lower bare chips 32 and 34 are adhered to each other to form a chip set C, and the chip set C is attached to the chip set C. Mold incapsulation is performed with polyimide. That is, between the two bare chips 32 and 34, each lead frame 37, 3
Since 7'is adhered so as to maintain a stable distance between the bare chips 32 and 34, a separate solder is not required, and the pads of the bare chips are not limited to the edge portions of the bare chips, but also the bare chips. Can be formed over the center and all desired areas. Therefore, when designing a bare chip, the pad can be arranged at any position, which is extremely convenient in design. Moreover, even when a plurality of bare chips are stacked, the lead frames of the stacked bare chips are respectively projected to the left and right sides to be integrally connected, and the lead frames are exposed to the left and right sides again from the connecting portions. A laminated bare chip can be formed by performing incapsulation on the laminated chip sets.

Further, as another embodiment of the present invention, FIG.
It is also possible to manufacture a stacked semiconductor package in which four bare chips are stacked as shown in FIG. That is, the solder bumps 3 of the upper and lower bare chips 32 and 34 are formed on both side surfaces of the inner lead of the upper TAB tape 31.
The upper and lower bare chips 32 and 34 are bonded by the solder 36, and the lower TA
The solder bumps 43 and 45 of the upper and lower bare chips 42 and 44 are adhered to both side surfaces of the inner lead of the B tape 41, respectively, and the upper and lower bare chips 42 and 44 are joined by a solder 46. Each of the out leads 31 and 41 is a lead frame 4 respectively.
7, 47 ', 48, 48', 49, 49 'are bonded to the upper and lower side surfaces, and an adhesive 51 is applied between the inner bare chips 34, 42. In the figure, the unexplained reference numeral 50 indicates a molding part.

Such four bare chips 32, 3
A method of manufacturing a stacked semiconductor package in which 4, 42 and 44 are stacked is as follows. First, the bare chips 42 and 44 on the lower side are subjected to TAB by the above-described method.
After the chip set C is formed by adhering the tape 41 to the tape 41 using the C-4 bonding technique, the out leads of the TAB tape 41 of the chip set C are connected to lead frames 47, 47 ', 48, 48', 49,4
Adhere to the lower side of 9 '. Next, the adhesive 51 is applied to the upper bare chip 42 of the chipset C,
The upper chip set packaged by the above-mentioned method is placed on the bare chip 42, and the TA of the chip set is set.
The B tape 31 out lead is connected to the lead frame 4
The upper side surfaces of 7, 47 ', 48, 48', 49, 49 'are bonded by thermocompression bonding. In this way, the four bare chips 32, 34, 42, 44 are laminated and then subjected to mold incapsulation to form the lead frames 47, 47 ', 48, 48', 49, 49 'in various shapes. The LOC-TSO shown in FIG.
J or the LOC-SOI type semiconductor package shown in FIG. 4 or the LOC-TSOP type semiconductor package shown in FIG. 5 can be manufactured.

[0012]

As described above, in the laminated semiconductor package according to the present invention, two bare chips are bonded to one TAB tape or two bare chips are bonded.
Since four bare chips are bonded to the AB tape to manufacture a laminated semiconductor package, the overall thickness of the semiconductor package can be further reduced, the structure can be simplified, and the cost can be reduced. .

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a LOC-TSOP which is an example of a stacked semiconductor package according to the present invention.

FIG. 2 is a sectional view of a LOC-TSOP which is another embodiment of the stacked semiconductor package according to the present invention.

FIG. 3 is another embodiment of the present invention, LOC-TS.
It is sectional drawing of OJP.

FIG. 4 is another embodiment of the present invention, LOC-S.
It is sectional drawing of an OI type | mold laminated semiconductor package.

FIG. 5 is another embodiment of the present invention, LOC-TS.
It is sectional drawing of OP.

FIG. 6 is a perspective view showing a conventional piggybag type stacked semiconductor package.

FIG. 7 is a cross-sectional view of a TSOP in which two semiconductor chips of a conventional stacked semiconductor package are stacked.

FIG. 8 is a sectional view of an SOJP in which four semiconductor chips of a conventional stacked semiconductor package are stacked.

[Explanation of symbols]

31, 41 TAB tape 32, 34, 42, 44 Bear chip 33, 35, 43, 45 Solder bump 36, 46 Solder 37, 37 ', 47, 47', 48, 48 ', 49, 4
9'Leadframe 51 Adhesive C Chipset

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 25/07 25/18 27/00 301 B 8418-4M

Claims (9)

[Claims] 1. Solder bumps (33, 35) of upper and lower bare chips (32, 34) are respectively adhered to both side surfaces of the inner lead of the TAB tape (31), and these upper and lower bare chips (32, 34) are bonded. Are joined by a solder (36) to form a chip set (C), and the out leads of the TAB tape (31) adhered to the chip set (C) are adhered to the lead frames (37, 37 '), respectively. A stacked semiconductor package in which two bare chips (32, 34) are stacked. 2. The upper and lower bare chips (32, 34) on both side surfaces of the inner lead of the upper TAB tape (31).
Solder bumps (33, 35) of the solder bumps (33, 35) are adhered to the upper and lower bare chips (32, 34) of the solder (3
6), and the upper and lower bare chips (42, 42) are attached to both side surfaces of the inner lead of the lower TAB tape (41).
44) solder bumps (43, 45) are adhered to each other, and the upper and lower bare chips (42, 44) are joined by a solder (46), and each out lead of the upper and lower TAB tapes (31, 41) Is a laminated semiconductor package in which four bare chips (32, 34, 42, 44) are laminated by being bonded to the upper and lower side surfaces of the lead frame (47, 47 '), respectively. 3. The inner bare chips (34, 4)
The adhesive (51) is applied between 2).
The laminated semiconductor package described. 4. The outlead of each of the TAB tapes (31, 41) is an SOJ type lead frame (47, 4).
7. The laminated semiconductor package according to claim 1, wherein the laminated semiconductor package is adhered to each of 7 '). 5. The out lead of each of the TAB tapes (31, 41) is a pad type lead frame (48, 4).
The laminated semiconductor package according to claim 1, wherein the laminated semiconductor package is adhered to each of 8 '). 6. Out leads of each of the TAB tapes (31, 41) are SOP type lead frames (49, 4).
9. The laminated semiconductor package according to claim 1, wherein the laminated semiconductor package is adhered to each of 9 '). 7. A lead frame (37, 37 ') is inserted and adhered between the upper and lower bare chips (32, 34) by a predetermined length, respectively, and these lead frames (37, 3') are adhered.
7 ') TAB tapes (31, 31) are adhered to one end of each side, and leads of the TAB tapes (31, 31) are formed on the pad portions of the upper and lower bare chips (32, 34), respectively. The chip sets (C) are molded in such that the bumps (33, 35) are adhered to each other to form a laminated chip set (C), and the other ends of the lead frames (37, 37 ') are exposed. A stacked semiconductor package that is encapsulated. 8. The upper and lower bare chips (32, 3)
4) is the lead frame (37, 37 ') according to the pad positions of the upper and lower bare chips (32, 34).
8. The stacked semiconductor package according to claim 7, wherein the length to be inserted is variable. 9. The chip set (C) is a chip set (C) in which a plurality of chip sets are stacked and formed, and the other side end of the lead frame of each individual chip set of the chip set (C) is The chipsets (C) are molded in such that the left and right leadframes of the chipsets (C) are exposed from the connecting parts after protruding to the left and right sides and integrally connected, respectively. The stacked semiconductor package according to claim 7, which is encapsulated.