JPH05182356A - Phase synchronizing circuit for information recording and reproducing device - Google Patents

Abstract

PURPOSE:To provide the phase synchronizing circuit of an information recording and reproducing device capable of detecting and correcting a phase deviation between synchronous signals of the relevant frame even when a signal generating circuit having no function making the phase between frame synchronous signals synchronize with each other except at the start of recording. CONSTITUTION:A reference clock from a CD encoder and a wobble clock synchronizing with ATIP data are frequency-divided respectively by 1st and 2nd frequency divider circuits 10, 20 having a frequency division ratio variable function and the result is supplied to a servo system circuit. A phase difference detection circuit 30 detects the delay or advance in the phase between the frame synchronizing signal of the ATIP data and the frame synchronizing signal of the subcode Q data. When the phase of the frame synchronizing signal of the ATIP data is lagged from the phase of the frame synchronizing signal of the subcode Q data, a phase difference correction circuit 40 decreases the frequency division ratio of the 2nd frequency divider circuit 20 and when the phase is advanced conversely, the circuit 40 decreases the frequency division ratio of the 1st frequency divider circuit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization circuit of an information recording / reproducing apparatus for recording information such as audio and video on a recording medium in which absolute time information has been written in advance in a recording area.

[0002]

2. Description of the Related Art In a recordable optical disk such as a write-once optical disk (CD-WO) and a magneto-optical disk (CD-MO), a wavy track with a slight amplitude is spirally engraved in its recording area. ing. The swell of the track represents absolute time information called ATIP (Absolute Time In Progroove) data, and is 22.05k.
The frequency of the swell having the fundamental frequency of Hz is the ATI
Unit length corresponding to 1 bit of P data (frequency 44.1k
It changes by ± 1 kHz depending on the contents of the bit, that is, "1" or "0" every 7 cycles of Hz).
In other words, the ATIP data is written in advance on the optical disc as the frequency change of the track waviness.

The ATIP data is composed of a large number of continuous frames each of which is composed of a bit string in which one frame contains a fixed number (84 bits) of bits and which has a fixed pattern frame synchronization signal at a predetermined position. The frame is designed to be repeated every 75 Hz.

On the other hand, when recording information such as audio and video on the above-mentioned optical disc, the number of channels of the song, the presence / absence of pre-emphasis, the song number, the time from the beginning of the song, and the absolute time from the innermost circumference of the disc. Etc., ie, the sub-code Q data is also recorded at the same time. The sub-code Q data includes a fixed number (98 bits) of bits per frame (however, the unit length corresponding to 1 bit is different from the case of ATIP data), and a fixed pattern frame synchronization is provided at a predetermined position. It is composed of a large number of frames each consisting of a bit string provided with a signal, and each frame is recorded at a period of 75 Hz.

Here, when actually recording information such as audio and video on an optical disc, the ATIP data and subcode Q data must be frame-synchronized and recorded.

Conventionally, when recording information such as audio and video on an optical disk, a signal generating circuit for generating subcode Q data together with a clock signal synchronized with ATIP data reproduced from the optical disk and information such as audio and video, Here, the clock signal of the CD encoder (strictly speaking, this is A
(The frequency-divided according to the clock signal of the TIP data) is input to a servo system circuit for controlling the relative movement of the optical disk and the recording head to synchronize its phase, and the frame synchronization of the ATIP data is performed in the CD encoder. By generating the subcode Q data in synchronization with the signal, the phase of the frame synchronization signal of the ATIP data and the phase of the frame synchronization signal of the subcode Q data are synchronized.

[0007]

However, depending on the CD encoder, the subcode Q data is generated in synchronization with the frame sync signal of the ATIP data only at the start of recording, and thereafter, the subcode Q data is independently generated according to a predetermined format. Some of them generate code Q data. In this case, if the synchronization of the clock signals is disturbed due to the offset, scratches, dust, etc. of the optical disc, the phase between the frame synchronization signals will shift and it will not be possible to correct them. There was a problem.

In view of the above-mentioned conventional problems, the present invention uses a signal generating circuit having no function of synchronizing the phases of the frame synchronization signals except when recording is started, and shifts the phases of the frame synchronization signals. It is an object of the present invention to provide a phase synchronization circuit of an information recording / reproducing apparatus which can detect the above and correct this.

[0009]

According to the present invention, in order to achieve the above object, in claim 1, one frame includes a fixed number of bits in advance in a recording area and a fixed pattern frame synchronization signal is provided at a predetermined position. A recording medium on which absolute time information composed of a number of consecutive frames composed of a bit sequence is recorded, and one frame includes a fixed number of bits together with information such as audio and video, and a fixed pattern frame synchronization is provided at a predetermined position. A clock signal synchronized with absolute time information reproduced from the recording medium when recording control information composed of a large number of frames each composed of a bit string provided with a signal,
A clock signal of a signal generation circuit that generates control information together with information such as audio and video is input to a servo system circuit that controls relative movement of the recording medium and the recording head, and recording is performed so that their phases are synchronized. In the phase synchronization circuit of the information recording / reproducing apparatus, which has a function of varying the division ratio, divides the clock signal of the signal generation circuit and supplies it to the servo system circuit, and the division ratio variable. A second frequency dividing circuit which has a function and divides the clock signal synchronized with the absolute time information and supplies it to the servo system circuit, the phase of the frame synchronization signal of the absolute time information, and the frame synchronization signal of the control information. And a phase difference detection circuit for detecting the delay or advance of the control signal, and when the frame synchronization signal of the absolute time information is behind the frame synchronization signal of the control information, the frequency division ratio in the second frequency division circuit is decreased. , Phase synchronization of an information recording / reproducing apparatus provided with a phase difference correction circuit for reducing the frequency division ratio in the first frequency dividing circuit when the frame synchronizing signal of time information is advanced with respect to the frame synchronizing signal of control information. A circuit is proposed, and in claim 2, when the phase delay amount or the lead amount is large, the decrease amount of the frequency division ratio in the second or first frequency dividing circuit is not large, and the phase delay amount or The phase synchronization circuit of the information recording / reproducing apparatus according to claim 1, wherein the amount of decrease in the frequency division ratio in the second or first frequency dividing circuit is reduced when the amount of advance is small.

[0010]

According to the first aspect of the present invention, the clock signal of the signal generating circuit and the clock signal synchronized with the absolute time information are divided by the first and second frequency dividing circuits each having a variable frequency division ratio function. The phase difference detection circuit detects the delay or advance of the phase between the frame synchronization signal of the absolute time information and the frame synchronization signal of the control information, and the absolute time is detected by the phase difference correction circuit. When the information frame sync signal is delayed with respect to the control information frame sync signal, the frequency division ratio in the second frequency dividing circuit is reduced,
Further, when the frame synchronization signal of the absolute time information leads the frame synchronization signal of the control information, the frequency division ratio in the first frequency dividing circuit is reduced. Further, according to claim 2, when the phase delay amount or the lead amount is large, the second or first phase is set.
If the amount of decrease in the frequency division ratio in the frequency divider circuit is large and the amount of phase delay or lead is small, the second or first
The amount of decrease in the frequency division ratio in the frequency divider circuit is reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a phase synchronization circuit of an information recording / reproducing apparatus of the present invention. In the figure, 1, 2, 3, 4 are input terminals, 5 and 6 are output terminals, and 10 is an output terminal. The first divider circuit,
Reference numeral 20 is a second frequency dividing circuit, 30 is a phase difference detecting circuit, and 40 is a phase difference correcting circuit.

The first frequency dividing circuit 10 receives 22.05 kHz from the CD encoder (not shown) via the input terminal 1.
A clock signal of z (hereinafter referred to as a reference clock) is frequency-divided and supplied to a servo system circuit (not shown) via an output terminal 5. As shown in FIG. It comprises a bit binary counter 11, D flip-flops 12, 13, and 14, an inverter 15, a NOR gate 16, and a NAND gate 17.

The 4-bit binary counter 11 actually divides the reference clock, and unless a load signal, which will be described later, is supplied from the NAND gate 17 to the preset enable terminal PE, or if the load signal is supplied, at that time. Unless the 4-bit correction data other than "0001" is supplied from the phase difference correction circuit 40 to the preset data input terminals D3 to D0, the reference clock input to the clock terminal C is divided by 16 and the divided reference clock is supplied. A clock (hereinafter referred to as the reference frequency-divided clock) is output from the terminal Q3. D flip-flops 12, 13
The NOR gate 16 detects the trailing edge of the reference frequency-divided clock, and generates a short pulse synchronized with the trailing edge, here, a pulse corresponding to one cycle of 22.05 kHz. Further, the short pulse synchronized with the falling edge is input to the NAND gate 17 together with an ATIP data delay signal which will be described later and becomes a load signal for the 4-bit binary counter 11. Further, the load signal is supplied to the phase difference correction circuit 40 via the D flip-flop 14.

The second frequency dividing circuit 20 is a 22.05 kHz clock signal (hereinafter referred to as a wobble clock) synchronized with the ATIP data of the optical disc, which is input through the input terminal 2 from the reproducing system of the optical head (not shown). Is divided and is supplied to a servo system circuit (not shown) via an output terminal 6. As shown in FIG. 2, a preset 4-bit binary counter 21, D flip-flops 22, 2 are provided.
3, 24, an inverter 25, a NOR gate 26 and a NAND gate 27.

The 4-bit binary counter 21 actually divides the wobble clock, and unless the load signal, which will be described later, is supplied from the NAND gate 27 to the preset enable terminal PE, or when the load signal is supplied, at that time. Preset data input terminals D3 to D0
Unless 4-phase correction data other than "0001" is supplied from the phase difference correction circuit 40, the wobble clock input to the clock terminal C is divided by 16, and the divided wobble clock (hereinafter, wobble division clock It is called.)
Is output from the terminal Q3. The D flip-flops 22 and 23 and the NOR gate 26 detect the falling edge of the above-mentioned wobble frequency-divided clock, and generate a short pulse synchronized with the falling edge, here a pulse corresponding to one cycle of 22.05 kHz. Is becoming The short pulse synchronized with the trailing edge is input to the NAND gate 27 together with an ATIP data advance signal described later, and becomes a load signal for the 4-bit binary counter 21. Also,
The load signal is supplied to the phase difference correction circuit 40 via the D flip-flop 24.

The phase difference detection circuit 30 receives a frame sync pulse of the subcode Q data (hereinafter referred to as a subcode sync pulse) input via the input terminal 3 and an optical disc input via the input terminal 4. Of the ATIP data frame sync pulse (hereinafter referred to as the ATIP sync pulse) is detected, and when the ATIP sync pulse is delayed with respect to the subcode sync pulse, the delay time is detected. High level ATI with corresponding width
The P data delay signal and, when the ATIP sync pulse is ahead of the subcode sync pulse, the high level ATIP data advance signal by a width corresponding to the time of advance are supplied to the phase difference correction circuit 40. As shown in FIG. 3, the D flip-flops 31, 32, the inverter 3
3, a NAND gate 34 and NOR gates 35 and 36.

The frame sync pulse of the subcode Q data described above is a short pulse output simultaneously with the frame sync signal of the subcode Q data from a CD encoder (not shown), and the frame sync pulse of the ATIP data of the optical disc. Is obtained by supplying the frame sync signal of the ATIP data of the optical disc output from the reproducing system of the optical head (not shown) to a circuit (not shown) that outputs a predetermined short pulse when the pattern is detected. Both of them are substantially the same as the frame sync signal of the subcode Q data and the ATIP data of the optical disc.

The phase difference correction circuit 40 includes a phase difference detection circuit 3
The ATIP data delay signal or AT input from 0
The time width of the IP data advance signal, that is, the delay amount or the advance amount is measured, and the correction data corresponding to the delay amount or the advance amount is supplied to the first frequency dividing circuit 10 or the second frequency dividing circuit 20. The frequency dividing ratio of the second frequency dividing circuit 20 or the first frequency dividing circuit 10 is decreased in accordance with the delay amount or the advance amount. As shown in FIG. 4, preset 4-bit binary counters 41, 42, It is composed of inverters 43 and 44 and AND gates 45 and 46.

The reference clock is input to the clock terminal C of the 4-bit binary counter 41 through the inverter 43, and the count enable terminal CEP is also provided.
Is supplied with an ATIP data delay signal via an AND gate 45, and when the ATIP data delay signal becomes high level, the reference clock is counted to measure its time width (however, the ripple is Since the carry-out terminal TC is connected to the other input terminal of the AND gate 45, the carry-out terminal TC stops when the count value becomes "1111" and no further counting is performed.). A 4-bit count value corresponding to the time width of the ATIP data delay signal is supplied to the 4-bit binary counter 11 of the first frequency dividing circuit 10 as correction data. Data of "0001" is fixedly input to the preset data input terminals D3 to D0 of the 4-bit binary counter 41, and the data is the D flip-flop 14 of the first frequency dividing circuit 10.
The correction data for the 4-bit binary counter 11 is preset at the timing of the load signal supplied from the device and fixed to "0001".

Further, the 4-bit binary counter 42
The wobble clock is input to the clock terminal C of the inverter via the inverter 44, and the ATIP data advance signal is input to the count enable terminal CEP via the AND gate 46. When the level is reached, the wobble clock is counted and the time width thereof is measured (however, since the ripple carry-out terminal TC is connected to the other input terminal of the AND gate 46, the count value is "111").
When it reaches 1 ”, it stops and no more counting is done. ). The 4-bit count value corresponding to the time width of the ATIP data advance signal is used as correction data by the second frequency divider 2
0 is supplied to the 4-bit binary counter 21. Data of "0001" is fixedly input to the preset data input terminals D3 to D0 of the 4-bit binary counter 42, and the data is input to the second frequency dividing circuit 20.
The preset data is preset at the timing of the load signal supplied from the D flip-flop 24, and the correction data for the 4-bit binary counter 21 is fixed to "0001".

The first and second frequency dividing circuits 10 and 2
The outputs of the inverters 15 and 25 in 0 may be input to the clock terminals C of the 4-bit binary counters 41 and 42, respectively. In this case, the inverters 43 and 44 are unnecessary.

FIGS. 5 and 6 are signal waveform diagrams showing an example of the operation of the circuit of FIG. 1, and the operation of the circuit will be described below in accordance with this.

Reference clock a input from the input terminals 1 and 2 to the first and second frequency dividing circuits 10 and 20, respectively.
And the wobble clock b, if the phases of the subcode synchronization pulse c and the ATIP synchronization pulse d input to the phase difference detection circuit 30 from the input terminals 3 and 4 are in phase, the wobble clock b is 16 minutes by the 4-bit binary counters 11 and 21, respectively. It is divided into a reference divided clock and a wobble divided clock, which are output to the servo system circuit via the output terminals 5 and 6. The servo system circuit compares the phases of the reference frequency-divided clock and the wobble frequency-divided clock, and controls the rotation of the optical disc so that they match.

Here, the subcode synchronization pulse c and AT
When the phase of the IP sync pulse d is deviated as shown, that is, when the ATIP sync pulse d is delayed with respect to the subcode sync pulse c, the phase difference detection circuit 30 raises the width corresponding to the delayed time. A level ATIP data delay signal e is output. In this case, the ATIP data advance signal f remains low level.

When the ATIP data delay signal e becomes high level, the 4-bit binary counter 41 of the phase difference correction circuit 40 starts counting the reference clock a. At this time, if the delay of the ATIP sync pulse d with respect to the sub-code sync pulse c is large, that is, the high-level period of the ATIP data delay signal e is long, the count value of the 4-bit binary counter 41 reaches "1111", and the ripple carry occurs. Since the signal g is output from the OUT terminal TC, the output h of the AND gate 45 becomes low level and the counting is stopped. Terminals Q3 to Q0 of the 4-bit binary counter 41
The output data of the first dividing circuit 1 is the corrected data i.
It is input to the preset data input terminals D3 to D0 of the 4-bit binary counter 11 of 0.

On the other hand, the ATIP data delay signal e is also input to the NAND gate 17 of the first frequency dividing circuit 10, and the pulse synchronized with the falling edge of the reference frequency-divided clock output from the NOR gate 16 has its low level. And is supplied to the preset enable terminal PE of the 4-bit binary counter 11 as the load signal j. Therefore, the above-mentioned modified data i is loaded into the 4-bit binary counter 11 with the reference clock a immediately after the reference divided clock first falls after the ATIP data delay signal e becomes low level.

At this time, the correction data i is "1" as described above.
111 ", the Q of the 4-bit binary counter 11
Three outputs become "1" and become "0" at the next reference clock a, that is, the reference divided clock k in which a short pulse is inserted immediately after the pulse obtained by dividing the reference clock a by 16 is obtained.
Since the short pulse is regarded as one of the reference divided clocks in the servo system circuit, the reference divided clock and the wobble divided clock are not synchronized in the servo system circuit,
Here, it is judged that the wobble division clock is delayed,
The servo is operated in the direction of advancing the phase of the wobble divided clock. As a result, the phase of the ATIP sync pulse d also advances, and the phase difference from the subcode sync pulse c decreases. The preset enable terminal PE of the 4-bit binary counter 41 of the phase difference correction circuit 40 is supplied with the load signal 1 corresponding to the load signal j from the D flip-flop 14 of the first frequency dividing circuit 10.
Since the ATIP data delay signal e is low level, it is not related to the operation.

The above-described operation is repeated as long as the high-level ATIP data delay signal e is output from the phase difference detection circuit 30, whereby the phase delay of the ATIP sync pulse d with respect to the subcode sync pulse c is corrected, and the final Match each other. When the phase difference between the ATIP sync pulse d and the subcode sync pulse c becomes small, the correction data i output from the 4-bit binary counter 41 is output.
Also becomes smaller than “1111”, and the insertion position of the above-mentioned short pulse gradually approaches the next pulse immediately after the pulse divided by 16, so that the ATIP synchronization pulse d is changed to the sub-pulse by repeating the above-mentioned operation. The code sync pulse c does not go in the opposite direction.

When the phase of the ATIP sync pulse leads the subcode sync pulse, that is, ATIP
If a high level output appears in the data advance signal,
By correcting the wobble clock in the 4-bit binary counter 42 of the phase difference correction circuit 40, correction data corresponding to the amount of advance of the phase is obtained and loaded into the 4-bit binary counter 21 of the second frequency dividing circuit 20. Then, a wobble divided clock in which a short pulse is inserted after a pulse obtained by dividing the wobble clock by 16 is obtained, and the servo system circuit operates the servo in the direction of advancing the phase of the reference divided clock so that the phase of the ATIP sync pulse is changed. Delay to match the subcode sync pulse.

As described above, according to the above circuit, when the ATIP sync pulse is delayed with respect to the subcode sync pulse, a short pulse is inserted in the reference frequency division clock to reduce the frequency division ratio for the wobble clock. Because
It is possible to operate the operation of the servo system circuit in the direction of advancing the phase of the wobble divided clock, that is, in the direction of advancing the phase of the ATIP sync pulse with respect to the subcode sync pulse.
If the ATIP sync pulse is ahead of the subcode sync pulse, the division ratio for the reference clock is reduced by inserting a short pulse in the wobble frequency-divided clock. The direction of advancing the phase of the peripheral clock, that is, the direction of delaying the phase of the ATIP sync pulse with respect to the subcode sync pulse can be exerted, and thereby the phase of the ATIP sync pulse and the phase of the subcode sync pulse can be matched. You can

[0031]

As described above, according to the first aspect of the present invention, the clock signal of the signal generating circuit and the clock signal synchronized with the absolute time information have first and second frequency division ratio variable functions, respectively. The frequency is divided by the frequency divider circuit 2 and supplied to the servo system circuit, and the phase difference detection circuit detects the phase delay or advance between the frame synchronization signal of the absolute time information and the frame synchronization signal of the control information. If the phase difference correction circuit delays the frame synchronization signal of the absolute time information with respect to the frame synchronization signal of the control information, the frequency division ratio in the second frequency division circuit is decreased, and if it is the other way around, By reducing the frequency division ratio in the frequency divider circuit of 1, the phase of the frame synchronization signal of the absolute time information is advanced or delayed with respect to the frame synchronization signal of the control information by the action of the servo system circuit. As a result, even if a signal generation circuit that does not have the function of synchronizing the phase between the frame sync signals is used except when recording is started, the phase shift between the frame sync signals due to the optical disc offset, scratch, dust, etc. can be detected. Yes, you can fix this.

According to the second aspect of the present invention, when the phase delay amount or the lead amount is large, the decrease amount of the frequency division ratio is not large, and when the phase delay amount or the lead amount is small, the minute division ratio is decreased. Since the reduction amount of the circumference ratio is reduced, the time required to match the phases can be shortened.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a phase synchronization circuit of an information recording / reproducing apparatus of the present invention.

FIG. 2 is a detailed circuit diagram of first and second frequency dividing circuits in FIG.

3 is a detailed circuit diagram of the phase difference detection circuit in FIG.

4 is a detailed circuit diagram of the phase difference correction circuit in FIG.

5 is a signal waveform diagram showing an example of the operation of the circuit of FIG.

6 is an enlarged view of a signal waveform showing an example of the operation of the circuit of FIG.

[Explanation of symbols]

10 ... 1st frequency divider circuit, 20 ... 2nd frequency divider circuit, 30 ...
Phase difference detection circuit, 40 ... Phase difference correction circuit.

Claims (2)

[Claims] 1. Absolute time information is recorded in advance in a recording area, wherein one frame includes a fixed number of bits and a predetermined position is composed of a number of consecutive frames composed of a bit string having a frame synchronization signal of a fixed pattern. Recording medium,
When recording control information composed of a number of frames each of which includes a fixed number of bits in one frame and a frame synchronization signal having a fixed pattern at a predetermined position, together with information such as audio and video, the recording medium A servo system for controlling the relative movement of the recording medium and the recording head with a clock signal synchronized with the absolute time information to be reproduced, and a clock signal of a signal generation circuit for generating control information together with the information such as audio and video. In the phase synchronization circuit of the information recording / reproducing apparatus that inputs to the circuit and records so that the phase is synchronized, it has a variable function of the division ratio, divides the clock signal of the signal generation circuit and supplies it to the servo system circuit And a second frequency dividing circuit having a function of varying the frequency dividing ratio and dividing the clock signal synchronized with the absolute time information and supplying it to the servo system circuit. A phase difference detection circuit that detects a phase delay or advance between the frame synchronization signal of absolute time information and the frame synchronization signal of control information, and the frame synchronization signal of absolute time information is delayed with respect to the frame synchronization signal of control information. If it is, the frequency division ratio in the second frequency dividing circuit is decreased, and if the frame synchronization signal of the absolute time information is ahead of the frame synchronization signal of the control information, the frequency division in the first frequency dividing circuit is performed. A phase synchronization circuit for an information recording / reproducing apparatus, comprising: a phase difference correction circuit for reducing the ratio. 2. When the phase delay amount or lead amount is large, the decrease amount of the frequency division ratio in the second or first frequency dividing circuit is not large, and when the phase delay amount or lead amount is small, Two
2. The phase synchronization circuit of the information recording / reproducing apparatus according to claim 1, wherein the amount of decrease in the frequency division ratio in the first frequency division circuit is reduced.