JPH0517775B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a power fluctuation detection device, and particularly to an impedance change rate relay that uses a digital computer to protect against power fluctuations occurring in a power system.

[Technical background of the invention and its problems] In recent years, interest in stable operation of power systems has particularly increased, and research in this field has been actively conducted. The most feared thing in power system operation is the collapse of the entire system due to a step-out phenomenon, and once a step-out phenomenon is detected, the system must be disconnected at the center point of the step-out or an appropriate point in its vicinity. It won't happen. Furthermore, if it is possible to detect as early as possible when a loss of synchronization is likely to occur and disconnect the system at an appropriate point early, the effect on the entire system will be small.

Generally, when a short circuit or ground fault occurs in a power system that is in steady operation, the power system becomes unstable. Particularly when the degree of agitation is large, the patient may lose his or her ability to recover, leading to loss of synchronicity.

Figure 1a shows the configuration of a power system with two equivalent power supplies. In the figure, A and B are each terminal, V _A , V _B
are the respective power supplies. FIG. 1b shows the voltage vectors at each terminal A and B when the system as shown in FIG. 1a loses synchronization. In other words, the A-terminal voltage V _A
When fixed, the B terminal voltage V _B begins to rotate around it.

FIG. 2 is a diagram showing a typical example of the voltage and current waveforms observed at each terminal during the step-out.

By the way, there are various types of protective relays for detecting such oscillation or step-out phenomenon, and FIGS. 3 and 4 show one example of one constructed using two distance relays and a timer.

FIG. 3 shows an example of the characteristics of a relay for detecting step-out. In the figure, the impedance seen by the relay is expressed by two circles A and B, Z1,
It is divided into three areas: Z2 and Z3. A shows the characteristic diagram of the motor relay (RY-A), and B shows the characteristic diagram of the offset motor relay (RY-B). Z3
is outside circle B, and the impedance seen by the relay is at Z3 under normal operating conditions. Also, Z1 is inside circle A, and the impedance seen by the relay at the time of a grid failure is at Z1. Z2 is between circle A and circle B. However, when the system goes out of synchronization, the impedance Zry seen by the relay traces a trajectory as shown in Figure 3, but the change is relatively slow, and Z3→
Changes from Z2 to Z1. Then, by moving to Z1 after staying in Z2 for a certain period of time,
It becomes possible to detect out-of-step phenomena.

Figure 4 shows the relay RY-A with the above characteristics A and B.
This figure shows a logic circuit for detecting synchronization using RY-B. In the figure, INH
is an inhibit circuit, TDE is an on-delay timer, FF is a flip-flop circuit, and AND1 is an AND circuit.

Now, the examples in Figures 3 and 4 are for detecting that the rate of change in impedance is within a certain range, but in recent years protection relays using digital computers, so-called digital relays, have been developed. An impedance change rate relay as shown in FIG. 5 is currently being considered. The relay shown in FIG. 5 detects the rate of change in impedance more directly and precisely than the relays shown in FIGS. 3 and 4. In the figure, 51 is a means for calculating the impedance change rate ΔZ/ΔT from the system voltage and current signals, and 52 is a means for calculating the impedance change rate ΔZ/ΔT from the system voltage and current signals. It is a means of detection.

K ₁ < ΔZ / ΔT < K ₂ ...(1) ΔT: Predetermined time width ΔZ: Change in impedance corresponding to ΔT K ₁ , K ₂ : Constants Now, the impedance of the power system as seen from the relay installation point The fluctuation in normal conditions is small, and the equation (1)
The value is smaller than the value of _K1 . On the other hand, changes in impedance due to system faults or system operations are steep, and the rate of change is greater than the value of K ₂ in equation (1). In the event of a step-out or system oscillation phenomenon, which is the purpose of the apparatus shown in FIG. 4, the impedance change rate will be an intermediate value, well within the range between the values of K ₁ and K ₂ .

Further, 53 is means for calculating the absolute value of impedance |Z| from the system voltage and current signals,
54 is a means for confirming that this |Z| is below a certain value K ₃ , and this constant K ₃ is a value smaller than the minimum value that the system impedance can take during normal times, and the impedance of the system during normal times is This is a means for locking the relay so that it will never produce an erroneous output due to a change, but this means is not essential to the invention. 55 is an AND gate, and 56 is an on-delay timer for confirming that the conditions 52 and 54 are satisfied and a certain period of time has elapsed.

FIG. 6 shows an example of the configuration of a digital relay for implementing the impedance change rate relay shown in FIG. In Figure 6, 61
Reference numerals a and 61b are input converters into which each phase voltage V and each phase current I of the power system 60 to be protected are introduced, and convert the input electrical quantity into a voltage signal of an appropriate magnitude. Filters 62a and 62b remove harmonic components contained in the outputs of the input converters 61a and 61b. Reference numeral 63 is a sample and hold circuit, and each filter 62a,
The output from 62b is sampled at predetermined intervals. 64 is an analog/digital (A/D) converter to which the output from the sample and hold circuit 63 is applied via a multiplexer 65 and converts it into digital data. 66 is a direct memory access (DMA) circuit,
An input of an A/D conversion circuit 64 is added. 67 is
A memory circuit that stores data input from the DMA circuit 66, and is a memory circuit that stores data input from the DMA circuit 66.
The output of the A conversion circuit 64 is written to a predetermined address. Reference numeral 68 is a read-only memory (ROM) in which programs and various constants are stored. 69 is an arithmetic circuit (CPU) to be described later, and 70 is an output circuit, which issues a shield breaker tripping command or display command as a relay output based on the calculation result of the CPU 69.

Now, when the function shown in the block diagram of FIG. 5 is expressed by the digital relay shown in FIG. 6, all programs for executing this function are stored in the ROM 68 in advance. The CPU 69 is a memory circuit 67
Using the system voltage and current data stored in
The impedance value Z is calculated according to the program stored in the ROM 68, and the functions shown in FIG. 5 are executed.

In the digital relay shown in Fig. 6, when realizing the impedance change rate relay shown in Fig. 5, the impedance change rate ΔZ/ΔT is calculated, and the value is determined according to the flowchart shown in Fig. 7 in order to determine the range. The method currently being considered is to run the program using

In other words, in FIG. 7, in step S71, the impedance value Zm calculated from the latest data,
Impedance value before n sampling points
The absolute value ΔZ of the difference from Zm−n is determined. step
In S72, it is determined whether the impedance change rate ΔZ/ΔT is within the range of predetermined values K ₁ and K ₂ using a known time width ΔT corresponding to n sampling intervals. As a result, if this condition is satisfied, it is determined in step S73 whether or not the condition in step S72 has been satisfied a predetermined value N or more times in succession. If it is repeated N times or more consecutively, the operating output of the relay is sent out in step S74. Further, if the number of consecutive cycles is not reached N, or if the condition of step S72 is not satisfied, the process moves to step S75 and no operational output of the relay is sent out. In this way, the entire calculation is executed every predetermined cycle J, and when the series of calculations is completed, the CPU 69 enters a standby state and waits for the timing to start the next calculation. From the above, it can be said that the flowchart of FIG. 7 is a method of fixing the denominator ΔT of the impedance change rate ΔZ/ΔT and detecting the numerator ΔZ.

FIG. 8 shows an equivalent block diagram when the functions realized by the flowchart of FIG. 7 are implemented using ordinary hardware. In the figure, 81 is a delay circuit that converts input Z(t) to time ΔT.
The output Z (t - ΔT) delayed by the amount of time is sent out. 8
2 is a differential circuit in which the absolute value of the difference between the input Z(t) and the output Z(t-ΔT) of the delay circuit 81 is ΔZ=|Z(t)-Z(t-
ΔT) | is output. 83 is a level detection circuit,
It is detected whether the value of ΔZ is in the range of ΔT·K ₁ <ΔZ<ΔT·K ₂ . Reference numeral 84 is a timer which sends out an operational output on the condition that the condition of the level detection circuit 83 continues for a certain period of time. In such a configuration,
Z(t) as Zm, or Z(t-ΔT) as Zm-n,
By making them equal, it can be seen that the block diagram of FIG. 8 has exactly the same function as the flowchart of FIG. 7.

Incidentally, impedance change rate relays that are generally intended for detecting system fluctuations and step-outs must have sufficient ability to identify system faults. FIG. 9a shows the response of the impedance change rate relay according to FIG. 7 at the time of a system fault. however,
For convenience, the absolute value of impedance Z is expressed as a scalar. In the figure, the solid line shows the change in impedance when a system fault occurs at time tO. In such a state, the impedance Zm after the accident and the impedance Zm before the accident are
When the calculation shown in FIG. 7 is executed using -n, the impedance change cannot be distinguished from that shown by the dotted line, and it is impossible to determine whether the change is gradual due to system oscillation or sudden change due to a system accident. Therefore, in order to avoid such a problem, it is sufficient to further determine the impedance change Zm+n-Zm at the next point in time and see whether the impedance change continues. If there is a system fault, as shown by the solid line, the impedance change will not continue, but if there is system oscillation, as shown by the dotted line, the impedance change will continue. In this way, by observing the changes in impedance a plurality of times, it is possible to clearly distinguish between a system fault and a system oscillation. Count function S in Figure 7
73 or the timer 84 in FIG. 8 has such an identification function.

As mentioned above, according to the flowchart in Figure 7, system accidents and system fluctuations can be reliably distinguished, but it is not necessarily an ideal method in terms of detection sensitivity and detection time of system fluctuations. I can not say. here,
The relationship between tilting motion and expected detection time/sensitivity will be examined using FIGS. 9b and 9c. FIG. 9b shows a case where the impedance value changes rapidly due to severe system fluctuation. In such cases, it is necessary to detect impedance changes as quickly as possible and perform appropriate system control. Also the 9th
Figure c shows a case where there is relatively slight system fluctuation and impedance changes are slow. In such a case,
The detection time is allowed to be relatively long. Therefore, applying the flowchart in Figure 7 to phenomena with such different properties and defining a common time step ΔT for impedance change detection will improve the detection sensitivity and detection time described above. cannot fully meet the needs of the power system.

In other words, if ΔT is chosen to be a sufficiently small value to achieve high-speed detection in preparation for sudden system fluctuations such as those shown in Figure 9b, the change will occur during ΔT when there is a slow change such as that shown in Figure 9c. The value of the impedance change ΔZ becomes small, and it becomes susceptible to various errors caused by the hardware shown in Figure 6, quantization errors during A/D conversion, etc., and is not sufficient to detect the impedance change. It is not possible to provide a certain level of sensitivity. Conversely, if the value of ΔT is set to a relatively large value in order to ensure sufficient detection sensitivity for slow phenomena such as the one shown in Figure 9c, it will be difficult to detect rapid phenomena such as that shown in Figure 9b. The detection time cannot be made fast enough.

From the above considerations, it is clear that the method in which the impedance change rate ΔZ/ΔT is detected by fixing the time width ΔT to a constant value, such as the method shown in the flowchart of FIG.
The detection sensitivity of the impedance change ΔZ cannot be kept constant for all impedance change phenomena, and it is difficult to say that it is an optimal relay.

[Objective of the Invention] The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to always maintain high sensitivity regardless of whether changes in power system impedance are rapid or slow. It is an object of the present invention to provide a highly reliable impedance change rate relay that can detect an impedance change and can also make the detection time faster for more rapid changes depending on the aspect of the impedance change.

[Summary of the Invention] In order to achieve the above object, the impedance change rate relay of the present invention includes a conversion means for converting a voltage signal and a current signal sampled from an electric power system into digital data and outputting the digital data; impedance calculation means for calculating the impedance value of the power system based on digital data, and time calculation means for calculating the time ΔT required for the impedance value calculated by the impedance calculation means to change by a predetermined magnitude _KZ . and determining means for determining whether the time ΔT calculated by the time calculating means is within a predetermined range, and the determining means determines that the time ΔT is within the predetermined range. In this case, the operating output of the relay is sent out.

[Embodiments of the Invention] The gist of the present invention is to calculate the impedance change rate ΔT/ΔZ of a power system by setting the impedance change ΔZ to a predetermined magnitude and measuring the time ΔT during which the impedance changes by ΔZ. It is what we are trying to measure.

An embodiment of the present invention shown in the drawings will be described below. FIG. 10 is a block diagram showing a configuration example in which the function of the CPU 69 in the impedance change rate relay according to the present invention is realized by hardware. Note that the other configurations are exactly the same as in FIG. 6.

In the figure, 101 is a sampling circuit that samples the calculated impedance value Z of the power system at a timing described later and stores it as _Z0 , and 102 is the output of this sampling circuit 101.
Difference between Z ₀ and the latest impedance value Z ΔZ = |Z
A difference circuit 103 outputting -Z ₀ | is a level detector which detects that the output ΔZ of the difference circuit 102 is larger than a predetermined value Kz, that is, ΔZ>Kz, and outputs "1". A timer 104 measures the period during which the output of the level detector 103 is "0" and outputs the measured value at the time when the output becomes "1" as ΔT. 105 is a level detector for the output ΔT of the timer 104, and the output ΔT is the set value.
It compares K _T1 and K _T2 and outputs “1” when K _T1 <ΔT<K _T2 . Reference numeral 106 denotes a counter, which outputs the operating output of the relay if the output of "1" from the level detector 105 is a predetermined number N or more consecutively. A timing delay circuit 107 receives the output of the level detector 103 and resets the timer 104 with a slight delay, thereby facilitating the operation of the level detector 105 at the next stage. The output of the level detector 103 not only serves as an input to the timer 104, but also provides the detection timing of the level detector 105 at the timing of inversion from "0" to "1", and also provides the count timing of the counter 106.
It provides timing for clearing the timer 104 and sampling for the sampling circuit 101, and creates a reference point in time for detecting the next impedance change rate ΔZ/ΔT. Furthermore, 108 is a timer, which is cleared by the output of the level detector 103. The function of this timer 108 is to provide sampling timing to the sampling circuit 101 on the condition that the output of the level detector 103 is not output for a certain period of time K _T2 or more, and also to provide a sampling timing to the timer 104 and the level detector 10.
5. Clears the counter 106.

Next, the operation of such an impedance change rate relay will be described using the flowchart shown in FIG. 11a. Note that this flowchart is entirely controlled by a clock, and calculations are repeated every time J. Furthermore, the impedance value of the power system is also updated with new data every time J.

First, in step S111, Zm is the latest impedance value, and _Z0 is the impedance value mJ hours ago. Therefore, ΔZ=|Zm−Z ₀ | means the change value during m·J time. step
In S112, the time ΔT from the time m=0 to the present is calculated as ΔT=m·J. Next step
In S113, the calculated value of ΔZ is compared with a predetermined set value Kz. As a result, if ΔZ<Kz, the process moves to step S1111 and after performing the processing described later, the calculation ends, and at the next calculation timing, the value ΔZ=Zm+ ₁ − Z ₀ is calculated in step S111. It turns out. Further, if ΔZ>Kz holds true above, the process moves to step S114, and the time ΔT from the sampling time of Z ₀ , that is, from the time N=0 to the present, is compared with predetermined set values K _T1 and K _T2 . As a result, if
If K _T1 <ΔT<K _T2 holds true, it is determined that the impedance change rate ΔZ/ΔT is within a predetermined range, and the process moves to step S115. And step S115
Then, the impedance change rate ΔZ/
Add 1 to the contents of a counter N that counts the number of operation determination results for ΔT. Next, step
In S117, the content of N that has been counted up is determined, and if it is greater than or equal to a predetermined value α, the process proceeds to step S118.
Sends out the operating output of the relay.

On the other hand, if the operating condition of ΔT is not satisfied in step S114, the contents of the counter N are cleared in step S116, and the process moves to step S119, in which the operating output of the relay is not transmitted. Further, even if the counter N has not reached the predetermined value α in step S117, the process moves to step S119 and no operational output of the relay is sent out. Furthermore, after making the determination in step S118 or step S119,
The latest impedance value Zm at step S1110
By updating the memory of Z ₀ and resetting the count value of m, the current point is set as the base point for impedance changes from the next time onwards. If ΔT>Kz does not hold in step S113, the value of ΔT is determined in step S1111. the result,
If this ΔT is smaller than K _T2 , the calculation is ended in step S1112 without any action, and the next m
Wait for the calculation to start at +1 point. If ΔT is larger than K _T2 , the process moves to step S116, and after going through the same process as described above, Z ₀ and m are determined in step S1110.
Update. Note that the function of step S1111 is to refresh the value of _Z0 , which is a reference for impedance changes, at regular intervals even in normal times when changes in impedance of the power system are small. Therefore, the value to be compared with ΔT is not necessarily limited to K _T2 .

Figures 11b and c show m in Figure 11a,
It shows the relationship between J, N, ΔZ, and ΔT. In the figure, the value of m is counted up every time J, and the value of ΔZ=|Zm−Z ₀ | is compared with a predetermined value Kz. Then, when ΔZ>Kz is established, m is cleared, Z ₀ is updated, and if ΔT=mJ is within a predetermined range, the value of the operation determination counter N is counted up.

Therefore, if Kz is selected to be as small as possible without being affected by various error components generated from hardware, then the desired impedance change can be detected using the set values of K _T1 and K ₂ . . In other words, in this case, the operating limits are set by the value of K _T1 for rapid impedance changes, and by the value of K _T2 for slow impedance changes. Also, the determination of count N is shown in Figure 9 a.
-c are used to distinguish between a system accident and system oscillation as described above, and α is normally selected to be about 2 to 3.

Sections 12a and 12b show the effects of the present invention. Figure a shows a case of a rapid impedance change, and figure b shows a case of a slow change, and the former shows a faster detection time and the latter shows a longer detection time for the same ΔZ setting. Therefore, according to the flowchart shown in Figure 11a,
By setting the detection sensitivity Kz of ΔZ to the smallest possible value within the range that is not affected by errors caused by hardware, impedance changes can always be detected with high sensitivity regardless of the systematic phenomenon.
Moreover, it is possible to realize an ideal impedance change rate relay that detects rapid impedance changes at high speed and detects slow changes relatively slowly.

In the above explanation, we did not particularly mention the process of calculating the impedance value Z from the voltage and current data V and I of the power system, but this is Z〓=V/Icosθ+j・V/Isinθ...(
2) It can be easily calculated using the well-known formula: V: grid voltage, I: grid current, θ: voltage/current position difference. In addition, in the above explanation, the impedance change ΔZ is expressed as ΔZ=|Zm−Zm−n|...(3) Zm: current impedance, Zm−Zn: impedance before n samplings, and so on, in the form of a vector difference between two vectors. However, the present invention can be applied in exactly the same way to the principle of detecting a scalar difference as shown in the following equation.

ΔZ=|Zm|−|Zm−n| ...(4) Furthermore, although _Z0 was updated with Zm in step S1110 of FIG. 11a, this strictly means that _Z0 = Zm
It doesn't have to be. That is, the same effect can be obtained with any data Zm-n between _Z0 and the latest value Zm. Also,
The memory update of Z ₀ in step S1110 is limited to cases in which ΔZ>Kz in step S113 or ΔT>K _T2 in step S1111 in FIG. 11a, but the timing of this Z ₀ update is For example, m
The present invention can be applied in exactly the same way even if the timing is delayed from the timing shown in the figure, such as at time +n.

[Effects of the Invention] As explained above, according to the present invention, impedance changes can be detected with high sensitivity regardless of whether the impedance changes in the power system are rapid or slow, and the detection time can be shortened. It is possible to provide a highly reliable impedance change rate relay that can be made faster for more rapid changes depending on the aspect of impedance change.

[Brief explanation of the drawing]

Figure 1a shows a two-terminal power system, Figure 1b
is a diagram showing the voltage vector at both ends at the time of step-out in Figure 1a, Figure 2 is a diagram showing the system voltage and current waveform at the time of step-out, and Figure 3 is an example of relay characteristics for detecting step-out. Figure 4 is a configuration diagram showing an example of a main relay for detecting step-out, Figure 5 is a conceptual diagram of an impedance change rate relay, and Figure 6 is a general configuration example of a digital impedance relay. 7 is a flowchart for explaining the conventional method, FIG. 8 is a functional block diagram for realizing the flowchart in FIG. 7, and FIG.
Figure a shows the difference in the appearance of impedance changes during system accidents and grid oscillations, Figures 9 b and c show impedance changes when system oscillations are rapid and slow, respectively, and Figure 10 11 is a functional block diagram showing an embodiment of the present invention, FIGS. 11a to 11c are diagrams for explaining the operation of the embodiment, and FIGS. 12a and b
2A and 2B are diagrams showing aspects of impedance change rate detection according to the present invention in cases where the system fluctuation is rapid and slow, respectively. 60...Power system, 61a, 61b...Input converter, 64...Analog-digital converter, 65
...Multiplexer, 66 ...DMA circuit, 67
... Memory circuit, 69 ... Arithmetic circuit, 70 ... Output circuit, 101 ... Sampling circuit, 102 ...
...Differential circuit, 103, 105...Level detector,
104, 108...timer, 106...counter, 107...delay circuit.

Claims (1)

[Claims] 1. Conversion means for converting voltage and current signals sampled from a power system into digital data and outputting the same; and calculating an impedance value of the power system based on the digital data output from the conversion means. impedance calculation means for calculating the time ΔT required for the impedance value calculated by the impedance calculation means to change by a predetermined magnitude K _Z ; and determining means for determining whether or not the time ΔT is within a predetermined range, and configured to transmit an operational output of the relay when the determining means determines that the time ΔT is within a predetermined range. An impedance change rate relay characterized by: