JPH05175443A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To form a CMOS, whose manufacturing steps can be shortened by providing the side-wall oxide films of the gate electrodes forming first-and second-conductivity type MOSs containing first-and second-conductivity type impurities, and providing the low-concentration impurity regions for the source and the drain formed by the diffusion from the oxide film. CONSTITUTION:A resist pattern 7 and a gate electrode 4 having a side-wall oxide film 6a are used as masks on an N-well region 2, and As is implanted. After the resist 7 is removed, heat treatment is performed, and N<+> type source and drain regions 8 are formed. Then, the resist pattern 7 and the gate electrode 4 having the side-wall oxide film 6a are used as masks on a P-well region 3, and BF2 is implanted. Then, P<+> type source and drain regions 9 are formed. N<-> type source and drain regions 12 are formed by the diffusion from the side wall 6a, which is formed of a PSG film. A P<-> type source and drain regions 13 are formed by the diffusion from a BSG film 10. Therefore, the patterning and ion implanting steps can be shortened to twice.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a LDD structure (Lightly Doped Drain) of CMOS and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of MOS semiconductor devices, a hot carrier phenomenon due to an increase in electric field in the vicinity of a drain has become a problem, and an LDD structure is adopted to suppress it.

2A to 2H are conventional CMOS LDDs.
FIG. 3 is a cross-sectional view showing an example of main steps in a method for manufacturing a structure, in which 1 is a single conductivity type silicon substrate and 2 is N.
Well region, 3 P well region, 4 gate electrode, 5 field oxide film, 7 resist, 8 N ⁺ type source / drain region, 9 P ⁺ type source / drain region, 12 N ⁻ Type source and drain regions, 13 is P ⁻
Type source and drain regions, 15 and 17 are CVD oxide films, 16 is silicate glass, 14 is a CVD oxide film, 1
Reference numeral 4a is a sidewall oxide film of the gate electrode.

Next, the manufacturing flow will be described. First,
An N well region 2, a P well region 3, a field oxide film 5 and a gate electrode 4 are formed on a one conductivity type silicon substrate 1 (FIG. 2 (a)).

Next, using the resist pattern 7 and the gate electrode 4 formed by patterning on the N well region 2 as a mask, 2E13 of phosphorus is implanted at 100 KeV, for example (FIG. 2B).

Next, after removing the resist, BF ₂ is injected by 1E13 at, for example, 40 KeV using the resist pattern 7 and the gate electrode 4 patterned on the P well region 3 as a mask (FIG. 2 (c)).

In order to prevent channeling, the phosphorus implantation and the BF ₂ implantation are performed at a slight angle, for example, at an angle of about 7 ° from a plane perpendicular to the substrate, so that shallow implantation is possible.

Next, after removing the resist, a CVD oxide film is deposited to a thickness of, for example, about 2000 Å (see FIG. 2).
(d)).

Next, the entire surface is etched back by anisotropic etching until the silicon surface is reached. At this time, the sidewall oxide film 14a is formed on the gate electrode (FIG. 2 (e)).

Then, using the resist pattern 7 patterned on the N well region 2 and the gate electrode 4 having the side wall oxide film 14a as a mask, As is, for example, 40 Ke.
Inject 4E15 with V (FIG. 2 (f)).

Then, after removing the resist, a heat treatment is performed, for example, to 90.
Performing at 0 ° C., N ⁺ type source / drain regions 8, N ⁻
After forming the p ^- type source / drain region 9 and the p ⁻ type source / drain region 13, the resist pattern 7 and the sidewall oxide film 14 patterned on the p-well region 3 are formed.
Using the gate electrode 4 having a as a mask, BF ₂ is implanted by 4E15 at 40 KeV (FIG. 2 (g)).

Next, after removing the resist, the CVD oxide film 1 is formed.
5, silicate glass 16 is sequentially deposited, and heat treatment is performed at, for example, 900 ° C. to flatten the silicate glass, and P ⁺ type source / drain regions 9 are formed. Thereafter, a CVD oxide film 17 is deposited to form an interlayer. The insulating film is completed (FIG. 2 (h)).

[0013]

In the conventional manufacturing method,
In the case of a CMOS having an LDD structure, a total of four times of patterning and implantation steps are required to form the source and drain regions.

Further, in forming N ^-- type and P ^-- type source and drain regions, when ion implantation is performed perpendicularly to the substrate, it is possible to penetrate deep into the substrate without colliding with crystal atoms. Due to the channeling effect, the transistor characteristics are significantly deteriorated. Therefore,
If the deviation from the plane perpendicular to the substrate is the implantation angle,
The injection angle is set to, for example, 7 ° to prevent channeling. However, due to this implantation angle, there is a problem that a shadowing effect in which the source and drain regions are asymmetrical appears and an asymmetrical transistor characteristic is generated.

The present invention has been made in order to solve the above problems, and reduces the number of patterning and implantation steps, and does not show the shadowing effect in the LD.
It is an object to provide a CMOS having a D structure and a manufacturing method thereof.

[0016]

In a semiconductor device and a method of manufacturing the same according to the present invention, a first conductivity type well region and a second conductivity type well region are formed on a silicon substrate, and a gate electrode is further formed. Forming a sidewall oxide film of the oxide film containing the first conductivity type impurity on the gate electrode, implanting the first conductivity type impurity only into the second conductivity type well region, and forming a high concentration first conductivity type source / drain Forming a region,
Implanting a second conductivity type impurity only into the first conductivity type region,
Forming high concentration second conductivity type source / drain regions, removing the sidewall oxide film on the first conductivity type region, and depositing on the source / drain regions of the first conductivity type well region; An oxide film containing a second conductivity type impurity is formed, and a heat treatment is performed to diffuse the oxide film containing the first conductivity type impurity and the second conductivity type impurity to obtain a low concentration first impurity.
A conductive type source / drain region and a low-concentration second conductive type source / drain region are formed.

The semiconductor device and the method of manufacturing the same according to the present invention include: a first conductivity type well region on a silicon substrate;
Forming a second conductive type well region and a gate electrode, and forming a sidewall oxide film of the oxide film containing the first conductive type impurity on the gate electrode; and forming a first conductive layer only in the second conductive type well region. Type impurities are implanted to form high-concentration first conductivity type source / drain regions, and second conductivity type impurities are implanted only into the first conductivity type region to form high-concentration second conductivity type source / drain regions. After removing the sidewall oxide film on the first conductivity type region, a sidewall oxide film made of an oxide film containing the second conductivity type impurity is formed on the gate electrode on the first conductivity type well region, and a heat treatment is performed. Diffusion from the sidewall oxide film by an oxide film containing the first conductivity type impurity and the second conductivity type impurity is performed to form a low concentration first conductivity type source,
The drain region and the low-concentration second conductivity type source and drain regions are formed.

[0018]

In the semiconductor device and the method of manufacturing the same according to the present invention, the sidewall oxide film of the gate electrode forming the first conductivity type MOS is made to be an oxide film containing impurities of the first conductivity type and the second conductivity type MOS is formed. An oxide film containing a second conductivity type impurity is deposited in the source / drain regions, or a sidewall oxide film of a gate electrode forming a first conductivity type MOS is formed into an oxide film containing a first conductivity type impurity. 2 conductivity type MOS
The side wall oxide film of the gate electrode forming the film is made to be the oxide film containing the second conductivity type impurity, and diffusion from the oxide film is performed to form the source and drain low concentration impurity regions of the CMOS having the LDD structure. As a result, the process can be greatly shortened and the shadowing effect can be eliminated.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 (a) to 1 (g) are cross-sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which 1 is a one conductivity type silicon substrate, 2 is an N well region, 3
Is a P well region, 4 is a gate electrode, 5 is a field oxide film, 6 is a PSG film, 7 is a resist, 8 is an N ⁺ type source / drain region, 9 is a P ⁺ type source / drain region, 1
0 is a BSG film, 12 is an N ⁻ type source / drain region, 1
3 is a P ⁻ type source / drain region, 16 is a silicate glass, 17 is a CVD oxide film, 6a is a sidewall oxide film of a gate electrode formed of a PSG film, and 10a is a sidewall oxide film of a gate electrode formed of a BSG film. Is.

Next, the manufacturing flow of the present invention will be described. First, as in the conventional case, the N well region 2, the P well region 3, the field oxide film 5 and the gate electrode 4 are formed on the one conductivity type silicon substrate 1. Next, the PSG film 6 is deposited, for example, 2000 to 3000 angstroms (FIG. 1 (a)).

Next, the entire surface is etched back by anisotropic etching until the silicon surface is reached. At this time, the sidewall oxide film 6a is formed on the gate electrode 4 (FIG. 1 (b)).

Next, using the resist pattern 7 patterned on the N well region 2 and the gate electrode 4 having the sidewall oxide film 6a as a mask, As is set to, for example, 40 KeV.
Then, 3-4E15 is injected (Fig. 1 (c)).

Next, after removing the resist 7, a heat treatment is performed at, eg, 900 ° C. to form the N ⁺ type source / drain regions 8, and then the resist pattern 7 and the sidewall oxide film patterned on the P well region 3 are formed. Using the gate electrode 4 having 6a as a mask, BF ₂ is added to, for example, 30 to 40 Ke.
Injection at 4E15 with V (FIG. 1 (d)).

Next, with the resist pattern 7 as it is,
The sidewall oxide film 6a on the N well region 2 is removed by dry etching (FIG. 1 (e)).

Next, after removing the resist 7, a BSG film 10 is deposited on the order of 4000 angstroms, for example (FIG. 1).
(f)).

Next, the silicate glass film 16 is applied to, for example, 4
After depositing about 000 angstroms, reflow is performed at 900 ° C. to planarize the BSG film 10 and the silicate glass film 16, and at the same time, the P ⁺ type source / drain regions 9 are formed and the PSG film is formed. Formation of N ⁻ type source / drain regions 12 by diffusion from the sidewall 6 a and P ⁻ by diffusion from the BSG film 10.
The source and drain regions 13 of the mold are formed, and then C
A VD oxide film 17 is deposited to complete an interlayer insulating film (FIG. 1 (g)).

As described above, according to this embodiment, the patterning and ion implantation steps can be shortened to a total of two, and the shadowing effect does not appear. Further, since the BSG film is used as it is for the interlayer insulating film, the manufacturing process can be further shortened.

Although the sidewall oxide film of the PSG film 6 is formed first in the above embodiment, the sidewall oxide film of the BSG film 10 may be formed first and the PSG film 6 may be used as the interlayer insulating film.

1 (h) and 1 (i) are sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

Similar to the first embodiment, the steps shown in FIG. 1F are formed. Next, the entire surface is etched back until it reaches the silicon surface, and the sidewall oxide film 10a formed of the BSG film is formed.
Are formed (FIG. 1 (h)).

Next, a CVD oxide film 15 and a silicate glass 16 are sequentially deposited, and a heat treatment is performed at 900 ° C. to flatten the silicate glass, and at the same time, a P ⁺ type source / drain region 9 is formed and a PSG film is formed. The formation of the N ⁻ type source / drain regions 12 by diffusion from the side wall oxide film 6a formed in step S6 and the formation of the P ⁻ type source / drain regions 13 by diffusion from the side wall oxide film 10a formed of the BSG film. Performed simultaneously, and then CVD oxide film 17
Is deposited to complete the interlayer insulating film (FIG. 1 (i)).

As described above, according to this embodiment, the patterning and ion implantation steps can be shortened to a total of two and the shadowing effect does not appear. Also, PMOS, N
By forming the sidewall oxide film on the gate electrode of both MOSs, the coverage of the interlayer insulating film can be improved.

Although the sidewall oxide film of the PSG film 6 is formed first in the above embodiment, the sidewall oxide film of the BSG film 10 may be formed first.

Although the PSG film and the BSG film are used in the first and second embodiments, the same effect can be obtained by using the N-type and P-type doped oxide films respectively. ..

[0035]

As described above, in the CMOS semiconductor device having the LDD structure and the method of manufacturing the same according to the present invention, the sidewall oxide film of the gate electrode forming the first conductivity type MOS is doped with the first conductivity type impurity. An oxide film containing the second conductivity type MOS is formed, and an oxide film containing the second conductivity type impurity is deposited in the source and drain regions forming the second conductivity type MOS.
The side wall oxide film of the gate electrode forming the first conductivity type MOS is an oxide film containing the first conductivity type impurity, and the side wall oxide film of the gate electrode forming the second conductivity type MOS is an oxide film containing the second conductivity type impurity. In this way, diffusion from the oxide film is performed to form the source and drain low-concentration impurity regions of the CMOS having the LDD structure, so that the patterning and ion implantation steps can be shortened to a total of two times. Moreover, there is an effect that the shadowing effect can be eliminated.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to first and second embodiments of the present invention.

FIG. 2 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 One conductivity type silicon substrate 2 N well region 3 P well region 4 Gate electrode 5 Field oxide film 6 PSG film 7 Resist 8 N ⁺ type source / drain region 9 P ⁺ type source / drain region 10 BSG film 12 N ⁻ type Source / drain region 13 P ^- type source / drain region 14 CVD oxide film 15 CVD oxide film 16 Silicate glass 17 CVD oxide film 6a Side wall of gate electrode formed of PSG film Oxide film 10a Side wall of gate electrode formed of BSG film Oxide film 14a Side wall oxide film of gate electrode formed of CVD oxide film

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[Procedure amendment]

[Submission date] January 26, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 3

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

Next, after removing the resist, the CVD oxide film 14 is formed.
Of about 2000 angstroms is deposited (FIG. 2 (d)).

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

[0010] The then the N-well region 2 resist pattern 7 was formed by patterning on, and the gate electrode 4 having a side <br/> wall oxide film 14a on the P-well region 3 in the mask A
4E15 is injected at 40 KeV (FIG. 2).
(f)).

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

Then, after removing the resist, a heat treatment is performed, for example, to 90.
Performing at 0 ° C., N ⁺ type source / drain regions 8, N ⁻
Type source / drain region 12 and P ⁻ type source / drain region 13 are formed , and then the resist pattern 7 and the N well region patterned on the P well region 3 are formed.
Using the gate electrode 4 having the sidewall oxide film 14a on the region 2 as a mask, BF ₂ is implanted at 4 Ke 15 at 40 KeV, for example (FIG. 2 (g )).

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

Further, in the formation of N ^- type and P ^- type source and drain regions, when ion implantation is carried out perpendicularly to the substrate, they penetrate deep into the substrate without colliding with crystal atoms, resulting in a channeling effect. Therefore, the transistor characteristics are significantly deteriorated. Therefore, assuming that the deviation from the plane perpendicular to the substrate is the implantation angle, the implantation angle is, for example, 7
Set to ° to prevent channeling. However, due to this implantation angle, there is a problem that a shadowing effect in which the source and drain regions are asymmetrical appears and an asymmetrical transistor characteristic is generated.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

[0016]

In a semiconductor device and a method of manufacturing the same according to the present invention, a first conductivity type well region and a second conductivity type well region are formed on a silicon substrate, and a gate electrode is further formed. Forming a sidewall oxide film of the oxide film containing the first conductivity type impurity on the gate electrode, implanting the first conductivity type impurity only into the second conductivity type well region, and forming a high concentration first conductivity type source / drain Forming a region,
Implanting a second conductivity type impurity only into the first conductivity type region,
Forming a high concentration second conductivity type source / drain region, removing the sidewall oxide film on the first conductivity type region, and depositing on the source / drain region of the first conductivity type well region; An oxide film containing a second conductivity type impurity is formed, and a heat treatment is performed to diffuse from the oxide film containing the first conductivity type impurity and the second conductivity type impurity.
A conductive type source / drain region and a low-concentration second conductive type source / drain region are formed.

[Procedure Amendment 8]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (4)

[Claims] 1. A CMOS semiconductor device having an LDD structure, comprising: a sidewall oxide film of a gate electrode forming a first conductivity type MOS, containing an impurity of a first conductivity type; and an oxide film containing an impurity of the first conductivity type. The source and drain low-concentration impurity regions formed by diffusion, the oxide film containing the second conductivity type impurities deposited in the source and drain regions forming the second conductivity type MOS, and the second conductivity type impurity A semiconductor device comprising a source / drain low-concentration impurity region formed by diffusion from an oxide film. 2. In a CMOS semiconductor device having an LDD structure, a sidewall oxide film of a gate electrode forming a first conductivity type MOS containing a first conductivity type impurity and a second conductivity type containing a second conductivity type impurity. A sidewall oxide film of a gate electrode forming a MOS, and source and drain low-concentration impurity regions formed by diffusion from the oxide film containing the first conductivity type impurity and the oxide film containing the second conductivity type impurity, respectively. A semiconductor device characterized by the above. 3. A step of forming a first conductivity type well region and a second conductivity type well region on a silicon substrate, and further forming a gate electrode, and an oxide film containing the first conductivity type impurity in the gate electrode. Forming a sidewall oxide film by the method of: forming a high-concentration first conductivity type source / drain region by implanting a first conductivity type impurity only in the second conductivity type well region; Second conductivity type impurities are implanted into
Forming high concentration second conductivity type source / drain regions, removing the sidewall oxide film on the first conductivity type regions, and depositing on the source / drain regions of the first conductivity type well regions. A step of forming an oxide film containing the second conductivity type impurity, and a heat treatment to diffuse the oxide film containing the first conductivity type impurity and the second conductivity type impurity to form a low concentration first conductivity type source, Drain region and low-concentration second conductivity type source,
And a step of forming drain regions, respectively. 4. A step of forming a first-conductivity-type well region and a second-conductivity-type well region on a silicon substrate, further forming a gate electrode, and oxidizing the gate electrode containing the first-conductivity-type impurity. Forming a sidewall oxide film of a film, implanting a first-conductivity-type impurity only in the second-conductivity-type well region, and forming high-concentration first-conductivity-type source / drain regions; Implanting the second conductivity type impurity only in the region,
Forming high concentration second conductivity type source / drain regions, removing the sidewall oxide film on the first conductivity type region, and forming the second conductivity on the gate electrode on the first conductivity type well region. A sidewall oxide film formed of an oxide film containing a second impurity, and a heat treatment to diffuse the sidewall oxide film from the oxide film containing the first conductivity type impurity and the second conductivity type impurity to form a low concentration first conductivity film. Forming a source region and a drain region and a low-concentration second conductivity type source region and a drain region, respectively.